From 23a074158e1e73f2829f54dab668c5ab9f7926c5 Mon Sep 17 00:00:00 2001
From: Bavyasritha Alahari <quic_alahari@quicinc.com>
Date: Sun, 14 May 2023 23:07:08 -0700
Subject: [PATCH] dt-bindings: soc: qcom: Add CRM device bindings

Add CESTA Resource manager (CRM) device bindings.

Change-Id: Id4178fc3eac332a61d1934bc784054b0266c24d9
Signed-off-by: Bavyasritha Alahari <quic_alahari@quicinc.com>
---
 bindings/soc/qcom/qcom,crm.yaml | 121 ++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,crm.yaml

diff --git a/bindings/soc/qcom/qcom,crm.yaml b/bindings/soc/qcom/qcom,crm.yaml
new file mode 100644
index 00000000..ecca5098
--- /dev/null
+++ b/bindings/soc/qcom/qcom,crm.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom-crm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) CRM bindings
+
+description:
+  Support for communication with the hardened-CRM blocks. A set of HW and
+  SW client DRVs in CRM provides interface to vote desired power state of
+  resources local to a subsystem.
+
+properties:
+  label:
+    $ref: /schemas/types.yaml#/definitions/string-array
+    maxItems: 1
+    oneOf:
+      - items:
+          - const: cam_crm
+          - const: pcie_crm
+      - description: Specifies the name of the CRM.
+
+  compatible:
+    enum:
+      - qcom,cam-crm
+      - qcom,pcie-crm
+
+  reg:
+    maxItems: 1
+    items:
+      - description: Should specify the base address for the CRM device.
+
+  reg-names:
+    maxItems: 1
+    items:
+      - const: base
+
+  interrupts:
+    maxItems: 1
+    items:
+      - description: SW drv vote completion IRQ.
+
+  interrupt-names:
+    maxItems: 1
+    oneOf:
+      - items:
+          - const: cam_crm
+          - const: pcie_crm
+
+  qcom,hw-drv-ids:
+    description: List of HW DRV IDs.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 3
+    items:
+      minimum: 0
+      maximum: 2
+
+  qcom,sw-drv-ids:
+    description: List of SW DRV IDs.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 2
+    items:
+      minimum: 0
+      maximum: 1
+
+  clocks:
+    maxItems: 1
+    items:
+      - description: Bus Clock
+
+required:
+  - label
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+
+oneOf:
+  - required:
+      - qcom,hw-drv-ids
+  - required:
+      - qcom,sw-drv-ids
+
+if:
+  required:
+      - qcom,sw-drv-ids
+then:
+  required:
+    - interrupts
+    - interrupt-names
+
+additionalProperties: false
+
+examples:
+  # Example of Camera CRM device with HW DRVs
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/qcom,camcc-kalama.h>
+    cam_crm: crm@add7000 {
+      label = "cam_crm";
+      compatible = "qcom,cam-crm";
+      reg = <0xadd7000 0x2000>;
+      clocks = <&camcc CAM_CC_DRV_AHB_CLK>;
+      qcom,hw-drv-ids = <0 1 2>;
+    };
+  # Example of PCIe CRM device with SW DRVs
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    pcie_crm: crm@1d01000 {
+      label = "pcie_crm";
+      compatible = "qcom,pcie-crm";
+      reg = <0x1d01000 0x3000>;
+      interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
+      interrupt-names = "pcie_crm";
+      clocks = <&pcie_0_pipe_clk>;
+      qcom,sw-drv-ids = <0>;
+    };
+...