From 23738ec11da8f88185a8f1f16a635164865ec3f5 Mon Sep 17 00:00:00 2001 From: Anil Veshala Veshala Date: Thu, 2 Nov 2023 03:43:29 -0700 Subject: [PATCH] ARM: dts: msm: add spi, i2c, gpi nodes for SVM SUN Adding spi, i2c, gsi nodes for SUN SVM. Change-Id: If3d1336379de8441e3ca2bae8da9449f2b410d53 Signed-off-by: Anil Veshala Veshala --- qcom/sun-qupv3.dtsi | 8 +-- qcom/sun-vm.dtsi | 167 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+), 4 deletions(-) diff --git a/qcom/sun-qupv3.dtsi b/qcom/sun-qupv3.dtsi index 3cd6b90f..55acb0ff 100644 --- a/qcom/sun-qupv3.dtsi +++ b/qcom/sun-qupv3.dtsi @@ -1025,8 +1025,8 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>; pinctrl-1 = <&qupv3_se15_i2c_sleep>; - dmas = <&gpi_dma2 0 7 3 64 0>, - <&gpi_dma2 1 7 3 64 0>; + dmas = <&gpi_dma2 0 7 3 64 2>, + <&gpi_dma2 1 7 3 64 2>; dma-names = "tx", "rx"; status = "disabled"; }; @@ -1050,8 +1050,8 @@ pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>, <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>; pinctrl-1 = <&qupv3_se15_spi_sleep>; - dmas = <&gpi_dma2 0 7 1 64 0>, - <&gpi_dma2 1 7 1 64 0>; + dmas = <&gpi_dma2 0 7 1 64 2>, + <&gpi_dma2 1 7 1 64 2>; dma-names = "tx", "rx"; spi-max-frequency = <50000000>; status = "disabled"; diff --git a/qcom/sun-vm.dtsi b/qcom/sun-vm.dtsi index a402927e..62ea85f6 100644 --- a/qcom/sun-vm.dtsi +++ b/qcom/sun-vm.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include / { @@ -104,6 +105,16 @@ vm-attrs = "crash-fatal", "context-dump"; + iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0 + 0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>; + + /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. + * QUP1_SE4: GPII5 : IRQ_316 + * QUP2_SE7: GPII5 : IRQ_625 + */ + gic-irq-ranges = <316 316 + 625 625>; /* PVM->SVM IRQ transfer */ + memory { #address-cells = <0x2>; #size-cells = <0x0>; @@ -432,6 +443,162 @@ msgq-label = <3>; }; + /* + * QUP1 : SE4 - Primary touch + * QUP2 : SE7 - Secondary touch + */ + qup_iommu_group: qup_common_iommu_group { + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + }; + + /* QUPv3_1 GPI Instance */ + gpi_dma1: qcom,gpi-dma@a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0xa00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0xac0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xb8 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Touchscreen I2C Instance */ + qupv3_se4_i2c: i2c@a90000 { + compatible = "qcom,i2c-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma1 0 4 3 64 0xc>, + <&gpi_dma1 1 4 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Touchscreen SPI Instance */ + qupv3_se4_spi: spi@a90000 { + compatible = "qcom,spi-geni"; + reg = <0xa90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma1 0 4 1 64 0xc>, + <&gpi_dma1 1 4 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + + /* QUPv3_2 GPI Instance */ + gpi_dma2: qcom,gpi-dma@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x800000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + qcom,max-num-gpii = <12>; + qcom,static-gpii-mask = <0x20>; + qcom,gpii-mask = <0x0>; + qcom,ev-factor = <1>; + qcom,gpi-ee-offset = <0x10000>; + qcom,le-vm; + status = "ok"; + }; + + /* QUPv3_2 wrapper instance */ + qupv3_2: qcom,qupv3_2_geni_se@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x8c0000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x438 0x0>; + qcom,iommu-group = <&qup_iommu_group>; + dma-coherent; + ranges; + status = "ok"; + + /* Secondary Tounch */ + qupv3_se15_i2c: i2c@89c000 { + compatible = "qcom,i2c-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&gpi_dma2 0 7 3 64 0xc>, + <&gpi_dma2 1 7 3 64 0xc>; + dma-names = "tx", "rx"; + qcom,le-vm; + status = "disabled"; + }; + + /* Secondary Tounch */ + qupv3_se15_spi: spi@89c000 { + compatible = "qcom,spi-geni"; + reg = <0x89c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + dmas = <&gpi_dma2 0 7 1 64 0xc>, + <&gpi_dma2 1 7 1 64 0xc>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,le-vm; + status = "disabled"; + }; + }; + qcom_smcinvoke { compatible = "qcom,smcinvoke"; };