From 7704cdcbcbf48c38ad875a69efb26d40d081febb Mon Sep 17 00:00:00 2001
From: Ankit Sharma <quic_anshar@quicinc.com>
Date: Wed, 11 Sep 2024 16:46:20 +0530
Subject: [PATCH] ARM: dts: msm: tuna: Add a node for cpufreq cycle counter
 driver

Add cpufreq cycle counter register information to devicetree in a
separate node for use by associated driver.

Change-Id: I5c57507acf6d4488402424619ac9d2ad356fb308
Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
---
 qcom/tuna-walt.dtsi | 24 ++++++++++++++++++++++++
 qcom/tuna.dtsi      |  1 +
 2 files changed, 25 insertions(+)
 create mode 100644 qcom/tuna-walt.dtsi

diff --git a/qcom/tuna-walt.dtsi b/qcom/tuna-walt.dtsi
new file mode 100644
index 00000000..ace295e6
--- /dev/null
+++ b/qcom/tuna-walt.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+	walt {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		qcom,cycle-cntr {
+			compatible = "qcom,epss";
+			reg = <0x17D91000 0x1000>,
+				<0x17D92000 0x1000>,
+				<0x17D93000 0x1000>,
+				<0x17D94000 0x1000>;
+			reg-names = "freq-domain0",
+				"freq-domain1",
+				"freq-domain2",
+				"freq-domain3";
+		};
+	};
+};
diff --git a/qcom/tuna.dtsi b/qcom/tuna.dtsi
index a26e7263..ea9150f7 100644
--- a/qcom/tuna.dtsi
+++ b/qcom/tuna.dtsi
@@ -1657,6 +1657,7 @@
 #include "tuna-qupv3.dtsi"
 #include "msm-rdbg.dtsi"
 #include "tuna-pmic-overlay.dtsi"
+#include "tuna-walt.dtsi"
 
 &qupv3_se7_2uart {
 	status = "ok";