From 4a4b8f110dd547a541329c27890090eda4abc69b Mon Sep 17 00:00:00 2001 From: Somesh Dey Date: Thu, 7 Nov 2024 12:03:19 +0530 Subject: [PATCH] ARM: dts: msm: Add correct pin functionality for ravelin pinctrl dtsi Adding correct pin functionality as per pinctrl table. Change-Id: I153d9f7114ce188eaec472be4b3acb3cdf3968d4 Signed-off-by: Somesh Dey --- qcom/ravelin-pinctrl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi index fad561c0..8959d50c 100644 --- a/qcom/ravelin-pinctrl.dtsi +++ b/qcom/ravelin-pinctrl.dtsi @@ -468,7 +468,7 @@ qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active { mux { pins = "gpio8"; - function = "qup0_se4_l0_mira"; + function = "qup0_se4_l0"; }; config { @@ -481,7 +481,7 @@ qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active { mux { pins = "gpio9"; - function = "qup0_se4_l1_mira"; + function = "qup0_se4_l1"; }; config { @@ -509,7 +509,7 @@ qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active { mux { pins = "gpio8"; - function = "qup0_se4_l0_mira"; + function = "qup0_se4_l0"; }; config { @@ -522,7 +522,7 @@ qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active { mux { pins = "gpio9"; - function = "qup0_se4_l1_mira"; + function = "qup0_se4_l1"; }; config {