From 202e2bbd82ce03f58435ca5025365444935b0706 Mon Sep 17 00:00:00 2001
From: Anaadi Mishra <quic_anaadim@quicinc.com>
Date: Tue, 23 Jul 2024 16:36:11 +0530
Subject: [PATCH] ARM: dts: msm: Add support for graphics clock controller on
 KERA

Add support for GPU clock controller and move corresponding
gdsc's from dummy to real on Kera platform.
While at it, add the clocks property to camera and display gdscs.

Change-Id: If3061a7603035e799e7548f0e2a93b7ded0e3005
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
---
 qcom/kera.dtsi | 29 +++++++++++++++++++++++++----
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/qcom/kera.dtsi b/qcom/kera.dtsi
index d39d3fdf..5d016158 100644
--- a/qcom/kera.dtsi
+++ b/qcom/kera.dtsi
@@ -1845,8 +1845,17 @@
 	};
 
 	gpucc: clock-controller@3d90000 {
-		compatible = "qcom,dummycc";
-		clock-output-names = "gpucc_clocks";
+		compatible = "qcom,kera-gpucc", "syscon";
+		reg = <0x3d90000 0xa000>;
+		reg-name = "cc_base";
+		vdd_cx-supply = <&VDD_CX_LEVEL>;
+		vdd_mx-supply = <&VDD_MX_LEVEL>;
+		clocks = <&rpmhcc RPMH_CXO_CLK>,
+			 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
+			 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
+		clock-names = "bi_tcxo",
+			      "gpll0_out_main",
+			      "gpll0_out_main_div";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -3080,26 +3089,32 @@
 #include "ipcc-test-no-slpi.dtsi"
 
 &cam_cc_ipe_0_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	status = "ok";
 };
 
 &cam_cc_ofe_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	status = "ok";
 };
 
 &cam_cc_tfe_0_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	status = "ok";
 };
 
 &cam_cc_tfe_1_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	status = "ok";
 };
 
 &cam_cc_tfe_2_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	status = "ok";
 };
 
 &cam_cc_titan_top_gdsc {
+	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	interconnects = <&mmss_noc MASTER_CAMNOC_HF &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
 	interconnect-names = "mmnoc";
 	parent-supply = <&VDD_CX_LEVEL>;
@@ -3107,11 +3122,13 @@
 };
 
 &disp_cc_mdss_core_gdsc {
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
 	status = "ok";
 };
 
 &disp_cc_mdss_core_int2_gdsc {
+	clocks = <&gcc GCC_DISP_AHB_CLK>;
 	parent-supply = <&VDD_CX_LEVEL>;
 	status = "ok";
 };
@@ -3161,13 +3178,17 @@
 };
 
 &gpu_cc_cx_gdsc {
-	compatible = "regulator-fixed";
 	reg = <0x3d99110 0x4>;
+	parent-supply = <&VDD_CX_LEVEL>;
+	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
+	clock-names = "ahb_clk";
 	status = "ok";
 };
 
 &gpu_cc_gx_gdsc {
-	compatible = "regulator-fixed";
+	parent-supply = <&VDD_GFX_LEVEL>;
+	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
+	clock-names = "ahb_clk";
 	status = "ok";
 };