samsung_sm8750/android_kernel_samsung_sm8750-devicetrees
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: dts: msm: Add M31 HS and QMP SS USB PHY configuration on sun

Browse Source 
Add M31 eUSB2 and QMP SS PHY nodes to sun. Add required dependencies in
pinctrl as well for HW based SS lane detection.

Change-Id: Ib1546aa7d92853a88a05d0bbc836ec4caac40960
Signed-off-by: Ronak Vijay Raheja <quic_rraheja@quicinc.com>
This commit is contained in:
Ronak Vijay Raheja
2023-11-01 16:09:58 -07:00
committed by Wesley Cheng
parent 7c6eec62b8
commit 1fb24b5e92
2 changed files with 270 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

241
qcom/sun-usb.dtsi
View File

@@ -3,6 +3,9 @@
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-sun.h>
#include <dt-bindings/phy/qcom,usb3-3nm-qmp-combo.h>
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
@@ -43,6 +46,7 @@
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
@@ -57,4 +61,241 @@
usb-role-switch;
};
};
/* USB port related High Speed PHY */
eusb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-m31-eusb2-phy";
reg = <0x88e3000 0x29C>,
<0x088e2000 0x4>,
<0x0c278000 0x4>;
reg-names = "eusb2_phy_base",
"eud_enable_reg",
"eud_detect_reg";
vdd-supply = <&pm_v8d_l2>;
qcom,vdd-voltage-level = <0 880000 880000>;
vdda12-supply = <&pm_v8g_l3>;
clocks = <&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB2_CLKREF_EN>;
clock-names = "ref_clk_src", "ref_clk";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
/* USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@88e8000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x88e8000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&pm_v8d_l2>;
qcom,vdd-voltage-level = <0 912000 912000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&pm_v8g_l3>;
usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
<&rpmhcc RPMH_CXO_PAD_CLK>,
<&tcsrcc TCSR_USB3_CLKREF_EN>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "global_phy_reset", "phy_reset";
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_default>;
qcom,qmp-phy-reg-offset =
<USB3_DP_PCS_PCS_STATUS1
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_DP_PCS_POWER_DOWN_CONTROL
USB3_DP_PCS_SW_RESET
USB3_DP_PCS_START_CONTROL
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
USB3_DP_COM_POWER_DOWN_CTRL
USB3_DP_COM_SW_RESET
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_AON_CLAMP_ENABLE>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value> based on tsmcn3e_USB3_Gen2_Seq v1.6 */
<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x04
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x16
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x01
USB3_DP_QSERDES_COM_HSCLK_SEL_1 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x0F
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x5C
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x0F
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xC0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x01
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x02
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x08
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x1A
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x41
USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x00
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x75
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x01
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x25
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x02
USB3_DP_QSERDES_COM_BG_TIMER 0x0A
USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
USB3_DP_QSERDES_COM_SSC_PER1 0x62
USB3_DP_QSERDES_COM_SSC_PER2 0x02
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0C
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x14
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x04
USB3_DP_QSERDES_COM_CORE_CLK_EN 0x20
USB3_DP_QSERDES_COM_CMN_CONFIG_1 0x16
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1 0xB6
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2 0x4A
USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3 0x36
USB3_DP_QSERDES_COM_ADDITIONAL_MISC 0x0C
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXA_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x11
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x31
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x20
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXA_GM_CAL 0x13
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0E
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x27
USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x0C
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x22
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x12
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xDA
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3F
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x19
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x09
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x91
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0xB7
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xAA
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXA_VTH_CODE 0x10
USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM 0x08
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x1F
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09
USB3_DP_QSERDES_TXB_LANE_MODE_1 0xF5
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x11
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x31
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x5F
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x05
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x06
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x0A
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x20
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
USB3_DP_QSERDES_RXB_GM_CAL 0x13
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0E
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x07
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x27
USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x0C
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x22
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x12
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xDA
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3F
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x19
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x09
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x91
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0xB7
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xAA
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
USB3_DP_QSERDES_RXB_VTH_CODE 0x10
USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1 0x14
USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM 0x08
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
USB3_DP_PCS_RX_SIGDET_LVL 0x99
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
USB3_DP_PCS_CDR_RESET_TIME 0x0A
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
USB3_DP_PCS_EQ_CONFIG1 0x4B
USB3_DP_PCS_EQ_CONFIG5 0x10
USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x68
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00>;
};
};