From 48f365b6cf50cbc464b6bad7965c95cc52563441 Mon Sep 17 00:00:00 2001 From: Anand Kulkarni Date: Mon, 6 May 2024 17:03:59 +0530 Subject: [PATCH 1/3] arm64: dts: qcom: monaco: Add devicetree files for monaco Add devicetree files with fastrpc property and context banks information for monaco target. Change-Id: Id98c632698dfcd0d33b5c6346ce940a726ee7067 Signed-off-by: Anand Kulkarni --- Kbuild | 4 +++ monaco/monaco-dsp.dts | 15 ++++++++++ monaco/monaco-dsp.dtsi | 65 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+) create mode 100644 monaco/monaco-dsp.dts create mode 100644 monaco/monaco-dsp.dtsi diff --git a/Kbuild b/Kbuild index 7d2ad2c1..58612c39 100644 --- a/Kbuild +++ b/Kbuild @@ -18,6 +18,10 @@ dtbo-y += sun/sun-dsp.dtbo endif endif +ifeq ($(CONFIG_ARCH_MONACO), y) +dtbo-y += monaco/monaco-dsp.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/monaco/monaco-dsp.dts b/monaco/monaco-dsp.dts new file mode 100644 index 00000000..9f088884 --- /dev/null +++ b/monaco/monaco-dsp.dts @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "monaco-dsp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Monaco SoC"; + compatible = "qcom,monaco"; + qcom,msm-id = <486 0x10000>, <517 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/monaco/monaco-dsp.dtsi b/monaco/monaco-dsp.dtsi new file mode 100644 index 00000000..7bef63cf --- /dev/null +++ b/monaco/monaco-dsp.dtsi @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&glink_edge { + qcom,fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + qcom,intents = <0x64 64>; + label = "adsp"; + memory-region = <&adsp_mem>; + qcom,vmids = <22 37>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x01C3 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <1>; /* ROOT_PD */ + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x01C4 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + qcom,nsessions = <5>; + dma-coherent; + pd-type = <3>; /* SENSORS_STATICPD */ + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x01C5 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <2>; /* AUDIO_STATICPD */ + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x01C6 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x01C7 0x0>; + qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>; + qcom,iommu-faults = "stall-disable"; + dma-coherent; + pd-type = <7>; /* USERPD */ + }; + }; +}; \ No newline at end of file From b8de1292e9f2773026dfe103fd614e28a4cac3a3 Mon Sep 17 00:00:00 2001 From: Himateja Reddy Date: Thu, 16 May 2024 16:45:29 -0700 Subject: [PATCH 2/3] arm64: dts: qcom: sun: Add SMMU pool configuration Add Unsigned PD pool configuration and allocation ranges property, used to pool multiple SMMU context banks with a fixed allocation ranges. This pool can be used by multiple Unsigned applications to offload to remote DSP subsystem and this removes the limitation of only allowing fixed number of Unsigned applications to offload to remote DSP subsystem. Change-Id: I3dc4309f4423aae7e68c743d129f9671a1ed96ca Signed-off-by: Himateja Reddy --- bindings/msm-fastrpc.txt | 3 +++ sun/sun-dsp.dtsi | 21 ++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/bindings/msm-fastrpc.txt b/bindings/msm-fastrpc.txt index 864db51f..f6f31c56 100644 --- a/bindings/msm-fastrpc.txt +++ b/bindings/msm-fastrpc.txt @@ -32,6 +32,9 @@ Subnode Required properties: - dma-coherent : A flag marking a context bank as I/O coherent - shared-cb : A value indicating how many fastrpc sessions can share a context bank +- pd-type : A value indicating remote subsystem proess type +- alloc-size-range: A pair values indicating the allocation size range + of context bank Example: qcom,msm_fastrpc { diff --git a/sun/sun-dsp.dtsi b/sun/sun-dsp.dtsi index 514ccc4f..d4cbd384 100644 --- a/sun/sun-dsp.dtsi +++ b/sun/sun-dsp.dtsi @@ -154,7 +154,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; }; compute-cb@6 { @@ -168,7 +169,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x4000000 0xFFFFFFFF>; }; compute-cb@7 { @@ -182,7 +184,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; }; compute-cb@8 { @@ -196,7 +199,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x1000000 0xFFFFFFFF>; }; compute-cb@9 { @@ -226,7 +230,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; compute-cb@11 { @@ -241,7 +246,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; compute-cb@12 { @@ -254,7 +260,8 @@ dma-coherent; qcom,iova-best-fit; qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ - pd-type = <7>; /* USERPD */ + pd-type = <9>; /* USER_UNSIGNEDPD_POOL */ + alloc-size-range = <0x0 0xFFFFFFFF>; }; }; }; \ No newline at end of file From 5ccc2af5ed713f1ef2739bcdb33a04da154de809 Mon Sep 17 00:00:00 2001 From: Edgar Flores Date: Tue, 28 May 2024 15:00:48 -0700 Subject: [PATCH 3/3] arm64: dts: msm: Add iova alignment flags for trusted dtsi Add iova-max-align-shift and iova-best-fit flags to maximize smmu allocation and minimize smmu fragmentation. Change-Id: Iaaab351ca5498a26243ecccd8392ec0bd1c9572c --- sun/sun-dsp-trustedvm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sun/sun-dsp-trustedvm.dtsi b/sun/sun-dsp-trustedvm.dtsi index e1c5db54..381f88c7 100644 --- a/sun/sun-dsp-trustedvm.dtsi +++ b/sun/sun-dsp-trustedvm.dtsi @@ -13,6 +13,8 @@ memory-region = <&fastrpc_gen_pool_region>; qcom,iommu-faults = "stall-disable", "HUPCF"; dma-coherent; + qcom,iova-best-fit; + qcom,iova-max-align-shift = <9>; /* Set MAX alignment to 2 MB*/ qrtr-gen-pool = <&fastrpc_compute_cb1>; frpc-gen-addr-pool = <0x8000 0x9000>; pd-type = <4>; /* SECURE_STATICPD */