From 3c6fce8da15d18e1d0cbbe3e0e5f4fa0391e4e54 Mon Sep 17 00:00:00 2001 From: Gerrit SelfHelp Service Account Date: Wed, 30 Aug 2023 23:57:38 -0700 Subject: [PATCH 001/242] Initial empty repository From 5da80fc64323b96df190abea081c9e8148bc9638 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Mon, 30 Oct 2023 13:24:40 +0800 Subject: [PATCH 002/242] ARM: dts: msm: Add devicetree changes for nt37801 display panel Add nt37801 command mode and video mode display panel support for dphy and cphy. Change-Id: I35426e4e67377b9e3c23443de7b2fc1a183dfa52 Signed-off-by: Yahui Wang --- ...-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 112 ++++++++++++++++++ .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 108 +++++++++++++++++ ...anel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 110 +++++++++++++++++ ...dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 107 +++++++++++++++++ 4 files changed, 437 insertions(+) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi new file mode 100644 index 00000000..eacca56f --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -0,0 +1,112 @@ +&mdss_mdp { + dsi_nt37801_amoled_cmd_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi new file mode 100644 index 00000000..92004657 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -0,0 +1,108 @@ +&mdss_mdp { + dsi_nt37801_amoled_cmd: qcom,mdss_dsi_nt37801_wqhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi new file mode 100644 index 00000000..65b22528 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -0,0 +1,110 @@ +&mdss_mdp { + dsi_nt37801_amoled_video_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_vid_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi new file mode 100644 index 00000000..0bab8128 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -0,0 +1,107 @@ +&mdss_mdp { + dsi_nt37801_amoled_video: qcom,mdss_dsi_nt37801_wqhd_plus_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; From 313d6ad6963325dab26ada7966825e06af736dad Mon Sep 17 00:00:00 2001 From: Varsha Suresh Date: Mon, 30 Oct 2023 09:11:18 -0700 Subject: [PATCH 003/242] ARM: dts: msm: add device tree files for sun target Add device tree files required for DPU driver on sun target. Move bindings for all mdp, dsi, panels, hdcp to opensource project. Change-Id: I1c6575313e33c5727f48ce94fe8b51cd9c62995d Signed-off-by: Varsha Suresh Signed-off-by: Veera Sundaram Sankaran --- Kbuild | 6 + Makefile | 9 + bindings/dsi.txt | 278 ++++++ bindings/mdss-dsi-panel.txt | 1005 ++++++++++++++++++++ bindings/msm_hdcp.txt | 14 + bindings/sde-dp.txt | 297 ++++++ bindings/sde-dsi.txt | 130 +++ bindings/sde-wb.txt | 23 + bindings/sde.txt | 1081 ++++++++++++++++++++++ display/sun-sde-common.dtsi | 335 +++++++ display/sun-sde-display-cdp-overlay.dts | 17 + display/sun-sde-display-cdp.dtsi | 7 + display/sun-sde-display-emulated.dtsi | 9 + display/sun-sde-display-mtp-overlay.dts | 17 + display/sun-sde-display-mtp.dtsi | 7 + display/sun-sde-display-rumi-overlay.dts | 17 + display/sun-sde-display-rumi.dtsi | 8 + display/sun-sde-display.dtsi | 26 + display/sun-sde.dts | 14 + display/sun-sde.dtsi | 88 ++ 20 files changed, 3388 insertions(+) create mode 100644 Kbuild create mode 100644 Makefile create mode 100644 bindings/dsi.txt create mode 100644 bindings/mdss-dsi-panel.txt create mode 100644 bindings/msm_hdcp.txt create mode 100644 bindings/sde-dp.txt create mode 100644 bindings/sde-dsi.txt create mode 100644 bindings/sde-wb.txt create mode 100644 bindings/sde.txt create mode 100644 display/sun-sde-common.dtsi create mode 100644 display/sun-sde-display-cdp-overlay.dts create mode 100644 display/sun-sde-display-cdp.dtsi create mode 100644 display/sun-sde-display-emulated.dtsi create mode 100644 display/sun-sde-display-mtp-overlay.dts create mode 100644 display/sun-sde-display-mtp.dtsi create mode 100644 display/sun-sde-display-rumi-overlay.dts create mode 100644 display/sun-sde-display-rumi.dtsi create mode 100644 display/sun-sde-display.dtsi create mode 100644 display/sun-sde.dts create mode 100644 display/sun-sde.dtsi diff --git a/Kbuild b/Kbuild new file mode 100644 index 00000000..78acba35 --- /dev/null +++ b/Kbuild @@ -0,0 +1,6 @@ +dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ + display/sun-sde-display-rumi-overlay.dtbo + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/bindings/dsi.txt b/bindings/dsi.txt new file mode 100644 index 00000000..a3f2fc10 --- /dev/null +++ b/bindings/dsi.txt @@ -0,0 +1,278 @@ +Qualcomm Technologies Inc. snapdragon DSI output + +DSI Controller: +Required properties: +- compatible: + * "qcom,mdss-dsi-ctrl" +- reg: Physical base address and length of the registers of controller +- reg-names: The names of register regions. The following regions are required: + * "dsi_ctrl" +- interrupts: The interrupt signal from the DSI block. +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: Phandles to device clocks. +- clock-names: the following clocks are required: + * "mdp_core" + * "iface" + * "bus" + * "core_mmss" + * "byte" + * "pixel" + * "core" + For DSIv2, we need an additional clock: + * "src" + For DSI6G v2.0 onwards, we need also need the clock: + * "byte_intf" +- assigned-clocks: Parents of "byte" and "pixel" for the given platform. +- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. +- vdd-supply: phandle to vdd regulator device node +- vddio-supply: phandle to vdd-io regulator device node +- vdda-supply: phandle to vdda regulator device node +- phys: phandle to DSI PHY device node +- phy-names: the name of the corresponding PHY device +- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) +- ports: Contains 2 DSI controller ports as child nodes. Each port contains + an endpoint subnode as defined in [2] and [3]. + +Optional properties: +- panel@0: Node of panel connected to this DSI controller. + See files in [4] for each supported panel. +- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. +- qcom,master-dsi: Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. +- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. +- pinctrl-names: the pin control state names; should contain "default" +- pinctrl-0: the default pinctrl state (active) +- pinctrl-n: the "sleep" pinctrl state +- ports: contains DSI controller input and output ports as children, each + containing one endpoint subnode. +- qcom,dsi-ctrl-shared: Boolean value indicating if the DSI controller is + shared between dual displays. + + DSI Endpoint properties: + - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's + input endpoint. For port@1, set to the MDP interface output. See [2] for + device graph info. + + - data-lanes: this describes how the physical DSI data lanes are mapped + to the logical lanes on the given platform. The value contained in + index n describes what physical lane is mapped to the logical lane n + (DATAn, where n lies between 0 and 3). The clock lane position is fixed + and can't be changed. Hence, they aren't a part of the DT bindings. See + [3] for more info on the data-lanes property. + + For example: + + data-lanes = <3 0 1 2>; + + The above mapping describes that the logical data lane DATA0 is mapped to + the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 + to phys DATA1 and logic DATA3 to phys DATA2. + + There are only a limited number of physical to logical mappings possible: + <0 1 2 3> + <1 2 3 0> + <2 3 0 1> + <3 0 1 2> + <0 3 2 1> + <1 0 3 2> + <2 1 0 3> + <3 2 1 0> + +DSI PHY: +Required properties: +- compatible: Could be the following + * "qcom,dsi-phy-28nm-hpm" + * "qcom,dsi-phy-28nm-lp" + * "qcom,dsi-phy-20nm" + * "qcom,dsi-phy-28nm-8960" + * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-10nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. +- reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_regulator" + For DSI 14nm and 10nm PHYs: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" +- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). +- power-domains: Should be <&mmcc MDSS_GDSC>. +- clocks: Phandles to device clocks. See [1] for details on clock bindings. +- clock-names: the following clocks are required: + * "iface" + For 28nm HPM/LP, 28nm 8960 PHYs: +- vddio-supply: phandle to vdd-io regulator device node + For 20nm PHY: +- vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: +- vcca-supply: phandle to vcca regulator device node + For 10nm PHY: +- vdds-supply: phandle to vdds regulator device node + +Optional properties: +- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY + regulator is wanted. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + +- frame-threshold-time-us: For command mode panels, this specifies the idle + time for dsi controller where no active data is + send to the panel, as controller is done sending + active pixels. If there is no desired DSI clocks + specified, then clocks will be derived from this + threshold time, which has a default value in chipset + based on the CPU processing power. + +- dsi_pll_codes: Contain an u32 array data to store dsi pll codes which were passed + from UEFI. +- qcom,dsi-phy-shared: Boolean value indicating if the DSI phy is shared + between dual displays. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/graph.txt +[3] Documentation/devicetree/bindings/media/video-interfaces.txt +[4] Documentation/devicetree/bindings/display/panel/ + +Example: + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus", + "byte", + "core", + "core_mmss", + "iface", + "mdp_core", + "pixel"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; + + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + qcom,dsi-ctrl-shared; + + qcom,mdss-mdp-transfer-time-us = <12000>; + frame-threshold-time-us = <800>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; + + dsi_phy0: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy-regulator-ldo-mode; + qcom,panel-allow-phy-poweroff; + qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; + qcom,panel-force-clock-lane-hs; + pll_codes_region = <&dsi_pll_codes_data>; + qcom,dsi-phy-shared; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt new file mode 100644 index 00000000..c65c61e1 --- /dev/null +++ b/bindings/mdss-dsi-panel.txt @@ -0,0 +1,1005 @@ +QTI mdss-dsi-panel + +mdss-dsi-panel is a dsi panel device which supports panels that +are compatible with MIPI display serial interface specification. + +Required properties: +- compatible: This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + This property specifies the version + for DSI HW that this panel will work with + "qcom,dsi-panel-v2" = DSI V2.0 +- status: This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + A string that has to be set to "okay/ok" + to enable the panel driver. By default this property + will be set to "disable". Will be set to "ok/okay" + status for specific platforms. +- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that + this panel will be mapped to. +- qcom,mdss-dsi-panel-width: Specifies panel width in pixels. +- qcom,mdss-dsi-panel-height: Specifies panel height in pixels. +- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel. + 3 = for rgb111 + 8 = for rgb332 + 12 = for rgb444 + 16 = for rgb565 + 18 = for rgb666 + 24 = for rgb888 +- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel. + "display_1" = DISPLAY_1 + "display_2" = DISPLAY_2 +- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY + timing settings for the panel. +- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane + timing settings for the panel. +- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: Message flags + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: Message flags + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are + sent after displaying an image. +- qcom,platform-reset-gpio: Specifies the reset gpio of primary display, not required for simulation panels. + +Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in +qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, +then 3 options can be tried. + 1. Send the packet as a long packet instead + Byte 0: dcs data type = 05 (DCS short Packet) + Byte 0: dcs data type = 29 (DCS long Packet) + 2. Send the packet in one burst by prepending with the next packet in packet stream + Byte 3 = 00 (indicates this is an individual packet) + Byte 3 = 40 (indicates this will be appended to the next + individual packet in the packet stream) + 3. Prepend a NULL packet to the short packet and send both in one burst instead of + combining multiple short packets and sending them in one burst. + +Optional properties: +- cell-index: Timing node index to help driver maintain the device tree ordering. +- qcom,platform-sec-reset-gpio: Specifies the reset gpio of secondary display. +- qcom,platform-bklight-en-gpio: Specifies the gpio for enabling backlight. +- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel +- qcom,vid-on-commands: same as "qcom,mdss-dsi-on-command" except commands are + only sent for video mode. +- qcom,vid-on-commands-state: String that specifies the ctrl state for sending panel on commands. + for video mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,cmd-on-commands: same as "qcom,mdss-dsi-on-command" except commands are + only sent for command mode. +- qcom,cmd-on-commands-state: String that specifies the ctrl state for sending panel on commands. + for command mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-physical-type: A string used as a decriptive type of the panel. + "oled" : That indicate it's an OLED panel. + "lcd" : That indicate it's an LCD panel. + If it is not set, consider it is a LCD panel as default. +- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane + timing settings for the panel. This is specific to SDE DRM driver. + The value of 'n' depends on the DSI PHY h/w revision and parsing this + property properly will be taken care in the DSI PHY DRM driver. +- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. +- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. +- qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch. +- qcom,poms-align-panel-vsync: Boolean used to align panel TE with timing engine vsync in POMS +- qcom,mdss-dsi-bpp-switch: Boolean used to enable bpp mode switch for non-DSC modes. +- qcom,mdss-dsi-bpp-mode: Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" is set. + 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. + 30 = for rgb101010. +- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. + Expressed as power of 2. To set as 128 lines, + this should be set to 7. +- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction. +- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3 + compression. +- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel. + Specified color order is used as default value. +- qcom,mdss-dsi-fbc-packing: Component packing. + 0 = default value. +- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation. +- qcom,mdss-dsi-fbc-bias: Bias for CD. + 0 = default value. +- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode. +- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode. +- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode. +- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget. + 0 = default value. +- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level. + 0 = default value. +- qcom,mdss-dsi-fbc-block-budget: Per block budget. + 0 = default value. +- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold. + 0 = default value. +- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value. + 0 = default value. +- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error. + 0 = default value +- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width. + 2 = default value. +- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value. + 0 = default value. +- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel. + 6 = default value. +- qcom,mdss-dsi-v-pulse-width: Vertical pulse width. + 2 = default value. +- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel. + 0 = default value +- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel. + 0 = default value +- qcom,mdss-dsi-v-top-border: Vertical top border in pixel. + 0 = default value +- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. + 0 = default value +- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the + panel under flow color. + 0xff = default value. +- qcom,mdss-dsi-border-color: Defines the border color value if border is present. + 0 = default value. +- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator + and denominator. It contains two u32 values - numerator + followed by denominator. The jitter configurition causes + the early wakeup if panel needs to adjust before vsync. + Default jitter value is 2.0%. Max allowed value is 10%. +- qcom,dsi-wd-jitter-enable: Boolean used to enable watchdog jitter in simulator panels +- qcom,dsi-wd-ltj-max-jitter: A u32 pair with numerator and denominator specifying the + maximum jitter over a long time. +- qcom,dsi-wd-ltj-time-sec: A u32 value to specify the time over which the jitter increases. +- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to + calculate the backoff time of rsc. + Default value is 16 lines. Max allowed value is vtotal. +- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically. +- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate. + "dfps_suspend_resume_mode"= FPS change request is + implemented during suspend/resume. + "dfps_immediate_clk_mode" = FPS change request is + implemented immediately using DSI clocks. + "dfps_immediate_porch_mode_hfp" = FPS change request is + implemented immediately by changing panel horizontal + front porch values. + "dfps_immediate_porch_mode_vfp" = FPS change request is + implemented immediately by changing panel vertical + front porch values. +- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. +- qcom,dsi-supported-qsync-min-fps-list: The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be + set along with this property. +- qcom,qsync-mode-min-refresh-rate: This u32 property is used to define qsync min fps per timing node instead + of using same qsync min fps for different timing modes. For defining qsync min + fps per timing node, this property should be defined in all timing nodes or else + to define single qsync fps for all modes, + "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. + "qcom,qsync-enable" property should be set along with this property. +- qcom,dsi-qsync-avr-step-list: The u32 fps values in this optional list indicate the avr step + requirement for qsync/AVR video mode panels. When a late frame is triggered, + AVR will delay the trigger to ensure the frame transfer snaps to the next step + interval. The step rate must be a common multiple of refresh and min-fps rates. + The values in this list should correspond to the dfps-list with same indeces + when DFPS is used, or a single value which applies to all rates. +- qcom,dsi-qsync-mode-avr-step-fps: This u32 property is used to define avr step fps per timing node instead + of using same qsync avr step fps for different timing modes. + For defining avr step fps per timing node, this property should be defined + in all timing nodes or else to define single qsync avr step fps for all modes + use "qcom,mdss-dsi-qsync-avr-step-fps". +- qcom,dsi-qsync-avr-step-fps: A u32 entry to specify avr step rate supported by the panel. + "qcom,qsync-enable" property should be set along with this property. +- qcom,mdss-dsi-transfer-time-us-min Minimum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. + qcom,mdss-dsi-transfer-time-us must be greater than this value. +- qcom,mdss-dsi-transfer-time-us-max Maximum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. This time should not be + greater than vsync duration. + qcom,mdss-dsi-transfer-time-us must be less than this value. +- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. +- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh + rate is not specified, then the frame rate of the panel in + qcom,mdss-dsi-panel-framerate is used. +- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature + is supported. +- qcom,dsi-dyn-clk-type: A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. +- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight + control for this panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) +- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight + control for secondary panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) +- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip. +- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight. + Required if backlight pmic control type is PWM +- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel. + 0 = default value. +- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. + 255 = default value. +- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. +- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. +- qcom,mdss-brightness-max-level: Specifies the max brightness level supported. + 255 = default value. +- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. + "delay_until_first_frame" = Delay backlight update of the panel + until the first frame is received from the HW. +- qcom,mdss-dsi-interleave-mode: Specifies interleave mode. + 0 = default value. +- qcom,mdss-dsi-panel-type: Specifies the panel operating mode. + "dsi_video_mode" = enable video mode (default). + "dsi_cmd_mode" = enable command mode. +- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost. +- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration. +- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal + for command mode panel. By default, panel TE will be used to generate the vsync. +- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync. +- qcom,qsync-enable: Boolean property to indicate if qsync is enabled/disabled. +- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. + "qcom,qsync-enable" property should be set along with this property. +- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature. +- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature. +- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode. + 0 = TE through embedded dcs command + 1 = TE through TE gpio pin. (default) +- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command. + 1 = default value. +- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start. + 0x2c = default value. +- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue. + 0x3c = default value. +- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel. + 0 = Don't send hsa/he following vs/ve packet(default) + 1 = Send hsa/he following vs/ve packet +- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during + horizontal front porch (HFP) blanking period. +- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during + horizontal back porch (HBP) blanking period. +- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during + horizontal sync active (HSA) mode. +- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line + interleave flag needs to be enabled. +- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during + blanking low power period (BLLP) EOF mode. +- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during + blanking low power period (BLLP) mode. +- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode. + "non_burst_sync_pulse" = non burst with sync pulses (default). + "non_burst_sync_event" = non burst with sync start event. + "burst_mode" = burst mode. +- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666). + "tight" = Tight packing (default value). + "loose" = Loose packing. +- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier. + 0 = default value. +- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering. + "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) + "rgb_swap_rbg" = DSI_RGB_SWAP_RBG + "rgb_swap_brg" = DSI_RGB_SWAP_BRG + "rgb_swap_grb" = DSI_RGB_SWAP_GRB + "rgb_swap_gbr" = DSI_RGB_SWAP_GBR +- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled. +- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled. +- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled. +- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled. +- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch. + 0x00 = default value. +- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch. + 0x00 = default value. +- qcom,mdss-dsi-stream: Specifies the packet stream to be used. + 0 = stream 0 (default) + 1 = stream 1 +- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_te" = Software trigger and TE +- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_seof" = Software trigger and start/end of frame trigger. + "trigger_sw_te" = Software trigger and TE +- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel. + 60 = 60 frames per second (default) +- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz. + 0 = default value. +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + 14000 = default value. +- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds + to the physical width in the framebuffer information. +- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds + to the physical height in the framebuffer information. +- qcom,mdss-dsi-panel-test-pin: Specifies the panel test gpio. +- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel + (such as single-port/dual-port), if qcom,panel-mode-gpio + binding is defined in dsi controller. + "dual_port" = Set GPIO to LOW + "single_port" = Set GPIO to HIGH + "high" = Set GPIO to HIGH + "low" = Set GPIO to LOW + The default value is "dual_port". +- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid + tearing. Other tear-check properties are ignored if this property is present. + The below tear check configuration properties can be individually tuned if + tear check is enabled. +- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines. + The default value is 0xfff0. +- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded + at vsync edge. The reader pointer refers to the line number of + panel buffer that is currently being updated. + The default value is panel height. +- qcom,mdss-tear-check-sync-threshold-start: + Allows the first ROI line write to an panel when read pointer is + between the range of ROI start line and ROI start line plus this + setting. + The default value is 4. +- qcom,mdss-tear-check-sync-threshold-continue: + The minimum number of lines the write pointer needs to be + above the read pointer so that it is safe to write to the panel. + (This check is not done for the first ROI line write of an update) + The default value is 4. +- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is + added and write is kicked off if the read pointer falls within that + region. + The default value is panel height. +- qcom,mdss-tear-check-rd-ptr-trigger-intr: + Specify the read pointer value at which an interrupt has to be + generated. + The default value is panel height + 1. +- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the + timing of TE simulation with more precision. + The default value is 6000 with 60 fps. +- qcom,mdss-dsi-reset-sequence: An array that lists the + sequence of reset gpio values and sleeps + Each command will have the format defined + as below: + --> Reset GPIO value + --> Sleep value (in ms) +- qcom,partial-update-enabled: String used to enable partial + panel update for command mode panels. + "none": partial update is disabled + "single_roi": default enable mode, only single roi is sent to panel + "dual_roi": two rois are merged into one big roi. Panel ddic should be able + to process two roi's along with the DCS command to send two rois. + disabled if property is not specified. This property is specified + per timing node to support resolution restrictions. +- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating + additional idle time in dsi clock cycles that is needed + to compensate for smaller line width. +- qcom,partial-update-roi-merge: Boolean indicates roi combination is need + and function has been provided for dcs + 2A/2B command. This property is specified per timing node to support + resolution restrictions. +- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent + through the left DSI controller only in a dual-dsi configuration +- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel. +- qcom,mdss-dsi-panel-hdr-color-primaries: + Array of 8 unsigned integers denoting chromaticity of panel.These + values are specified in nits units. The value range is 0 through 50000. + To obtain real chromacity, these values should be divided by factor of + 50000. The structure of array is defined in below order + value 1: x value of white chromaticity of display panel + value 2: y value of white chromaticity of display panel + value 3: x value of red chromaticity of display panel + value 4: y value of red chromaticity of display panel + value 5: x value of green chromaticity of display panel + value 6: y value of green chromaticity of display panel + value 7: x value of blue chromaticity of display panel + value 8: y value of blue chromaticity of display panel +- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value + typical value becomes peak brightness. Value is specified in nits units. + To obtain real peak brightness, this value should be divided by factor of + 10000. +- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as + ratio of peak brightness to contrast. Value is specified in nits units. + To obtain real blackness level, this value should be divided by factor of + 10000. +- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11) + before issuing hardware reset line. +- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11 + mode. This master delay (t_init_delay as per DSI spec) should be sum + of DSI internal delay to reach fuctional after power up and minimum + delay required by panel to reach functional. +- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets. +- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. +- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. +- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. +- qcom,spr-pack-type: String to specify the SPR pack type of panel pixel layout + Expected string for the pack types supported by MDSS are, + "pentile", "rgbw", "yygm", "yygw" +- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its + left, top, width, height alignments and minimum width and + height values. This property is specified per timing node to support + resolution's alignment restrictions. +- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. +- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol, to read the panel status. + This value is used to kick in the ESD recovery. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload +- qcom,mdss-dsi-panel-status-command-mode: + String that specifies the ctrl state for reading the panel status. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-lp1-command: An optional byte stream to request low + power mode on a panel +- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra + low power mode on a panel +- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low + power and ultra low power panel modes +- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode +- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery. + "bta_check" = Uses BTA to check the panel status + "reg_read" = Reads panel status register to check the panel status + "reg_read_nt35596" = Reads panel status register to check the panel + status for NT35596 panel. + "te_signal_check" = Uses TE signal behaviour to check the panel status +- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values + for each of panel registers. Each length is corresponding to number of + returned parameters of register introduced in specification. +- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check + for each of register. + Some panel need only check the first few values returned from panel. + So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, + then just ignore this one. +- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register + which is used to check the panel status. The size of each array is the sum of + length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. + This can cover that Some panel may return several alternative values. +- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register + read that can be ignored before treating that the panel has gone bad. +- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports + dynamic switching from video mode to command mode + and vice versa. +- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch. + If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is + dynamic-switch-suspend-resume. + "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will + go blank during transition. + "dynamic-switch-immediate"= Switch on next frame update. Panel will + not go blank for this transition. + "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will + not go blank for this transition. +- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel + after panel has switch modes. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,cmd-mode-switch-out-commands: List of commands that need to be sent + to panel in order to switch out command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,cmd-mode-switch-out-commands-state: String that specifies the ctrl state for sending command mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,cmd-mode-switch-in-commands: List of commands that need to be sent + to panel in order to switch in command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,cmd-mode-switch-in-commands-state: String that specifies the ctrl state for sending command mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,video-mode-switch-out-commands: List of commands that need to be sent + to panel in order to switch out video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,video-mode-switch-out-commands-state: String that specifies the ctrl state for sending video mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,video-mode-switch-in-commands: List of commands that need to be sent + to panel in order to switch in video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,video-mode-switch-in-commands-state: String that specifies the ctrl state for sending video mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent, + either before or after switch commands during dynamic resolution + switch in DSC panels. If the property is not present, the default + behavior is to send PPS commands after the switch commands. +- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel + "180" = panel is flipped in both horizontal and vertical directions + "hflip" = panel is flipped in horizontal direction + "vflip" = panel is flipped in vertical direction +- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel + for any commands that we send. +- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. +- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. +- qcom,compression-mode: Select compression mode for panel. + "fbc" - frame buffer compression + "dsc" - display stream compression. + "vdc" - VESA display compression. + If "dsc" or "vdc" compression is used then config subnodes needs to be defined. +- qcom,panel-supply-entries: A node that lists the elements of the supply used to + power the DSI panel. There can be more than one instance + of this binding, in which case the entry would be appended + with the supply entry index. For a detailed description of + fields in the supply entry, refer to the qcom,ctrl-supply-entries + binding above. +- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only DSC rev 1(Major).1(Minor) + right now. +- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates + current SCR revision information supported by panel. +- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used + to drive data stream to DSI. + Default value is 1 and max value is 2. + 2 encoder should be used only if qcom,mdss-lm-split or + qcom,split-mode with pingpong-split is used. +- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height. +- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width. + Multiple of slice width should be equal to panel-width. + Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders + are used then minimum slice width is equal to panel-width/4. +- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet. +- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression. +- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression. +- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. +- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps + instead of standard dcs type 0x0A. +- qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only VDC rev 1(Major).2(Minor) + right now. +- qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. +- qcom,vdc-slice-height: An u32 value which indicates slice height. This should be at least 16 lines. +- qcom,vdc-slice-width: An u32 value which indicates slice width. This should be at least 64 pixels and + should also be a multiple of 8 +- qcom,vdc-slice-per-pkt: An u32 value indicates the slice per dsi packet. +- qcom,vdc-bit-per-component: An u32 value indicates the bits per component before compression. +- qcom,vdc-bit-per-pixel: An u32 value indicates the bits per pixel after compression. +- qcom,src-color-space: An u32 value indicating the source color space. It can either be RGB or YUV. + Default value is assumed to be RGB + 0 - RGB + 1 - YUV +- qcom,src-chroma-format: An u32 value indicating the source color space. It can either be 444, 420 or 422. + Default value is assumed to be 444 + 0 - 444 + 1 - 422 + 2 - 420 +- qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command + delay in milliseconds. If no value is specified, it chooses zero by default. +- qcom,display-topology: Array of u32 values which specifies the list of topologies available + for the display. A display topology is defined by a + set of 3 values in the order: + - number of mixers + - number of compression encoders + - number of interfaces + Therefore, the array should always contain a tuple of 3 elements. +- qcom,default-topology-index: An u32 value which indexes the topology set + specified by the node "qcom,display-topology" + to identify the default topology for the + display. The first set is indexed by the + value 0. +- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. +- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. +- qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels +- qcom,mdss-dsi-mdp-idle-ctrl-en: A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. +- qcom,mdss-dsi-mdp-idle-ctrl-len: An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. +- qcom,vert-padding-value: An u32 value indicating the second display height while using two displays + in shared display feature. + +Required properties for sub-nodes: None +Optional properties: +- qcom,dba-panel: Indicates whether the current panel is used as a display bridge + to a non-DSI interface. +- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name + is required if qcom,dba-panel is defined for the panel. +- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate + s/w delay while configuring the event timer wakeup logic. + +- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports. + Each child represents timings settings for a specific resolution. +- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional + to show proper display. +- qcom,mdss-dsi-video-mode: A boolean to indicates current timing can only work in video mode. +- qcom,mdss-dsi-cmd-mode: A boolean to indicates current timing can only work in command mode. + +Additional properties added to the second level nodes that represent timings properties: +- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default + timing configuration that will be used. +- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent + to panel when the resolution/timing switch happens dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. +- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode +- qcom,dsi-dyn-clk-list: An u32 array of all the supported dsi bit clock + frequencies in Hz for the given mode, listed in + order of preference. +- qcom,disable-rsc-solver: Timing node property to dynamically disable RSC solver for + high FPS usecase due to lower bitclk rate. + +Note, if a given optional qcom,* binding is not present, then the driver will configure +the default values specified. + +Example: +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-pixel-packing = <0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-fbc-enable; + qcom,mdss-dsi-panel-mode-switch; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-bpp-switch; + qcom,mdss-dsi-fbc-slice-height = <5>; + qcom,mdss-dsi-fbc-2d-pred-mode; + qcom,mdss-dsi-fbc-ver2-mode; + qcom,mdss-dsi-fbc-bpp = <0>; + qcom,mdss-dsi-fbc-packing = <0>; + qcom,mdss-dsi-fbc-quant-error; + qcom,mdss-dsi-fbc-bias = <0>; + qcom,mdss-dsi-fbc-pat-mode; + qcom,mdss-dsi-fbc-vlc-mode; + qcom,mdss-dsi-fbc-bflc-mode; + qcom,mdss-dsi-fbc-h-line-budget = <0>; + qcom,mdss-dsi-fbc-budget-ctrl = <0>; + qcom,mdss-dsi-fbc-block-budget = <0>; + qcom,mdss-dsi-fbc-lossless-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-threshold = <0>; + qcom,mdss-dsi-fbc-rgb-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; + qcom,mdss-dsi-fbc-max-pred-err = <2>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <1>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = < 15>; + qcom,mdss-brightness-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-interleave-mode = <0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-last-line-interleave; + qcom,mdss-dsi-traffic-mode = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = <0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-mdp-trigger = <0>; + qcom,mdss-dsi-dma-trigger = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 2e 06 08 05 03 04 a0]; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 FF 99]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; + qcom,dsi-qsync-avr-step-list = <0 360 660>; + qcom,dsi-qsync-avr-step-fps = <360>; + qcom,min-refresh-rate = <30>; + qcom,max-refresh-rate = <60>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; + qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; + qcom,mdss-pan-physical-width-dimension = <60>; + qcom,mdss-pan-physical-height-dimension = <140>; + qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; + qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; + qcom,mdss-tear-check-sync-init-val = <1280>; + qcom,mdss-tear-check-sync-threshold-start = <4>; + qcom,mdss-tear-check-sync-threshold-continue = <4>; + qcom,mdss-tear-check-start-pos = <1280>; + qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; + qcom,mdss-tear-check-frame-rate = <6000>; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-init-delay-us = <100>; + mdss-dsi-rx-eot-ignore; + mdss-dsi-tx-eot-append; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <8>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 B0 03]; + qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B + 15 01 00 00 00 00 02 C2 08]; + qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; + qcom,send-pps-before-switch; + qcom,panel-ack-disabled; + qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, + <40 120 128>, + <128 240 64>; + qcom,mdss-dsi-panel-orientation = "180" + qcom,mdss-dsi-panel-jitter = <0x8 0x10>; + qcom,mdss-dsi-panel-prefill-lines = <0x10>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,compression-mode = "dsc"; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,platform-reset-gpio = <&tlmm 0 0>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,mdss-dsi-display-timings { + wqhd { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-bpp-mode = <24>; + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <728>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <424000000>; + qcom,mdss-mdp-transfer-time-us = <12500>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-mdp-transfer-time-us-min = <10000>; + qcom,mdss-mdp-transfer-time-us-max = <15000>; + qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2a>; + qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 00 00 00 00 00 02 B0 04 + 29 00 00 00 00 00 02 F1 00]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,qsync-mode-min-refresh-rate = <48>; + qcom,dsi-qsync-mode-avr-step-fps = <360>; + qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + + qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + + qcom,vert-padding-value = <2940>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <4 4 2 2 20 20>; + }; + }; + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <0>; + qcom,vdc-version = <0x12>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; + }; +}; diff --git a/bindings/msm_hdcp.txt b/bindings/msm_hdcp.txt new file mode 100644 index 00000000..8d5f55d7 --- /dev/null +++ b/bindings/msm_hdcp.txt @@ -0,0 +1,14 @@ +MSM HDCP driver + +Standalone driver managing HDCP related communications +between TZ and HLOS for MSM chipset. + +Required properties: + +compatible = "qcom,msm-hdcp"; + +Example: + +qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; +}; diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt new file mode 100644 index 00000000..fb48ae98 --- /dev/null +++ b/bindings/sde-dp.txt @@ -0,0 +1,297 @@ +Qualcomm Technologies, Inc. +sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. +DP Controller: Required properties: +- compatible: Should be "qcom,dp-display". +- reg: Base address and length of DP hardware's memory mapped regions. +- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. +- cell-index: Specifies the controller instance. +- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs) +- clocks: Clocks required for Display Port operation. +- clock-names: Names of the clocks corresponding to handles. Following clocks are required: + "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", + "link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk". +- vdda-1p2-supply: phandle to vdda 1.2V regulator node. +- vdda-0p9-supply: phandle to vdda 0.9V regulator node. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DSI block. +- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. +- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. +- qcom,mst-enable: MST feature enable control node. +- qcom,dsc-feature-enable: DSC feature enable control node. +- qcom,fec-feature-enable: FEC feature enable control node. +- qcom,qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask +- qcom,qos-cpu-latency-us: A u32 value indicating desired PM QoS CPU latency in usec +- qcom,altmode-dev: Phandle for the AltMode GLink driver. +- usb-controller: Phandle for the USB controller. +- qcom,pll-revision: PLL hardware revision. +- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. +- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. +- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. +- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. +- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. +- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types" + can be "core", "ctrl", "pll" and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off + +msm_ext_disp is a device which manages the interaction between external +display interfaces, e.g. Display Port, and the audio subsystem. + +Optional properties: +- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' + properties. The 'DISP_CC' ID of the clock must be used to enable + the property for the respective clock, whereas a value of zero + disables the property. +- vdd_mx-supply: phandle to vdda MX regulator node +- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. +- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. +- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. +- qcom,ext-disp: phandle for msm-ext-display module +- compatible: Must be "qcom,msm-ext-disp" +- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node +- qcom,phy-version: Phy version +- qcom,pn-swap-lane-map: P/N swap configuration of each lane +- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node + Refer to pinctrl-bindings.txt +- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl + device node. Refer to pinctrl-bindings.txt +- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. +- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one +- qcom,hbr-rbr-voltage-swing: Specifies the voltage swing levels for HBR and RBR rates. +- qcom,hbr-rbr-pre-emphasis: Specifies the pre-emphasis levels for HBR and RBR rates. +- qcom,hbr2-3-voltage-swing: Specifies the voltage swing levels for HBR2 and HBR3 rates. +- qcom,hbr2-3-pre-emphasis: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. + +[Optional child nodes]: These nodes are for devices which are +dependent on msm_ext_disp. If msm_ext_disp is disabled then +these devices will be disabled as well. Ex. Audio Codec device. + +- ext_disp_audio_codec: Node for Audio Codec. +- compatible : "qcom,msm-ext-disp-audio-codec-rx"; + +Example: + +ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; +}; + +sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt new file mode 100644 index 00000000..db92a23d --- /dev/null +++ b/bindings/sde-dsi.txt @@ -0,0 +1,130 @@ +Qualcomm Technologies, Inc. + +mdss-dsi is the master DSI device which supports multiple DSI host controllers +that are compatible with MIPI display serial interface specification. + +DSI Controller and PHY: +Required properties: +- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported + versions include 2.4, 2.5, and 2.6. + eg: qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, + qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5, + qcom,dsi-ctrl-hw-v2.6 + And for dsi phy driver: + qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, + qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 +- reg: List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. +- reg-names: A list of strings that name the list of regs. + "dsi_ctrl" - DSI controller memory region. + "disp_cc_base" - Base address of disp_cc memory region. + "mdp_intf_base" - Base address of mdp_intf memory region. +- cell-index: Specifies the controller instance. +- clocks: Clocks required for DSI controller operation. +- clock-names: Names of the clocks corresponding to handles. Following + clocks are required: + "mdp_core_clk" + "iface_clk" + "core_mmss_clk" + "bus_clk" + "byte_clk" + "pixel_clk" + "core_clk" + "byte_clk_rcg" + "pixel_clk_rcg" +- pll-label Supported versions of DSI PLL: + dsi_pll_5nm +- gdsc-supply: phandle to gdsc regulator node. +- vdda-supply: phandle to vdda regulator node. +- vcca-supply: phandle to vcca regulator node. +- interrupt-parent phandle to the interrupt parent device node. +- interrupts: The interrupt signal from the DSI block. +- qcom,dsi-default-panel: Specifies the default panel. +- qcom,mdp: Specifies the mdp node which can find panel node from this. +- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. + +Bus Scaling Data: +- qcom,msm-bus,name: String property describing MDSS client. +- qcom,msm-bus,num-cases: This is the number of bus scaling use cases + defined in the vectors property. This must be + set to <2> for MDSS DSI driver where use-case 0 + is used to remove BW votes from the system. Use + case 1 is used to generate bandwidth requestes + when sending command packets. +- qcom,msm-bus,num-paths: This represents number of paths in each bus + scaling usecase. This value depends on number of + AXI master ports dedicated to MDSS for + particular chipset. +- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt. + DSI driver should always set average bandwidth + (ab) to 0 and always use instantaneous + bandwidth(ib) values. + +Optional properties: +- label: String to describe controller. +- qcom,platform-te-gpio: Specifies the gpio used for TE. +- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer. +- qcom,dsi-ctrl: handle to dsi controller device +- qcom,dsi-phy: handle to dsi phy device +- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel +- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel +- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel +- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel +- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel +- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel +- qcom,dsi-display-list: Specifies the list of supported displays. +- qcom,dsi-manager: Specifies dsi manager is present +- qcom,dsi-display: Specifies dsi display is present +- qcom,hdmi-display: Specifies hdmi is present +- qcom,dp-display: Specified dp is present +- qcom,-supply-entries: A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. +- qcom,dsi-phy-pll-bypass: A boolean property that enables bypassing hardware access in DSI + PHY/PLL drivers to allow the DSI driver to run on emulation platforms + that might be missing those modules. +- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller. +- ports: This video port is used when external bridge is present. + The connection is modeled using the OF graph bindings + specified in Documentation/devicetree/bindings/graph.txt. + Video port 0 reg 0 is for the bridge output. The remote + endpoint phandle should be mipi_dsi_device device node. +- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. +- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. +- qcom,ssc-frequency-hz: Integer property to specify the spread frequency + to be programmed for the SSC. +- qcom,ssc-ppm: Integer property to specify the Parts per Million + value of SSC. +- qcom,avdd-regulator-gpio: Specifies the gpio pin used for avdd + power supply regulator. diff --git a/bindings/sde-wb.txt b/bindings/sde-wb.txt new file mode 100644 index 00000000..90093e41 --- /dev/null +++ b/bindings/sde-wb.txt @@ -0,0 +1,23 @@ +Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display + +Required properties: +- compatible: "qcom,wb-display" + +Optional properties: +- cell-index: Index of writeback device instance. + Default to 0 if not specified. +- label: String to describe this writeback display. + Default to "unknown" if not specified. + +Example: + +/ { + ... + + sde_wb: qcom,wb-display { + compatible = "qcom,wb-display"; + cell-index = <2>; + label = "wb_display"; + }; + +}; diff --git a/bindings/sde.txt b/bindings/sde.txt new file mode 100644 index 00000000..c088ece5 --- /dev/null +++ b/bindings/sde.txt @@ -0,0 +1,1081 @@ +Qualcomm Technologies, Inc. SDE KMS + +Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user +interface to different panel interfaces. SDE driver is the core of +display subsystem which manage all data paths to different panel interfaces. + +Required properties +- compatible: Must be "qcom,sde-kms" +- compatible: "msm-hdmi-audio-codec-rx"; +- reg: Offset and length of the register set for the device. +- reg-names : Names to refer to register sets related to this device +- clocks: List of Phandles for clock device nodes + needed by the device. +- clock-names: List of clock names needed by the device. +- mmagic-supply: Phandle for mmagic mdss supply regulator device node. +- vdd-supply: Phandle for vdd regulator device node. +- interrupt-parent: Must be core interrupt controller. +- interrupts: Interrupt associated with MDSS. +- interrupt-controller: Mark the device node as an interrupt controller. +- #interrupt-cells: Should be one. The first cell is interrupt number. +- iommus: Specifies the SID's used by this context bank. +- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information. + A source pipe can be "vig", "rgb", "dma" or "cursor" type. + Number of xin ids defined should match the number of offsets + defined in property: qcom,sde-sspp-off. +- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets + are calculated from register "mdp_phys" defined in + reg property + "sde-off". The number of offsets defined here should + reflect the amount of pipes that can be active in SDE for + this configuration. +- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding + to the respective source pipes. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-sspp-off. +- qcom,sde-ctl-off: Array of offset addresses for the available ctl + hw blocks within SDE, these offsets are + calculated from register "mdp_phys" defined in + reg property. The number of ctl offsets defined + here should reflect the number of control paths + that can be configured concurrently on SDE for + this configuration. +- qcom,sde-wb-off: Array of offset addresses for the programmable + writeback blocks within SDE. +- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding + to the respective writeback. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-wb-off. +- qcom,sde-mixer-off: Array of offset addresses for the available + mixer blocks that can drive data to panel + interfaces. These offsets are be calculated from + register "mdp_phys" defined in reg property. + The number of offsets defined should reflect the + amount of mixers that can drive data to a panel + interface. +- qcom,sde-dspp-top-off: Offset address for the dspp top block. + The offset is calculated from register "mdp_phys" + defined in reg property. +- qcom,sde-dspp-off: Array of offset addresses for the available dspp + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-pp-off: Array of offset addresses for the available + pingpong blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. +- qcom,sde-pp-slave: Array of flags indicating whether each ping pong + block may be configured as a pp slave. +- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block + connected to each pingpong, starting at 0. +- qcom,sde-merge-3d-off: Array of offset addresses for the available + merge 3d blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. +- qcom,sde-intf-off: Array of offset addresses for the available SDE + interface blocks that can drive data to a + panel controller. The offsets are calculated + from "mdp_phys" defined in reg property. The number + of offsets defined should reflect the number of + programmable interface blocks available in hardware. +- qcom,sde-mixer-blend-op-off Array of offset addresses for the available + blending stages. The offsets are relative to + qcom,sde-mixer-off. +- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with + mixer number corresponding to the array index. + +Optional properties: +- clock-rate: List of clock rates in Hz. +- clock-max-rate: List of maximum clock rate in Hz that this device supports. +- clock-mmrm: List of clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' properties. + The 'DISP_CC' ID of the clock must be used to enable the property for the + respective clock, whereas a value of zero disables the property. +- qcom,platform-supply-entries: A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + -- reg: offset and length of the register set for the device. + -- qcom,supply-name: name of the supply (vdd/vdda/vddio) + -- qcom,supply-min-voltage: minimum voltage level (uV) + -- qcom,supply-max-voltage: maximum voltage level (uV) + -- qcom,supply-enable-load: load drawn (uA) from enabled supply + -- qcom,supply-disable-load: load drawn (uA) from disabled supply + -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on + -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on + -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off + -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off +- qcom,sde-hw-version: A u32 value indicates the MDSS hw version +- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. +- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. +- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. +- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. +- qcom,sde-intf-size: A u32 value indicates the address range for each intf. +- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. +- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc. +- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. +- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. +- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. +- qcom,sde-pp-cwb: Array of u32 flags indicating whether each ping pong + block may be configured as a cwb pp block. +- qcom,sde-wb-size: A u32 value indicates the address range for each writeback. +- qcom,sde-len: A u32 entry for SDE address range. +- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on + each interface. +- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. +- qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. +- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width + for scaling purposes. +- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. +- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. +- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width + supported by WB for linear color formats. +- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. +- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for + alpha blending. +- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. +- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the + QSEED hardware block +- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. + It supports "csc" and "csc-10bit" entries for csc + type. +- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. +- qcom,sde-ubwc-version: Property to specify the UBWC feature version. A u32 UBWC version is based on MDSS support. +- qcom,sde-ubwc-static: Property to specify the default UBWC static + configuration value. +- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth + calculation algorithm +- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle + configuration value. +- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for + split display on smart panel. Possible values: + 0x0 - no alignment + 0xc - align at start of frame + 0xd - align at start of line +- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal + control feature is available on each source pipe. +- qcom,sde-has-src-split: Boolean property to indicate if source split + feature is available or not. +- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer + feature is available or not. +- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle + power collapse feature available or not. +- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. +- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction + feature available or not. +- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler + feature is available or not. +- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the + maximum input line width to destination scaler. +- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the + maximum output line width of destination scaler. +- qcom,sde-dest-scaler-top-off: A u32 value provides the + offset from mdp base to destination scaler block. +- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top +- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks + offset from destination scaler top offset. +- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block +- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off +- qcom,sde-sspp-clk-status: Array of offsets describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off. +- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle + support on each sspp. +- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe + priority of secondary rectangles when smart dma + is supported. Number of priority values should + match the number of offsets defined in + qcom,sde-sspp-off node. Zero indicates no support + for smart dma for the sspp. +- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version + supported on the device. Supported entries are + "smart_dma_v1" and "smart_dma_v2". +- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc. +- qcom,sde-intf-type: Array of string provides the interface type information. + Possible string values + "dsi" - dsi display interface + "dp" - Display Port interface + "hdmi" - HDMI display interface + An interface is considered as "none" if interface type + is not defined. +- qcom,sde-intf-tear-irq-off Array of offset addresses for the available + tear effect (TE) IRQ blocks from "mdp_phys". + There should be one entry per INTF instance with + a zero value for INTFs without TE IRQ block. +- qcom,sde-emulated-env: Boolean property to indicate if the MDSS is running in an + emulated environment. +- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. +- qcom,sde-cdm-off: Array of offset addresses for the available + cdm blocks. These offsets will be calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-vbif-off: Array of offset addresses for the available + vbif blocks. These offsets will be calculated from + register "vbif_phys" defined in reg property. +- qcom,sde-vbif-size: A u32 value indicates the vbif block address range. +- qcom,sde-uidle-off: A u32 value with the offset for the uidle + block, from the "mdp_phys". +- qcom,sde-uidle-size: A u32 value indicates the uidle block address range. +- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong. + This offset is 0x0 by default. +- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. +- qcom,sde-te-size: A u32 value indicates the te block address range. +- qcom,sde-te2-size: A u32 value indicates the te2 block address range. +- qcom,sde-dsc-off: Array of offset addresses for the available dsc + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. +- qcom,sde-dsc-hw-rev: A string value indicates the dsc hw block + version. +- qcom,sde-dsc-enc: Array of offset addresses for the available dsc + encoder blocks. These offsets are calculated from + the corresponding DSC base. +- qcom,sde-dsc-enc-size A u32 value indicates the enc block offset range. +- qcom,sde-dsc-ctl: Array of offset addresses for the available dsc + ctl blocks. These offsets are calculated from + the corresponding DSC base. +- qcom,sde-dsc-ctl-size A u32 value indicates the ctl block offset range. +- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc + block can support native 422 and native 420 + encoding. +- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width. +- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. + This offset is calculated from register "mdp_phys" + defined in reg property. +- qcom,sde-vdc-enc-size A u32 value indicates the enc block offset range. +- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is + calculated from qcom,sde-vdc-off. +- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is + calculated from qcom,sde-vdc-off. +- qcom,sde-vdc-ctl-size A u32 value indicates the ctl block offset range. +- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. +- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. +- qcom,sde-dither-version: A u32 value indicates the dither block version. +- qcom,sde-dither-size: A u32 value indicates the dither block address range. +- qcom,sde-cwb-dither: Array of u32 flags indicating whether each dither block + may be configured as a cwb dither block. +- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. There can + be more than one instance of this binding, in which case the + entry would be appended with the vcm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP VIG contains + that feature hardware. + e.g. qcom,sde-sspp-vig-blocks + -- vcm@0 + -- cell-index: A u32 index for the sub-block. + -- qcom,sde-vig-top-off: A u32 offset of the sub-block top. + -- qcom,sde-vig-csc-off: offset of CSC hardware + -- qcom,sde-vig-qseed-off: offset of QSEED hardware + -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler. + -- qcom,sde-vig-pcc: offset and version of PCC hardware + -- qcom,sde-vig-hsic: offset and version of global PA adjustment + -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware + -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware + -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware + -- qcom,sde-vig-inverse-pma: Boolean property to indicate if + inverse PMA feature is available on VIG pipe + -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware + -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware + -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware + -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware + -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC + IGC hardware + -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC + Unmult hardware + -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC + GC hardware + -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC + CSC hardware + -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC + Alpha Dither hardware +- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There + can be more than one instance of this binding, in which case the + entry would be appended with dgm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP DMA contains + that feature hardware. + e.g. qcom,sde-sspp-dma-blocks + -- dgm@0 + -- cell-index: A u32 index for the sub-block. + -- qcom,sde-dma-top-off: A u32 offset of the sub-block top. + -- qcom,sde-dma-igc: offset and version of DMA IGC + -- qcom,sde-dma-gc: offset and version of DMA GC + -- qcom,sde-dma-inverse-pma: Boolean property to indicate if + inverse PMA feature is available on DMA pipe + -- qcom,sde-dma-csc-off: offset of CSC hardware + -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware + -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware + -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware + -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware + -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC + IGC hardware + -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC + Unmult hardware + -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC + GC hardware + -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC + CSC hardware + -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC + Alpha Dither hardware +- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP RGB contains that feature hardware. + e.g. qcom,sde-sspp-rgb-blocks + -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware + -- qcom,sde-rgb-scaler-size: A u32 address range for scaler. + -- qcom,sde-rgb-pcc: offset and version of PCC hardware +- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The + block entries will contain the offset and version of each + feature block. The presence of a block entry indicates that + the DSPP contains that feature hardware. + e.g. qcom,sde-dspp-blocks + -- qcom,sde-dspp-pcc: offset and version of PCC hardware + -- qcom,sde-dspp-gc: offset and version of GC hardware + -- qcom,sde-dspp-igc: offset and version of IGC hardware + -- qcom,sde-dspp-hsic: offset and version of global PA adjustment + -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware + -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware + -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware + -- qcom,sde-dspp-dither: offset and version of dither hardware + -- qcom,sde-dspp-hist: offset and version of histogram hardware + -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware +- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the layer mixer contains that feature hardware. + e.g. qcom,sde-mixer-blocks + -- qcom,sde-mixer-gc: offset and version of mixer GC hardware +- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the + DSPP offset. Since AD hardware is represented as part of + DSPP block, the AD offsets must be offset from the + corresponding DSPP base. +- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware +- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) + version of the LTM hardware +- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the + DSPP offsets. Since LTM hardware is represented as part of + DSPP block, the LTM offsets are calculated based on the + corresponding DSPP base. +- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware. +- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. +- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. +- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. +- qcom,sde-dspp-rc-min-region-width: A u32 value indicating the RC block minimum region width. +- qcom,sde-dspp-spr-off: Array of u32 offsets indicate the SPR block offsets from the + corresponding DSPP block offset as base. +- qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range +- qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware. +- qcom,sde-dspp-demura-off: Array of u32 offsets indicate the demura block offsets from the + corresponding DSPP block offset as base. +- qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range +- qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware. +- qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. +- qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. +- qcom,sde-vbif-id: Array of vbif ids corresponding to the + offsets defined in property: qcom,sde-vbif-off. +- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit +- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit +- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the read limit to apply if the given + pps is not exceeded. +- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the write limit to apply if the given + pps is not exceeded. +- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0 +- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1 +- qcom,sde-wb-id: Array of writeback ids corresponding to the + offsets defined in property: qcom,sde-wb-off. +- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off +- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off +- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. +- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off +- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. +- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" + defined in reg property. +- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast + functionality in the register dma hardware block should be used. +- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding + to the LUTDMA block. +- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. +- qcom,sde-dram-channels: This represents the number of channels in the + Bus memory controller. +- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. +- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps + that can be supported without underflow. + This is a low bandwidth threshold which should + be applied in most scenarios to be safe from + underflows when unable to satisfy bandwidth + requirements. +- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps + that can be supported without underflow in the + event where there is no VFE. + This is a high bandwidth threshold which can be + applied in scenarios where panel interface can + be more tolerant to memory latency such as + command mode panels. +- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for + core ib calculation. +- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for + core clock calculation. +- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. +- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio + for each supported compressed format on realtime interface. + The string is composed of one or more of + /// + separated with spaces. +- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio + for each supported compressed format on non-realtime interface. + The string is composed of one or more of + /// + separated with spaces. +- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines. +- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines. +- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines. +- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines. +- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines. +- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines. +- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. +- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. +- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. +- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register + priority for realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register + priority for non-realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register + priority for concurrent writeback clients. First 8 entries are + for rp_remap and the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register + priority for lutdma client. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register + priority for cnoc clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register + priority for offline-wb clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. +- qcom,sde-vbif-qos-wb-rot-remap: This u32 array is used to program vbif qos remapper register + priority for wb-rotation clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. +- qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts + qos configuration for different refresh rates. +- qcom,sde-danger-lut: This u32 array of 18 cell property, with a format of + for each entry, + , indicating the danger luts on sspp and wb. +- qcom,sde-safe-lut: This u32 array of 18 cell property, with a format of + for each entry, + , indicating the safe luts on sspp and wb. +- qcom,sde-creq-lut: This u64 array of 18 cell property, with a format of + for each + entry, for qos cases from , with of-node count based + on the qos refresh rates count. +- qcom,sde-cdp-setting: Array of 2 cell property, with a format of + for cdp use cases in + order of , and . +- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. +- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. +- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. +- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. +- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used + for ipcc registers access. +- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline + rotation. +- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, + namely sspp or wb. Number of entries should match + the number of xin-ids defined in + property: qcom,sde-inline-rot-xin +- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of xin-ids defined in + property: qcom,sde-inline-rot-xin +- qcom,sde-secure-sid-mask: Array of secure SID masks used during + secure-camera/secure-display usecases. +- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0. +- #list-cells: Number of mdp cells, must be 1. +- qcom,sde-mixer-display-pref: A string array indicating the preferred display type + for the mixer block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display +- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block. + for CWB. Possible values: + "cwb" - preferred for cwb + "none" - no preference on display +- qcom,sde-mixer-dcwb-pref: A string array indicating the preferred mixer block. + for Dedicated-CWB. Possible values: + "dcwb" - preferred for dedicated-cwb + "none" - no preference on display +- qcom,sde-ctl-display-pref: A string array indicating the preferred display type + for the ctl block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display +- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe + ordering block + 0: lower priority pipe has to be on the left for a given pair of pipes. + 1: priority have to be explicitly configured for a given pair of pipes. +- qcom,sde-trusted-vm-env: Boolean property to indicate if the device + driver is executing in a trusted VM +- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment +- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment +- qcom,tvm-include-reg An array of u32 tuplets indicating the address + ranges of the display sub-device registers +- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes +- qcom,pmic-arb-address: A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. +- qcom,sde-ib-bw-vote: A u32 array of IB bandwidth vote values in kbps for + MNOC, LLCC and DDR/EBI respectively. +- qcom,sde-dnsc-blur-version: A u32 value indicating the downscale blur version +- qcom,sde-dnsc-blur-off: An array of u32 values with the offset for the downscale blur + block, from the "mdp_phys". +- qcom,sde-dnsc-blur-size: A u32 value indicates the downscale blur block address range. +- qcom,sde-dnsc-blur-gaus-lut-off: An array of u32 values with the offset for gaussian LUT + block, from the dnsc-blur-off +- qcom,sde-dnsc-blur-gaus-lut-size: A u32 value indicates the gaussian LUT block address range. +- qcom,sde-dnsc-blur-dither-off: An array of u32 values with the offset for dither + block, from the dnsc-blur-off +- qcom,sde-dnsc-blur-dither-size: A u32 value indicates the dither block address range. + +Bus Scaling: +- interconnects An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ +- interconnect-names An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus +- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. +- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, + instance id), of inline rotator device. + +SMMU Subnodes: +- smmu_sde_****: Child nodes representing sde smmu virtual + devices + +Subnode properties: +- compatible: Compatible names used for smmu devices. + names should be: + "qcom,smmu_sde_unsec": smmu context bank device + for unsecure sde real time domain. + "qcom,smmu_sde_sec": smmu context bank device + for secure sde real time domain. + "qcom,smmu_sde_nrt_unsec": smmu context bank device + for unsecure sde non-real time domain. + "qcom,smmu_sde_nrt_sec": smmu context bank device + for secure sde non-real time domain. + + +Please refer to ../../interrupt-controller/interrupts.txt for a general +description of interrupt bindings. + +Example: + mdss_mdp: qcom,mdss_mdp@900000 { + compatible = "qcom,sde-kms"; + reg = <0x00900000 0x90000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>, + <0x0aeac000 0x00f0>; + reg-names = "mdp_phys", + "vbif_phys", + "vbif_nrt_phys", + "regdma_phys"; + qcom,tvm-include-reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mdss_mdp_vote_clk>, + <&clock_mmss clk_smmu_mdp_axi_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_mdss_vsync_clk>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "iommu_clk", + "mmagic_clk", + "vsync_clk"; + clock-rate = <0>, <0>, <0>; + clock-max-rate= <0 320000000 0>; + clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; + mmagic-supply = <&gdsc_mmagic_mdss>; + vdd-supply = <&gdsc_mdss>; + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mdp_smmu 0>; + #power-domain-cells = <0>; + + qcom,sde-hw-version = <0x70000000>; + qcom,sde-emulated-env; + qcom,sde-off = <0x1000>; + qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + qcom,sde-mixer-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,sde-mixer-display-pref = "primary", "none", + "none", "none"; + qcom,sde-mixer-cwb-pref = "none", "none", + "cwb", "none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-off = <0x00055000 0x00057000>; + qcom,sde-dspp-ad-off = <0x24000 0x22800>; + qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-min-region-width = <20>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>: + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-wb-off = <0x00066000>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + qcom,sde-pp-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cdm-off = <0x0007a200>; + qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-sspp-type = "vig", "vig", "vig", + "vig", "rgb", "rgb", + "rgb", "rgb", "dma", + "dma", "cursor", "cursor"; + + qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 + 0x0000b000 0x00015000 0x00017000 + 0x00019000 0x0001b000 0x00025000 + 0x00027000 0x00035000 0x00037000>; + + qcom,sde-sspp-xin-id = <0 4 8 + 12 1 5 + 9 13 2 + 10 7 7>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; + qcom,sde-highest-bank-bit = <0x7 0x2>; + qcom,sde-ubwc-version = <0x10000000>; + qcom,sde-ubwc-static = <0x100>; + qcom,sde-ubwc-swizzle = <0>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xd>; + qcom,sde-panic-per-pipe; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-sspp-src-size = <0x100>; + qcom,sde-mixer-size = <0x100>; + qcom,sde-ctl-size = <0x100>; + qcom,sde-dspp-top-size = <0xc>; + qcom,sde-dspp-size = <0x100>; + qcom,sde-intf-size = <0x100>; + qcom,sde-dsc-size = <0x100>; + qcom,sde-cdm-size = <0x100>; + qcom,sde-pp-size = <0x100>; + qcom,sde-wb-size = <0x100>; + qcom,sde-dest-scaler-top-size = <0xc>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-len = <0x100>; + qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-sspp-scale-size = <0x100>; + qcom,sde-mixer-blendstages = <0x8>; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-highest-bank-bit = <15>; + qcom,sde-has-mixer-gc; + qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; + qcom,fullsize-va-map; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-sspp-max-rects = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-smart-dma-priority = <0 0 0 0 + 0 0 0 0 + 0 0 + 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-te-off = <0x100>; + qcom,sde-te2-off = <0x100>; + qcom,sde-te-size = <0xffff>; + qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, + <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, + 0xffff0000 0xffff0000>; + qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, + <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, + 0xff>; + qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 + 0x00112234 0x45566777 0x00112236 0x67777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>, + <0x02344455 0x56667777 0x02366677 0x77777777 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + + qcom,sde-vbif-off = <0 0>; + qcom,sde-vbif-id = <0 1>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <16>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-max-bw-high-kbps = <9000000>; + qcom,sde-max-bw-low-kbps = <9000000>; + + qcom,sde-core-ib-ff = "1.1"; + qcom,sde-core-clk-ff = "1.0"; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-undersized-prefill-lines = <4>; + qcom,sde-xtra-prefill-lines = <5>; + qcom,sde-dest-scale-prefill-lines = <6>; + qcom,sde-macrotile-prefill-lines = <7>; + qcom,sde-yuv-nv12-prefill-lines = <8>; + qcom,sde-linear-prefill-lines = <9>; + qcom,sde-downscaling-prefill-lines = <10>; + qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 + 2400000 2400000 2400000 2400000>; + qcom,sde-amortizable-threshold = <11>; + qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-broadcast-disabled = <0>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0xa00>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + /* Offset from vig top, version of HSIC */ + qcom,sde-vig-hsic = <0x200 0x00010000>; + qcom,sde-vig-memcolor = <0x200 0x00010000>; + qcom,sde-vig-pcc = <0x1780 0x00010000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x800>; + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-rgb-blocks { + qcom,sde-rgb-scaler-off = <0x200>; + qcom,sde-rgb-scaler-size = <0x74>; + qcom,sde-rgb-pcc = <0x380 0x00010000>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00010000>; + qcom,sde-dspp-pcc = <0x1700 0x00010000>; + qcom,sde-dspp-gc = <0x17c0 0x00010000>; + qcom,sde-dspp-hsic = <0x0 0x00010000>; + qcom,sde-dspp-memcolor = <0x0 0x00010000>; + qcom,sde-dspp-sixzone = <0x0 0x00010000>; + qcom,sde-dspp-gamut = <0x1600 0x00010000>; + qcom,sde-dspp-dither = <0x0 0x00010000>; + qcom,sde-dspp-hist = <0x0 0x00010000>; + qcom,sde-dspp-vlut = <0x0 0x00010000>; + }; + + qcom,sde-mixer-blocks { + qcom,sde-mixer-gc = <0x3c0 0x00010000>; + }; + + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + + qcom,sde-inline-rotator = <&mdss_rotator 0>; + qcom,sde-inline-rot-xin = <10 11>; + qcom,sde-inline-rot-xin-type = "sspp", "wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + }; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi new file mode 100644 index 00000000..55adf8f3 --- /dev/null +++ b/display/sun-sde-common.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000 + 0x4b000 0x4c000 0x0f0f + 0x0f0f 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none", + "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800 0x12800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000 0x3000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x65000 0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0xa 6>; + qcom,sde-wb-id = <1 2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x6e000 0x6f000 0x70000 0x71000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3 0x4 0x4 0x5 0x5>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000 0x52000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000 0x83000 0x83000 0x84000 0x84000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 4 3 6 5 8 7>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200 0x100 0x200 0x100 0x200>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80 0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 14 15>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <7 8 9 10 1 2 3 4 5 6>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7 10 9 12 11>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 + 4500000 4500000 + 4500000 4500000 + 4500000 4500000 + 4500000 4500000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5700000 5700000 + 5700000 5700000 + 5700000 5700000 + 5700000 5700000 + 5700000 5700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, <0x8330 0>, <0xa330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>, + <0x2c330 0>, <0x2e330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, <0x8334 0>, <0xa334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>, + <0x2c334 0>, <0x2e334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x3>, + <0x7 0x2>; + qcom,sde-ubwc-version = <0x50000001>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <17000000>; + qcom,sde-max-bw-high-kbps = <27000000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <4>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>; + qcom,sde-dspp-demura-size = <0xe4>; + qcom,sde-dspp-demura-version = <0x00020000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask-performance = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x0002801 0x0002c01>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00040000>; + qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; +}; + diff --git a/display/sun-sde-display-cdp-overlay.dts b/display/sun-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..ec9b2784 --- /dev/null +++ b/display/sun-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <1 0>; +}; + diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi new file mode 100644 index 00000000..dd810573 --- /dev/null +++ b/display/sun-sde-display-cdp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + diff --git a/display/sun-sde-display-emulated.dtsi b/display/sun-sde-display-emulated.dtsi new file mode 100644 index 00000000..28b440bf --- /dev/null +++ b/display/sun-sde-display-emulated.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..4a5ba68e --- /dev/null +++ b/display/sun-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <8 0>; +}; + diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi new file mode 100644 index 00000000..dd810573 --- /dev/null +++ b/display/sun-sde-display-mtp.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + diff --git a/display/sun-sde-display-rumi-overlay.dts b/display/sun-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..ce4c64c0 --- /dev/null +++ b/display/sun-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RUMI"; + compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi"; + qcom,msm-id = <618 0x10000>; + qcom,board-id = <15 0>; +}; + diff --git a/display/sun-sde-display-rumi.dtsi b/display/sun-sde-display-rumi.dtsi new file mode 100644 index 00000000..b5cf1f78 --- /dev/null +++ b/display/sun-sde-display-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" +#include "sun-sde-display-emulated.dtsi" + diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi new file mode 100644 index 00000000..da7270d2 --- /dev/null +++ b/display/sun-sde-display.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde.dtsi" +#include + +&soc { + sde_wb1: qcom,wb-display@1 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display1"; + }; + + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <1>; + label = "wb_display2"; + }; +}; + +&mdss_mdp { + connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>; +}; + diff --git a/display/sun-sde.dts b/display/sun-sde.dts new file mode 100644 index 00000000..d55ab390 --- /dev/null +++ b/display/sun-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde.dtsi" + +/ { + qcom,msm-id = <618 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi new file mode 100644 index 00000000..166f64f7 --- /dev/null +++ b/display/sun-sde.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "sun-sde-common.dtsi" + +&soc { + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 575000000 575000000 19200000 575000000>; + clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-dspp-ltm-version = <0x00010002>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + From 3f35daf3cf3a0b17b176acc1feb7a7d170bf521b Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Tue, 7 Nov 2023 17:11:43 +0800 Subject: [PATCH 004/242] ARM: dts: msm: add dp dt change for sun platform Add dp device tree change for sun platform. Change-Id: I56d1d7e542fa4de971d5803dc4a40a66ea34dcf3 Signed-off-by: Yahui Wang --- display/sun-sde.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 166f64f7..29d03668 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -12,6 +12,160 @@ #include "sun-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + }; + + sde_dp: qcom,dp_display@af54000 { + status = "disabled"; + cell-index = <0>; + compatible = "qcom,dp-display"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88ebc00 0x200>, + <0x88eb400 0x200>, + <0x88eb800 0x200>, + <0x88eb000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,pll-revision = "3nm-v1"; + qcom,phy-version = <0x800>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L3G>; + vdda-0p9-supply = <&L2D>; + vdda_usb-0p9-supply = <&L2D>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>, + <0x31 0x3e 0x3f 0xff>, + <0x36 0x3f 0xff 0xff>, + <0x3f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>, + <0x20 0x2e 0x35 0xff>, + <0x20 0x2e 0xff 0xff>, + <0x22 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>, + <0x29 0x39 0x3f 0xff>, + <0x30 0x3f 0xff 0xff>, + <0x3f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>, + <0x22 0x2e 0x36 0xff>, + <0x22 0x31 0xff 0xff>, + <0x24 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x800 0x2>; From d25f73950b893d50c0b6a95aaaa738ff9cdad171 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Wed, 1 Nov 2023 17:23:18 -0700 Subject: [PATCH 005/242] ARM: dts: msm: dsi: add legacy panels Adds device tree files for legacy panels Change-Id: Ifa8b590474663d1edd1aaa2ffe8b429041f3ae6a Signed-off-by: Kirill Shpin --- display/dsi-panel-sharp-dsc-4k-cmd.dtsi | 96 ++ display/dsi-panel-sharp-dsc-4k-video.dtsi | 89 + display/dsi-panel-sim-cmd-au.dtsi | 131 ++ display/dsi-panel-sim-cmd.dtsi | 1275 ++++++++++++++ display/dsi-panel-sim-dsc-10bit-cmd.dtsi | 1225 ++++++++++++++ display/dsi-panel-sim-dsc375-cmd.dtsi | 279 ++++ display/dsi-panel-sim-dualmipi-cmd.dtsi | 258 +++ .../dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 1458 +++++++++++++++++ display/dsi-panel-sim-dualmipi-video.dtsi | 64 + display/dsi-panel-sim-sec-hd-cmd.dtsi | 64 + display/dsi-panel-sim-video.dtsi | 66 + ...panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi | 360 ++++ ...nel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi | 123 ++ .../dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi | 552 +++++++ ...dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi | 129 ++ ...vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi | 159 ++ ...dr6130-qsync-dsc-fhd-plus-144hz-video.dtsi | 127 ++ 17 files changed, 6455 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-4k-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dsc-4k-video.dtsi create mode 100644 display/dsi-panel-sim-cmd-au.dtsi create mode 100644 display/dsi-panel-sim-cmd.dtsi create mode 100644 display/dsi-panel-sim-dsc-10bit-cmd.dtsi create mode 100644 display/dsi-panel-sim-dsc375-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi create mode 100644 display/dsi-panel-sim-dualmipi-video.dtsi create mode 100644 display/dsi-panel-sim-sec-hd-cmd.dtsi create mode 100644 display/dsi-panel-sim-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi new file mode 100644 index 00000000..4231b746 --- /dev/null +++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -0,0 +1,96 @@ +&mdss_mdp { + dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi new file mode 100644 index 00000000..a687b5ff --- /dev/null +++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -0,0 +1,89 @@ +&mdss_mdp { + dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-tx-eot-append; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-cmd-au.dtsi b/display/dsi-panel-sim-cmd-au.dtsi new file mode 100644 index 00000000..3815307f --- /dev/null +++ b/display/dsi-panel-sim-cmd-au.dtsi @@ -0,0 +1,131 @@ +&mdss_mdp { + dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au { + qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,vert-padding-value = <2940>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 07 FF + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi new file mode 100644 index 00000000..c10c3bce --- /dev/null +++ b/display/dsi-panel-sim-cmd.dtsi @@ -0,0 +1,1275 @@ +&mdss_mdp { + dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { + qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,panel-ack-disabled; + qcom,qsync-enable; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,cmd-on-commands = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + qcom,vid-on-commands = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + ]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0c + ]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 11 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0b + ]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 01 02 49 + ]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <110>; + qcom,mdss-dsi-h-back-porch = <110>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <90>; + qcom,mdss-dsi-v-front-porch = <110>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <840>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,disable-rsc-solver; + + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00]; + /* CABC brightness */ + + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <240>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,disable-rsc-solver; + + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@8 { + cell-index = <8>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@9 { + cell-index = <9>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <1>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@10 { + cell-index = <10>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <5>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@11 { + cell-index = <11>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <10>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@12 { + cell-index = <12>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@13 { + cell-index = <13>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@14 { + cell-index = <14>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@15 { + cell-index = <15>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@16 { + cell-index = <16>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@17 { + cell-index = <17>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@18 { + cell-index = <18>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi new file mode 100644 index 00000000..6c624c30 --- /dev/null +++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -0,0 +1,1225 @@ +&mdss_mdp { + dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC3:1 10bit dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,disable-rsc-solver; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <240>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,disable-rsc-solver; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <1>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <10>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@8 { + cell-index = <8>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@9 { + cell-index = <9>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@10 { + cell-index = <10>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@11 { + cell-index = <11>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi new file mode 100644 index 00000000..0211f659 --- /dev/null +++ b/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -0,0 +1,279 @@ +&mdss_mdp { + dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi new file mode 100644 index 00000000..b16c48d5 --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -0,0 +1,258 @@ +&mdss_mdp { + dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,mdss-dsi-bpp-switch; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-mdp-transfer-time-us-min = <14000>; + qcom,mdss-mdp-transfer-time-us-max = <16000>; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-mdp-transfer-time-us-min = <6900>; + qcom,mdss-mdp-transfer-time-us-max = <7900>; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <80>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-bpp-mode= <24>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <80>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-bpp-mode= <30>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <80>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi new file mode 100644 index 00000000..e59bfb05 --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -0,0 +1,1458 @@ +&mdss_mdp { + dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Sim dual cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <8>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@8 { + cell-index = <9>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@9 { + cell-index = <10>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@10 { + cell-index = <11>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@11 { + cell-index = <12>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <1080>; + qcom,mdss-dsc-slice-width = <1260>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@12 { + cell-index = <13>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@13 { + cell-index = <14>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@14 { + cell-index = <15>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@15 { + cell-index = <16>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@16 { + cell-index = <17>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@17 { + cell-index = <18>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi new file mode 100644 index 00000000..537a0181 --- /dev/null +++ b/display/dsi-panel-sim-dualmipi-video.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { + qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-panel-broadcast-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>; + qcom,panel-ack-disabled; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi new file mode 100644 index 00000000..dd948313 --- /dev/null +++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -0,0 +1,64 @@ +&mdss_mdp { + dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-panel-name = + "sim hd command mode secondary dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,panel-ack-disabled; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi new file mode 100644 index 00000000..78d18c82 --- /dev/null +++ b/display/dsi-panel-sim-video.dtsi @@ -0,0 +1,66 @@ +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <8>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = + [32 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-off-command = + [22 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi new file mode 100644 index 00000000..4096eb88 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -0,0 +1,360 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode 120hz dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi new file mode 100644 index 00000000..6f0e924b --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -0,0 +1,123 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode 120hz dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 00000000..4fcb45d3 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,552 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-panel-mode-switch; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <10>; + qcom,mdss-dsi-h-back-porch = <16>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <18>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + ]; + + qcom,cmd-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,vid-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 07 + ]; + qcom,cmd-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 02 6f 01 + ]; + qcom,video-mode-switch-in-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 03 + 39 01 00 00 00 00 02 6f 02 + ]; + qcom,video-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi new file mode 100644 index 00000000..df28a81f --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi @@ -0,0 +1,129 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi new file mode 100644 index 00000000..c14db0a0 --- /dev/null +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi @@ -0,0 +1,159 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled qsync cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <95>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 3c 00 3c 00 + 0c 00 0c 04 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 0c bb 00 4c 00 01 00 + 01 32 01 6e 01 6e + 39 01 00 00 00 00 02 bb 01 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 02 bb 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi new file mode 100644 index 00000000..6948326c --- /dev/null +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi @@ -0,0 +1,127 @@ +&mdss_mdp { + dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled qsync video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; From e3b7d16634654b1f0b85dfef220bd37f349710bf Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Wed, 1 Nov 2023 16:49:29 -0700 Subject: [PATCH 006/242] ARM: dts: msm: dsi: enable sun platforms Adds initial dts nodes for CDP, MTP, RCM platforms. Also adds the common, display common, and pinctrl configurations. Change-Id: I473dbca3b60bd32c7d54bef600c8398ef6d35a59 Signed-off-by: Kirill Shpin Signed-off-by: Rohith Iyer --- Kbuild | 2 + display/sun-sde-common.dtsi | 138 +++- display/sun-sde-display-cdp-overlay.dts | 1 - display/sun-sde-display-cdp.dtsi | 176 +++++ display/sun-sde-display-common.dtsi | 914 ++++++++++++++++++++++++ display/sun-sde-display-mtp-overlay.dts | 1 - display/sun-sde-display-mtp.dtsi | 89 +++ display/sun-sde-display-pinctrl.dtsi | 113 +++ display/sun-sde-display.dtsi | 149 ++++ display/sun-sde.dtsi | 43 ++ 10 files changed, 1623 insertions(+), 3 deletions(-) create mode 100644 display/sun-sde-display-common.dtsi create mode 100644 display/sun-sde-display-pinctrl.dtsi diff --git a/Kbuild b/Kbuild index 78acba35..762643b2 100644 --- a/Kbuild +++ b/Kbuild @@ -1,4 +1,6 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ + display/sun-sde-display-cdp-overlay.dtbo \ + display/sun-sde-display-mtp-overlay.dtbo \ display/sun-sde-display-rumi-overlay.dtbo always-y := $(dtb-y) $(dtbo-y) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 55adf8f3..1a6143bc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -331,5 +331,141 @@ qcom,sde-dspp-dither = <0x82c 0x00010007>; }; }; -}; + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v7.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_3nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v7.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_3nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/sun-sde-display-cdp-overlay.dts b/display/sun-sde-display-cdp-overlay.dts index ec9b2784..ab2f2519 100644 --- a/display/sun-sde-display-cdp-overlay.dts +++ b/display/sun-sde-display-cdp-overlay.dts @@ -14,4 +14,3 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>; qcom,board-id = <1 0>; }; - diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index dd810573..0e65dc00 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -5,3 +5,179 @@ #include "sun-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + avdd-supply = <&display_panel_avdd>; + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy>; + }; +}; + +&qupv3_se15_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy>; + }; +}; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi new file mode 100644 index 00000000..bec93df8 --- /dev/null +++ b/display/sun-sde-display-common.dtsi @@ -0,0 +1,914 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" + +#include "sun-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <154000>; + qcom,supply-disable-load = <45000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1000000>; + qcom,supply-max-voltage = <1100000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <471>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <1000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 86 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 87 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_sim_panel_au { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a + 0b 0a 02 04 00 21 10]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b + 1d 18 02 04 00 51 21]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25 + 27 1f 02 04 00 69 2a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12 + 14 11 02 04 00 39 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 17 14 0e + 0e 0d 02 04 00 2b 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index 4a5ba68e..9038f744 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -14,4 +14,3 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>; qcom,board-id = <8 0>; }; - diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index dd810573..3154f2e3 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -5,3 +5,92 @@ #include "sun-sde-display.dtsi" +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy>; + }; +}; + +&battery_charger { + qcom,display-panels = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy>; +}; diff --git a/display/sun-sde-display-pinctrl.dtsi b/display/sun-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..16f21a89 --- /dev/null +++ b/display/sun-sde-display-pinctrl.dtsi @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio86"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio86"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio87"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio87"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index da7270d2..1fa00786 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -4,6 +4,7 @@ */ #include "sun-sde.dtsi" +#include "sun-sde-display-common.dtsi" #include &soc { @@ -18,9 +19,157 @@ cell-index = <1>; label = "wb_display2"; }; + + + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + vddio-supply = <&L12B>; + vci-supply = <&L13B>; + vdd-supply = <&L11B>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + vddio-supply = <&L12B>; + vci-supply = <&L13B>; + vdd-supply = <&L11B>; }; &mdss_mdp { connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>; }; +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 20 360 20 360 20>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 166f64f7..c1f29bac 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -86,3 +86,46 @@ }; }; +&mdss_dsi0 { + vdda-1p2-supply = <&L3G>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L3G>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L3I>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; + +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L3I>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; +}; From d3d5136f5f8449e128666014f57e04ef5084e137 Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Thu, 9 Nov 2023 12:15:55 -0800 Subject: [PATCH 007/242] ARM: dts: msm: add DSI nodes to connectors list for sun This change adds DSI nodes to the connectors list for sun target. Change-Id: Idabce49d9abec0e5a310dbe59fbfb4a18ac2b226 Signed-off-by: Rohith Iyer --- display/sun-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 1fa00786..e53a918a 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,7 +92,7 @@ }; &mdss_mdp { - connectors = <&smmu_sde_unsec &sde_wb1 &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2>; }; &dsi_vtdr6130_amoled_cmd { From 46f32bb8da40faa0dec33c3a86994e9dce85eaa6 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Fri, 24 Nov 2023 20:33:32 +0800 Subject: [PATCH 008/242] ARM: dts: msm: enable dp hdcp/pll/audio codec for sun Enable dp hdcp/pll/audio codec for sun. Change-Id: Ibdc94b27e4b8d1cb558656c9374d18b7b6266460 Signed-off-by: Yahui Wang --- display/sun-sde.dtsi | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 29d03668..a79a31a8 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -14,16 +14,30 @@ &soc { ext_disp: qcom,msm-ext-disp { compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88eb000 { + compatible = "qcom,dp-pll-3nm-v1"; + #clock-cells = <1>; }; sde_dp: qcom,dp_display@af54000 { - status = "disabled"; cell-index = <0>; compatible = "qcom,dp-display"; usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -52,10 +66,10 @@ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&sde_dp 0>, + <&sde_dp_pll 0>, <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, - <&sde_dp 1>, + <&sde_dp_pll 1>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; @@ -64,7 +78,7 @@ "link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; - qcom,pll-revision = "3nm-v1"; + qcom,dp-pll = <&sde_dp_pll>; qcom,phy-version = <0x800>; qcom,aux-cfg0-settings = [20 00]; qcom,aux-cfg1-settings = [24 13]; From 7a945a913dd6029f11924283321284f14671bfaa Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 27 Nov 2023 13:52:02 -0800 Subject: [PATCH 009/242] ARM: dts: msm: dsi: add power supply for CSOT CPHY Adds missing power supply node to pull up a pin necessary for CSOT panel's CPHY mode. Change-Id: I260ae895a015cdc6a02a89d986aa8d3d62c7c1d0 Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 10 ++++++++++ display/sun-sde-display.dtsi | 2 ++ 2 files changed, 12 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index bec93df8..383db4c8 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -75,6 +75,16 @@ qcom,supply-disable-load = <300>; qcom,supply-post-on-sleep = <0>; }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "tvdd"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <2000>; + }; }; dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 1fa00786..296f037f 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -61,6 +61,7 @@ vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; + tvdd-supply = <&L4B>; }; &sde_dsi1 { @@ -89,6 +90,7 @@ vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; + tvdd-supply = <&L4B>; }; &mdss_mdp { From 8a5b409dd0d3342e252ab8659f8bc4777c6d776a Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Tue, 21 Nov 2023 13:11:20 -0800 Subject: [PATCH 010/242] ARM: dts: msm: increase LPM load current for L13B rail Increase active load current for L13B rail vote to 10 mA. Vote of >= 10 mA is required for active use case to prevent OCP on regulator. Change-Id: I8e1652b031479cfa0f4e51bcd2c2bc4347400b4a Signed-off-by: Rohith Iyer --- display/sun-sde-display-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index bec93df8..10a0a890 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -71,7 +71,7 @@ qcom,supply-name = "vci"; qcom,supply-min-voltage = <3000000>; qcom,supply-max-voltage = <3000000>; - qcom,supply-enable-load = <1000>; + qcom,supply-enable-load = <10000>; qcom,supply-disable-load = <300>; qcom,supply-post-on-sleep = <0>; }; From 8dcf527549c174f6cc3d5fb220444bfc895995fe Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Mon, 27 Nov 2023 16:33:05 -0800 Subject: [PATCH 011/242] ARM: dts: msm: dsi: support LCD panels Add pm8550_gpios node and gpio information to support LCD panels. Change-Id: Ie755d57d7acd16d4bfc8ac6c0cf3f2d0b5ff15e6 Signed-off-by: Rohith Iyer --- display/sun-sde-display.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 1fa00786..b3592f13 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -7,6 +7,18 @@ #include "sun-sde-display-common.dtsi" #include +&pm8550_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio11"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + &soc { sde_wb1: qcom,wb-display@1 { compatible = "qcom,wb-display"; @@ -27,6 +39,7 @@ regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; regulator-enable-ramp-delay = <233>; + gpio = <&pm8550_gpios 11 0>; enable-active-high; regulator-boot-on; proxy-supply = <&display_panel_avdd>; From bcb4f713e5cfb97cc15da9ea2bb7b229a6b2a930 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 22 Nov 2023 14:27:31 -0800 Subject: [PATCH 012/242] ARM: dts: msm: enable idle-pc on sun target Enable idle power collapse feature on sun target. Change-Id: Ifa2481321322414f16aaa872431f2e1c270dff33 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 166f64f7..d623a027 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -57,6 +57,8 @@ interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-has-idle-pc; + qcom,sde-ib-bw-vote = <2500000 0 800000>; qcom,sde-dspp-ltm-version = <0x00010002>; /* offsets are based off dspp 0, 1, 2, and 3 */ From 2eed873fd76ae5a03f3c65d04dd8b660c354dc7b Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 28 Nov 2023 09:53:57 -0800 Subject: [PATCH 013/242] ARM: dts: msm: add SMMU_PROXY_DISPLAY_CB to MDP device in sun target SMMU_PROXY_DISPLAY_CB is used as a hint for memory driver, for special handling of secure-camera preview buffer. Add it to the MDP device as the secure-camera preview buffers will be attached with the MDP device as the dummy device. Change-Id: I439687335b29f82d9288953bd72872860af5a8a2 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 166f64f7..d5652e0b 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include "sun-sde-common.dtsi" &soc { @@ -47,6 +48,8 @@ vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; + qti,smmu-proxy-cb-id = ; + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; /* data and reg bus scale settings */ From 7dd76e1b107fab65a9ecec059d81412d07ebfe0f Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Fri, 24 Nov 2023 20:37:38 +0800 Subject: [PATCH 014/242] ARM: dts: msm: add sde_dp node to connectors list for sun Add sde_dp node to connectors list for sun. Change-Id: Iccc9911b6ac1f9da8807009fb3a3d520eea68aea Signed-off-by: Yahui Wang --- display/sun-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 67eb583c..819dd5ee 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -107,7 +107,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2 &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { From ae736009b3aedc6146fdeaa1d0d6f5a1c0c5049a Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Thu, 30 Nov 2023 15:25:35 -0800 Subject: [PATCH 015/242] ARM: dts: msm: dsi: add panel commands to reduce load on VCI power rail Add panel commands to nt37801 panel's configurations which program BTPUMPCTRL to reduce the load on VCI power rail to 1 mA. Change-Id: Iad4d74db8195175f82f06574145db40306897bd8 Signed-off-by: Rohith Iyer --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 ++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 2 ++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 2 ++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 2 ++ 4 files changed, 8 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index eacca56f..25357b7c 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -87,6 +87,8 @@ 39 01 00 00 00 00 05 FF AA 55 A5 82 39 01 00 00 00 00 02 6F 08 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 ]; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 92004657..a9bda899 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -83,6 +83,8 @@ 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 ]; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 65b22528..83152a0e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -87,6 +87,8 @@ 39 01 00 00 00 00 05 FF AA 55 A5 82 39 01 00 00 00 00 02 6F 08 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 ]; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 0bab8128..652cd619 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -84,6 +84,8 @@ 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 05 01 00 00 78 00 01 11 05 01 00 00 14 00 01 29 ]; From 3cf30c9b549d2a28a0342284863a7747d8f8a20f Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Wed, 29 Nov 2023 15:02:44 -0800 Subject: [PATCH 016/242] ARM: dts: msm: dsi: disable secondary touch node Disable secondary touch node as there are currently i2c errors from that address causing st_fts touch driver to enter error case and fail probe. Change-Id: I7b9427c0aedd17f8cfda9fdd4966d125369edf61 Signed-off-by: Rohith Iyer --- display/sun-sde-display-cdp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 0e65dc00..3d9db11a 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -174,6 +174,7 @@ }; &qupv3_se15_i2c { + status = "disabled"; st_fts@49 { panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy From f790be71615dc83cb4b9183daca3f6bae5b7b125 Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Tue, 5 Dec 2023 14:52:23 -0800 Subject: [PATCH 017/242] ARM: dts: msm: dsi: fix indices on mdss_dsi_phy* providers Since mdss_dsi_phy* providers only support two clocks, fix current implementation which indexes out of bounds and causes a failure in dsi when trying to get clocks. Change-Id: I671b1f4032c124a515c4d5cebbbd098fdfaca95e Signed-off-by: Rohith Iyer --- display/sun-sde-display.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 819dd5ee..d48d6045 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -51,8 +51,8 @@ &sde_dsi { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe @@ -80,8 +80,8 @@ &sde_dsi1 { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe From 9779d94585c8657248cd99732105dc4813733e1e Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 10 Nov 2023 13:25:10 +0800 Subject: [PATCH 018/242] ARM: dts: msm: add display device tree support for QRD SUN variants Add display device tree support for QRD SUN variants. Change-Id: I0f6f9914904d0ddf26bff2149ce490b69a1259b8 Signed-off-by: Lei Chen --- Kbuild | 5 +- display/sun-sde-display-common.dtsi | 26 ++++++++++ display/sun-sde-display-qrd-sku1-overlay.dts | 17 +++++++ .../sun-sde-display-qrd-sku1-v8-overlay.dts | 17 +++++++ .../sun-sde-display-qrd-sku2-v8-overlay.dts | 17 +++++++ display/sun-sde-display-qrd.dtsi | 50 +++++++++++++++++++ 6 files changed, 131 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-qrd-sku1-overlay.dts create mode 100644 display/sun-sde-display-qrd-sku1-v8-overlay.dts create mode 100644 display/sun-sde-display-qrd-sku2-v8-overlay.dts create mode 100644 display/sun-sde-display-qrd.dtsi diff --git a/Kbuild b/Kbuild index 762643b2..d078accc 100644 --- a/Kbuild +++ b/Kbuild @@ -1,7 +1,10 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-overlay.dtbo \ display/sun-sde-display-mtp-overlay.dtbo \ - display/sun-sde-display-rumi-overlay.dtbo + display/sun-sde-display-rumi-overlay.dtbo \ + display/sun-sde-display-qrd-sku1-overlay.dtbo \ + display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \ + display/sun-sde-display-qrd-sku2-v8-overlay.dtbo always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index aebc8612..0f22bc80 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -358,6 +358,32 @@ }; }; +&dsi_nt37801_amoled_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-qrd-sku1-overlay.dts b/display/sun-sde-display-qrd-sku1-overlay.dts new file mode 100644 index 00000000..2479ab77 --- /dev/null +++ b/display/sun-sde-display-qrd-sku1-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/display/sun-sde-display-qrd-sku1-v8-overlay.dts b/display/sun-sde-display-qrd-sku1-v8-overlay.dts new file mode 100644 index 00000000..4780320d --- /dev/null +++ b/display/sun-sde-display-qrd-sku1-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x3000B 0>; +}; diff --git a/display/sun-sde-display-qrd-sku2-v8-overlay.dts b/display/sun-sde-display-qrd-sku2-v8-overlay.dts new file mode 100644 index 00000000..0820a163 --- /dev/null +++ b/display/sun-sde-display-qrd-sku2-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x2000B 0>; +}; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi new file mode 100644 index 00000000..3d730f68 --- /dev/null +++ b/display/sun-sde-display-qrd.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; From c6a758b4241fb44f8a664b4f4a3f169a5dd38261 Mon Sep 17 00:00:00 2001 From: Alisha Thapaliya Date: Mon, 20 Nov 2023 00:03:47 -0800 Subject: [PATCH 019/242] ARM: dts: msm: introduce mDNIe support The Sun platform introduces support for mDNIe hardware. Update the device tree definition to provide mDNIe hardware details and register access to the MSM DRM driver. Change-Id: I783d7baeca2886c08329feeeef4f8a1c445ddbb7 Signed-off-by: Alisha Thapaliya --- bindings/sde.txt | 42 +++++++++++++++++++++++++++++++++++++ display/sun-sde-common.dtsi | 17 +++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index c088ece5..2abbe5a5 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -387,6 +387,31 @@ Optional properties: corresponding DSPP block offset as base. - qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range - qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware. +- qcom,sde-dspp-aiqe-off: Array of u32 values indicating the offset of each AIQE block + relative to its parent DSPP block. +- qcom,sde-dspp-aiqe-version: A u32 value indicating the version of the AIQE hardware. +- qcom,sde-dspp-aiqe-size: A u32 value indicating the shared memory size of each AIQE + hardware block instance. +- qcom,sde-dspp-aiqe-dither-off: Array of u32 values indicating the offset of each AIQE + dither block relative to its parent DSPP block. +- qcom,sde-dspp-aiqe-dither-version: A u32 value indicating the version of the AIQE dither + hardware. +- qcom,sde-dspp-aiqe-dither-size: A u32 value indicating the shared memory size of each AIQE + dither hardware block instance. +- qcom,sde-dspp-aiqe-wrapper-off: Array of u32 values indicating the offset of each AIQE + wrapper block relative to its parent DSPP block. +- qcom,sde-dspp-aiqe-wrapper-version: A u32 value indicating the version of the AIQE wrapper + hardware. +- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE + wrapper hardware block instance. +- qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe + hardware. +- qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC + hardware. +- qcom,sde-aiqe-has-feature-ssrc: Boolean property indicating the presence of AIQE feature SSRC + hardware. +- qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR + hardware. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -710,6 +735,23 @@ Example: qcom,sde-lm-noise-off = <0x320>; qcom,sde-lm-noise-version = <0x00010000>; + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + qcom,sde-dspp-rc-mem-size = <2720>; qcom,sde-dest-scaler-top-off = <0x00061000>; qcom,sde-dest-scaler-off = <0x800 0x1000>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 1a6143bc..c517fc02 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -193,6 +193,23 @@ qcom,sde-dspp-demura-size = <0xe4>; qcom,sde-dspp-demura-version = <0x00020000>; + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + qcom,sde-lm-noise-off = <0x320>; qcom,sde-lm-noise-version = <0x00010000>; From a959cdec45b98fbf8aef9a2eb5307cf97be7965f Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Wed, 6 Dec 2023 17:39:45 -0800 Subject: [PATCH 020/242] ARM: dts: msm: add RCM device tree files Adds new files for RCM CDT, which falls back on the CDP files for configuration. Change-Id: I323099abc2cab872e665d3d21bdee94d4ae9f5cf Signed-off-by: Kirill Shpin --- Kbuild | 1 + display/sun-sde-display-rcm-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm.dtsi | 6 ++++++ 3 files changed, 23 insertions(+) create mode 100644 display/sun-sde-display-rcm-overlay.dts create mode 100644 display/sun-sde-display-rcm.dtsi diff --git a/Kbuild b/Kbuild index d078accc..649aa4ce 100644 --- a/Kbuild +++ b/Kbuild @@ -2,6 +2,7 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-overlay.dtbo \ display/sun-sde-display-mtp-overlay.dtbo \ display/sun-sde-display-rumi-overlay.dtbo \ + display/sun-sde-display-rcm-overlay.dtbo \ display/sun-sde-display-qrd-sku1-overlay.dtbo \ display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \ display/sun-sde-display-qrd-sku2-v8-overlay.dtbo diff --git a/display/sun-sde-display-rcm-overlay.dts b/display/sun-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..4236e89b --- /dev/null +++ b/display/sun-sde-display-rcm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x15 0>; +}; diff --git a/display/sun-sde-display-rcm.dtsi b/display/sun-sde-display-rcm.dtsi new file mode 100644 index 00000000..4566cd46 --- /dev/null +++ b/display/sun-sde-display-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display-cdp.dtsi" From 9ab8a2cac05cb28b153186f374e36bd58aeb711c Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 29 Nov 2023 11:34:17 -0800 Subject: [PATCH 021/242] ARM: dts: msm: add all supported platform variants for sun target Add Kiwi, NFC, v8 Power Grid, v8 Power Grid with Kiwi on MTP & CDP platforms for Sun target. Change-Id: I3cd60571147aa566aa11aad4f49829b19d928983 Signed-off-by: Veera Sundaram Sankaran --- Kbuild | 10 +++++++++- display/sun-sde-display-cdp-kiwi-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-cdp-kiwi-v8-overlay.dts | 17 +++++++++++++++++ display/sun-sde-display-cdp-nfc-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-cdp-v8-overlay.dts | 17 +++++++++++++++++ display/sun-sde-display-mtp-kiwi-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-mtp-kiwi-v8-overlay.dts | 17 +++++++++++++++++ display/sun-sde-display-mtp-nfc-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-mtp-v8-overlay.dts | 17 +++++++++++++++++ 9 files changed, 141 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-cdp-kiwi-overlay.dts create mode 100644 display/sun-sde-display-cdp-kiwi-v8-overlay.dts create mode 100644 display/sun-sde-display-cdp-nfc-overlay.dts create mode 100644 display/sun-sde-display-cdp-v8-overlay.dts create mode 100644 display/sun-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/sun-sde-display-mtp-kiwi-v8-overlay.dts create mode 100644 display/sun-sde-display-mtp-nfc-overlay.dts create mode 100644 display/sun-sde-display-mtp-v8-overlay.dts diff --git a/Kbuild b/Kbuild index d078accc..46f59d76 100644 --- a/Kbuild +++ b/Kbuild @@ -4,7 +4,15 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-rumi-overlay.dtbo \ display/sun-sde-display-qrd-sku1-overlay.dtbo \ display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \ - display/sun-sde-display-qrd-sku2-v8-overlay.dtbo + display/sun-sde-display-qrd-sku2-v8-overlay.dtbo \ + display/sun-sde-display-cdp-kiwi-overlay.dtbo \ + display/sun-sde-display-mtp-kiwi-overlay.dtbo \ + display/sun-sde-display-cdp-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-mtp-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-cdp-nfc-overlay.dtbo \ + display/sun-sde-display-mtp-nfc-overlay.dtbo \ + display/sun-sde-display-cdp-v8-overlay.dtbo \ + display/sun-sde-display-mtp-v8-overlay.dtbo always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts new file mode 100644 index 00000000..acfc23ea --- /dev/null +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x20001 0>; +}; diff --git a/display/sun-sde-display-cdp-kiwi-v8-overlay.dts b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..fba63430 --- /dev/null +++ b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60001 0>; +}; diff --git a/display/sun-sde-display-cdp-nfc-overlay.dts b/display/sun-sde-display-cdp-nfc-overlay.dts new file mode 100644 index 00000000..f9aba3ab --- /dev/null +++ b/display/sun-sde-display-cdp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40001 0>; +}; diff --git a/display/sun-sde-display-cdp-v8-overlay.dts b/display/sun-sde-display-cdp-v8-overlay.dts new file mode 100644 index 00000000..dee0d9e7 --- /dev/null +++ b/display/sun-sde-display-cdp-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x50001 0>; +}; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..6d755f25 --- /dev/null +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x20008 0>; +}; diff --git a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..c354a996 --- /dev/null +++ b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x50008 0>; +}; diff --git a/display/sun-sde-display-mtp-nfc-overlay.dts b/display/sun-sde-display-mtp-nfc-overlay.dts new file mode 100644 index 00000000..544c30fe --- /dev/null +++ b/display/sun-sde-display-mtp-nfc-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x30008 0>; +}; diff --git a/display/sun-sde-display-mtp-v8-overlay.dts b/display/sun-sde-display-mtp-v8-overlay.dts new file mode 100644 index 00000000..3cfae533 --- /dev/null +++ b/display/sun-sde-display-mtp-v8-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40008 0>; +}; From 5087f5eb21adc2235e4e2067eea155cf4f96b1aa Mon Sep 17 00:00:00 2001 From: Rohith Iyer Date: Wed, 29 Nov 2023 17:06:17 -0800 Subject: [PATCH 022/242] ARM: dts: msm: dsi: support secondary display for nt37801 panel Add properties to support secondary display on CDP for both command and video mode for nt37801 panel. Change-Id: I040bece2ae656606f76e13c59e67b08cd730dea2 Signed-off-by: Rohith Iyer Signed-off-by: Kirill Shpin --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 2 ++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 2 ++ display/sun-sde-display-cdp.dtsi | 6 ++++++ display/sun-sde-display-common.dtsi | 2 ++ 4 files changed, 12 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index a9bda899..61437024 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -13,6 +13,8 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-lane-map = "lane_map_0123"; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 652cd619..70ba9540 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -10,6 +10,8 @@ qcom,mdss-dsi-border-color = <0>; qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; qcom,mdss-dsi-traffic-mode = "burst_mode"; qcom,mdss-dsi-bllp-eof-power-mode; qcom,mdss-dsi-bllp-power-mode; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 3d9db11a..7c979c54 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -43,22 +43,28 @@ &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_vtdr6130_amoled_120hz_video { diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 0f22bc80..765cc2d4 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -347,6 +347,7 @@ &dsi_nt37801_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-display-timings { timing@0 { @@ -386,6 +387,7 @@ &dsi_nt37801_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; qcom,mdss-dsi-display-timings { timing@0 { From f87233beaca71f0f68a621ba76e08e2425914433 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Tue, 12 Dec 2023 14:45:01 +0800 Subject: [PATCH 023/242] ARM: dts: msm: enable touch panel on sun QRD platform Adds touch panel dts nodes for QRD platform. Change-Id: Ia60a126574e6841bdd2c4de1dacf63d42fe93ded Signed-off-by: Rui Chen --- display/sun-sde-display-qrd.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 3d730f68..65f8e0d2 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -48,3 +48,12 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video>; + }; +}; From 423d3e762a39536ee61c521d9127561c3215fe1a Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Sun, 17 Dec 2023 23:27:20 -0800 Subject: [PATCH 024/242] ARM: dts: msm: add APQ SOC id for SDE on sun target Add APQ SOC id in mtp/cdp variants on sun target. Change-Id: I42cf0b07a08f09a983399cd5cffe2001481061e7 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display-cdp-overlay.dts | 2 +- display/sun-sde-display-mtp-overlay.dts | 2 +- display/sun-sde.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display-cdp-overlay.dts b/display/sun-sde-display-cdp-overlay.dts index ab2f2519..a3b29d3c 100644 --- a/display/sun-sde-display-cdp-overlay.dts +++ b/display/sun-sde-display-cdp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <1 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index 9038f744..48ad6325 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde.dts b/display/sun-sde.dts index d55ab390..4b3a3f74 100644 --- a/display/sun-sde.dts +++ b/display/sun-sde.dts @@ -9,6 +9,6 @@ #include "sun-sde.dtsi" / { - qcom,msm-id = <618 0x10000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <15 0>; }; From 2f8d5c682facdb02c19fccbebd6b480c6b384b6b Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 26 Dec 2023 10:27:03 -0800 Subject: [PATCH 025/242] ARM: dts: msm: add missing license markings Adds missing license markers to files that don't have them. Change-Id: I855935751e4e60976428ad201c5facc2da28db2e Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 1 + display/sun-sde-display-pinctrl.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 765cc2d4..143f1aec 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ diff --git a/display/sun-sde-display-pinctrl.dtsi b/display/sun-sde-display-pinctrl.dtsi index 16f21a89..7a7846df 100644 --- a/display/sun-sde-display-pinctrl.dtsi +++ b/display/sun-sde-display-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ From 421daddce2fd95deac8eb45e27fc310643cdb9a7 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 12 Dec 2023 16:12:12 -0800 Subject: [PATCH 026/242] ARM: dts: msm: add FHD+ mode for CSOT panel Adds a mode with FHD+ resolution to the CSOT panel. Change-Id: I73ba24676e0a74f6f1c95254850d5c2add498336 Signed-off-by: Kirill Shpin --- .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 85 +++++++++++++++++++ display/sun-sde-display-common.dtsi | 7 ++ 2 files changed, 92 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index a9bda899..cc9feff4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -51,6 +51,12 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 02 8F 00 + ]; + qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 06 F0 55 AA 52 08 01 39 01 00 00 00 00 02 6F 01 @@ -105,6 +111,85 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 02 8F 01 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0 + 39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0 + 39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0 + 39 01 00 00 00 00 02 03 00 + 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 0f22bc80..a78c7146 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -355,6 +355,13 @@ qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; }; }; From 9f36f8826743fd826beeb1078261ec6e13afb793 Mon Sep 17 00:00:00 2001 From: Renchao Liu Date: Wed, 15 Nov 2023 14:09:46 +0800 Subject: [PATCH 027/242] ARM: dts: msm: update DSPP GC/PCC version DSPP functionality has been updated to support high precision mode. Update the DSPP block versions accordingly. Change-Id: Iad137c4fc54127c05cc92b8ed4948e2b78e43437 Signed-off-by: Renchao Liu --- display/sun-sde-common.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c517fc02..c17ac6b3 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -343,8 +343,8 @@ qcom,sde-dspp-sixzone = <0x900 0x00020000>; qcom,sde-dspp-vlut = <0xa00 0x00010008>; qcom,sde-dspp-gamut = <0x1000 0x00040003>; - qcom,sde-dspp-pcc = <0x1700 0x00040000>; - qcom,sde-dspp-gc = <0x17c0 0x00010008>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; qcom,sde-dspp-dither = <0x82c 0x00010007>; }; }; From c730c8a7cb78b5486cd640c7fbc78b52a98d6d9d Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Tue, 19 Dec 2023 17:35:16 -0500 Subject: [PATCH 028/242] ARM: dts: msm: replace smmu address property for sun target Replacing existing smmu address property to upstream compatible property. Change-Id: I0a2eb94d7e91d1d59467bfc68ca4b87a52bd2160 Signed-off-by: Jayasri Sampath Kumaran --- display/sun-sde.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index ae31c68c..6c7e3b31 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -181,10 +181,16 @@ }; }; + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd5500000 0x02b00000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { compatible = "qcom,smmu_sde_unsec"; iommus = <&apps_smmu 0x800 0x2>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + memory-region = <&smmu_sde_iommu_region_partition>; qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ dma-coherent; @@ -193,7 +199,7 @@ smmu_sde_sec: qcom,smmu_sde_sec_cb { compatible = "qcom,smmu_sde_sec"; iommus = <&apps_smmu 0x801 0x0>; - qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + memory-region = <&smmu_sde_iommu_region_partition>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; From 8e576b545651159d3cdb88c5c79c117a9cff6cdb Mon Sep 17 00:00:00 2001 From: Qing Huang Date: Mon, 13 Nov 2023 15:20:06 +0800 Subject: [PATCH 029/242] ARM: dts: msm: Update IGC versions for high-precision mode IGC functionality has been updated to support high-precision mode. Update the IGC versions accordingly. Change-Id: I1f57014763c05c26318de703447a6a2c7649a4f7 Signed-off-by: Qing Huang --- display/sun-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c17ac6b3..1be8c707 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -336,7 +336,7 @@ }; qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x1260 0x00040000>; + qcom,sde-dspp-igc = <0x1260 0x00050000>; qcom,sde-dspp-hsic = <0x800 0x00010007>; qcom,sde-dspp-memcolor = <0x880 0x00010007>; qcom,sde-dspp-hist = <0x800 0x00010007>; From 4fc4835cef7e6b8432350fba983b6111513be96f Mon Sep 17 00:00:00 2001 From: Qing Huang Date: Wed, 15 Nov 2023 14:58:31 +0800 Subject: [PATCH 030/242] ARM: dts: msm: Update LTM version to 1.3 LTM ROI region handling has been updated. Update the LTM DTSI version to 1.3 to track this change. Change-Id: I57a0a07f4f249f837c2f057114f5f15e827e0731 Signed-off-by: Qing Huang --- display/sun-sde.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index ae31c68c..19f90baa 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -231,7 +231,7 @@ qcom,sde-has-idle-pc; qcom,sde-ib-bw-vote = <2500000 0 800000>; - qcom,sde-dspp-ltm-version = <0x00010002>; + qcom,sde-dspp-ltm-version = <0x00010003>; /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; From bcee516166f0aca8a42a1f7bc9265654cc6b4828 Mon Sep 17 00:00:00 2001 From: Renchao Liu Date: Wed, 8 Nov 2023 17:01:46 +0800 Subject: [PATCH 031/242] ARM: dts: msm: update ucsc version This change updates ucsc version to support INT2FP/FP2INT enable. Change-Id: I548cef05759cf3ee557d7424b96c5f2ba2ba82d3 Signed-off-by: Renchao Liu --- display/sun-sde-common.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 1be8c707..c03d81ba 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -285,10 +285,10 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; }; @@ -298,10 +298,10 @@ qcom,sde-fp16-unmult = <0x280 0x00010000>; qcom,sde-fp16-gc = <0x280 0x00010000>; qcom,sde-fp16-csc = <0x280 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; }; }; @@ -314,10 +314,10 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; }; @@ -327,10 +327,10 @@ qcom,sde-fp16-unmult = <0x200 0x00010000>; qcom,sde-fp16-gc = <0x200 0x00010000>; qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; }; }; From e7717ae78ddfd67765c980159a96d347981cd392 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 26 Dec 2023 10:27:03 -0800 Subject: [PATCH 032/242] ARM: dts: msm: add missing license markings. Adds missing license markers to files that don't have them. Change-Id: I855935751e4e60976428ad201c5facc2da28db2e Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 1 + display/sun-sde-display-pinctrl.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index aebc8612..d0b187ab 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ diff --git a/display/sun-sde-display-pinctrl.dtsi b/display/sun-sde-display-pinctrl.dtsi index 16f21a89..7a7846df 100644 --- a/display/sun-sde-display-pinctrl.dtsi +++ b/display/sun-sde-display-pinctrl.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ From ee1cbb9e3cf72a74376fa2a8e94826566c6fd2f1 Mon Sep 17 00:00:00 2001 From: Yuchao Ma Date: Fri, 22 Dec 2023 13:44:14 +0800 Subject: [PATCH 033/242] ARM: dts: msm: Add pack type for SPR on sun target This change adds pack type for SPR on sun target. Change-Id: I2d403a15e2e8a66586dd4acddf1f635c644a9dae Signed-off-by: Yuchao Ma --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 1 + display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 1 + display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 1 + display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 1 + 4 files changed, 4 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 25357b7c..5612ec26 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -32,6 +32,7 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e219d5ed..e417cdb2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -34,6 +34,7 @@ qcom,mdss-dsi-te-dcs-command = <1>; qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 83152a0e..53de247a 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -22,6 +22,7 @@ qcom,mdss-dsi-tx-eot-append; qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 70ba9540..d4647340 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -27,6 +27,7 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 2f01796505872ef491eda0fea8e0dff5d528e274 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Thu, 14 Dec 2023 17:05:29 +0530 Subject: [PATCH 034/242] ARM: dts: msm: introduce AI Scaler support The Sun platform introduces support for AI Scaler hardware. Update the device tree definition to provide AI Scaler hardware details and register access to the MSM DRM driver. Change-Id: I38944376bc4579759391ff1e70882bf812dc133e Signed-off-by: Sanskar Omar --- bindings/sde.txt | 8 ++++++++ display/sun-sde-common.dtsi | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 2abbe5a5..779a3da7 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -404,6 +404,12 @@ Optional properties: hardware. - qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE wrapper hardware block instance. +- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE + AI Scaler block relative to its parent DSPP block. +- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler + hardware. +- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE + AI Scaler hardware block instance. - qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe hardware. - qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC @@ -412,6 +418,8 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR hardware. +- qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature + AI Scaler hardware. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c517fc02..eb41ed1e 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -205,10 +205,15 @@ qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + qcom,sde-dspp-aiqe-aiscaler-off = <0x30000 0xffffffff>; + qcom,sde-dspp-aiqe-aiscaler-version = <0x00010000>; + qcom,sde-dspp-aiqe-aiscaler-size = <0x7d0>; + qcom,sde-aiqe-has-feature-mdnie; qcom,sde-aiqe-has-feature-abc; qcom,sde-aiqe-has-feature-ssrc; qcom,sde-aiqe-has-feature-copr; + qcom,sde-aiqe-has-feature-aiscaler; qcom,sde-lm-noise-off = <0x320>; qcom,sde-lm-noise-version = <0x00010000>; From deeda4cc1fc1014a0fe0fffc9d83e5016d201ccc Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Tue, 9 Jan 2024 11:20:14 -0500 Subject: [PATCH 035/242] ARM: dts: msm: update BW limits for sun target Update BW limit values based on QOS recommendation for sun target. Change-Id: Id3ba8542cb89bd4b8d682e7d48841c6a29e2c6d6 Signed-off-by: Jayasri Sampath Kumaran --- display/sun-sde-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c17ac6b3..5d60bfd6 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -177,8 +177,8 @@ qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; - qcom,sde-max-bw-low-kbps = <17000000>; - qcom,sde-max-bw-high-kbps = <27000000>; + qcom,sde-max-bw-low-kbps = <18900000>; + qcom,sde-max-bw-high-kbps = <28500000>; qcom,sde-min-core-ib-kbps = <2500000>; qcom,sde-min-llcc-ib-kbps = <0>; qcom,sde-min-dram-ib-kbps = <800000>; From 2cc2220b57d32e73c3b02821a22e1a89412923a8 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Tue, 12 Dec 2023 13:19:49 -0800 Subject: [PATCH 036/242] ARM: dts: msm: add cont-splash & ramdump support on sun target Add continuous splash memory region & ramdump memory region on sun target to enable the features. Change-Id: Ia7bed7b30935a912c977a543430a2b9ad0921439 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index d48d6045..c798a37f 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -46,6 +46,18 @@ qcom,proxy-consumer-enable; pinctrl-names = "default"; }; + + disp_rdump_memory: disp_rdump_region@0xd5500000 { + reg = <0xd5500000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xd5500000 0x0 0x02b00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { From 0cae8dfc8019b5285dee198c24a06a625d4ee463 Mon Sep 17 00:00:00 2001 From: Anjelique Melendez Date: Thu, 4 Jan 2024 11:56:28 -0800 Subject: [PATCH 037/242] ARM: dts: msm: add display panels under battery_charger device for Sun QRD Add display panels under battery_charger device for Sun so battery_charger device will receive notifications when display is turned on/off. Change-Id: Ic128b3285b1ee76469863323f1a69a42ed1c55bd Signed-off-by: Anjelique Melendez --- display/sun-sde-display-qrd.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 65f8e0d2..9ffcea89 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde-display.dtsi" @@ -57,3 +57,10 @@ &dsi_nt37801_amoled_video>; }; }; + +&battery_charger { + qcom,display-panels = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy>; +}; From 7d485131a1be81a2b1a6d21536d8c9de5a55bfcf Mon Sep 17 00:00:00 2001 From: Ramkumar Radhakrishnan Date: Wed, 22 Nov 2023 02:14:39 -0800 Subject: [PATCH 038/242] ARM: dts: msm: Add trustedvm device tree files for Sun target Add the trusted VM devicetree nodes for Sun target. Change-Id: I393576e742d0c793d26558e64a3f39102c1de032 Signed-off-by: Ramkumar Radhakrishnan Signed-off-by: Mahadevan --- Kbuild | 5 + .../trustedvm-sun-sde-display-cdp-overlay.dts | 17 +++ display/trustedvm-sun-sde-display-cdp.dtsi | 143 ++++++++++++++++++ .../trustedvm-sun-sde-display-mtp-overlay.dts | 17 +++ display/trustedvm-sun-sde-display-mtp.dtsi | 69 +++++++++ display/trustedvm-sun-sde-display.dtsi | 28 ++++ display/trustedvm-sun-sde.dtsi | 82 ++++++++++ 7 files changed, 361 insertions(+) create mode 100644 display/trustedvm-sun-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-sun-sde-display-cdp.dtsi create mode 100644 display/trustedvm-sun-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-sun-sde-display-mtp.dtsi create mode 100644 display/trustedvm-sun-sde-display.dtsi create mode 100644 display/trustedvm-sun-sde.dtsi diff --git a/Kbuild b/Kbuild index e80ba254..a824c4d7 100644 --- a/Kbuild +++ b/Kbuild @@ -1,3 +1,4 @@ +ifneq ($(CONFIG_ARCH_QTI_VM), y) dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-overlay.dtbo \ display/sun-sde-display-mtp-overlay.dtbo \ @@ -14,6 +15,10 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ + display/trustedvm-sun-sde-display-mtp-overlay.dtbo +endif always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) diff --git a/display/trustedvm-sun-sde-display-cdp-overlay.dts b/display/trustedvm-sun-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..8daf5e96 --- /dev/null +++ b/display/trustedvm-sun-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x10001 0>; +}; diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi new file mode 100644 index 00000000..26a92cf5 --- /dev/null +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..fd2fea89 --- /dev/null +++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x10008 0>; +}; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi new file mode 100644 index 00000000..8094ced6 --- /dev/null +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-sun-sde-display.dtsi b/display/trustedvm-sun-sde-display.dtsi new file mode 100644 index 00000000..995d7758 --- /dev/null +++ b/display/trustedvm-sun-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; +}; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi new file mode 100644 index 00000000..22855dd8 --- /dev/null +++ b/display/trustedvm-sun-sde.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "sun-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,sde-hw-version =<0xC0000000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From c87ac12f64d27946481028513e3072171d7af335 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Fri, 19 Jan 2024 17:32:06 -0800 Subject: [PATCH 039/242] ARM: dts: msm: add secure cb to connector-list on sun target Add smmu secure context bank to the connector-list on sun target to make it as part of the drm component dependent list. Change-Id: I9e1d65f32b864f12e9683566771acdc687923380 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index d48d6045..398e121f 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -107,7 +107,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { From b74489855bfe8d6287f55b403d9768331d422ca1 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 19 Jan 2024 13:39:41 +0800 Subject: [PATCH 040/242] ARM: dts: msm: enable esd check on sun target This change enable esd check on sun target. Change-Id: I55cbf46247370b31a192b8350a60994d727d48d5 Signed-off-by: Jinfeng Gu --- display/sun-sde-display-common.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 23bce180..54797f5e 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" @@ -349,6 +349,12 @@ &dsi_nt37801_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0 { @@ -369,6 +375,12 @@ &dsi_nt37801_amoled_video_cphy { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0 { @@ -382,6 +394,12 @@ &dsi_nt37801_amoled_cmd_cphy { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0 { @@ -396,6 +414,12 @@ &dsi_nt37801_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; qcom,mdss-dsi-display-timings { timing@0 { From cc38699007b8108ddffbe22e0a1e7b2308cdac4e Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Mon, 22 Jan 2024 13:11:45 -0500 Subject: [PATCH 041/242] ARM: dts: msm: update iommu address range for sun target Update unsecure iommu address pool to exclude memory region allocated to HW-Fence. Change-Id: I20ae5e357da5346e663044bbc1565135ff3a1ca7 Signed-off-by: Jayasri Sampath Kumaran --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..1c714c37 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd4e23000 0x002dd000>, <&smmu_sde_unsec 0xd5500000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 9e5057ad5b8d9c3b54b62e4d4fde2e33a35f5d2e Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 22 Jan 2024 22:43:57 -0800 Subject: [PATCH 042/242] ARM: dts: msm: add ATP variant DT support on sun target Add DT support for ATP variant on sun target. Change-Id: I3860457c497e311e625884dad6972496cc3729c0 Signed-off-by: Veera Sundaram Sankaran --- Kbuild | 3 ++- display/sun-sde-display-atp-overlay.dts | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-atp-overlay.dts diff --git a/Kbuild b/Kbuild index a824c4d7..3060fd20 100644 --- a/Kbuild +++ b/Kbuild @@ -14,7 +14,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-nfc-overlay.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ - display/sun-sde-display-mtp-v8-overlay.dtbo + display/sun-sde-display-mtp-v8-overlay.dtbo \ + display/sun-sde-display-atp-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts new file mode 100644 index 00000000..d3b24f2d --- /dev/null +++ b/display/sun-sde-display-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun ATP"; + compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x10021 0>; +}; From 754cc63fca8f517ee9525b495e12ab2a834553f1 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Mon, 22 Jan 2024 10:58:20 +0800 Subject: [PATCH 043/242] ARM: dts: msm: Add trustedvm device tree files for Sun qrd Add the trusted VM devicetree nodes for Sun target. Change-Id: I5812f991777ed30e4a34f6cf4c4d291c9c850374 Signed-off-by: Rui Chen --- Kbuild | 3 +- .../trustedvm-sun-sde-display-qrd-overlay.dts | 18 +++++++ display/trustedvm-sun-sde-display-qrd.dtsi | 51 +++++++++++++++++++ 3 files changed, 71 insertions(+), 1 deletion(-) create mode 100644 display/trustedvm-sun-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-sun-sde-display-qrd.dtsi diff --git a/Kbuild b/Kbuild index a824c4d7..93ff5622 100644 --- a/Kbuild +++ b/Kbuild @@ -17,7 +17,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ - display/trustedvm-sun-sde-display-mtp-overlay.dtbo + display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ + display/trustedvm-sun-sde-display-qrd-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) diff --git a/display/trustedvm-sun-sde-display-qrd-overlay.dts b/display/trustedvm-sun-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..8fac6d6e --- /dev/null +++ b/display/trustedvm-sun-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/trustedvm-sun-sde-display-qrd.dtsi b/display/trustedvm-sun-sde-display-qrd.dtsi new file mode 100644 index 00000000..bee9aabe --- /dev/null +++ b/display/trustedvm-sun-sde-display-qrd.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; + From ea996a0a93c9e9c5c22d3d69833d36cc38898cb5 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Wed, 10 Jan 2024 17:11:18 +0800 Subject: [PATCH 044/242] ARM: dts: msm: enable mmrm on sun target This change enables mmrm device tree entry for supporting mdp core clock voting through mmrm on sun target. Change-Id: Ie0a10345e53d29c7080f591b42405048c7ff494d Signed-off-by: Lei Chen --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..105cab82 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -218,6 +218,7 @@ "lut_clk"; clock-rate = <0 0 575000000 575000000 19200000 575000000>; clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; From 745316e53e8d59bdffb7b2091c4b28fa2569c5ea Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Mon, 29 Jan 2024 14:19:45 -0800 Subject: [PATCH 045/242] ARM: dts: msm: add support for ipcc protocol for hw fence on sun This change adds the register address and size for ipcc base and the dpu client physical id to be used for hw fencing register access. Change-Id: I6a389626c186cc0f5a10900e890ecd33f6a606d2 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index d8fe8840..36d306c0 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -12,10 +12,12 @@ compatible = "qcom,sde-kms"; reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, - <0x0af80000 0x7000>; + <0x0af80000 0x7000>, + <0x400000 0x2000>; reg-names = "mdp_phys", "vbif_phys", - "regdma_phys"; + "regdma_phys", + "ipcc_reg"; /* interrupt config */ interrupts = ; @@ -261,6 +263,9 @@ qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; qcom,sde-reg-dma-id = <0 1>; From ab7e80ddd8f1e9537e5afe84dbe582061ebb0b01 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Fri, 26 Jan 2024 13:18:24 -0800 Subject: [PATCH 046/242] ARM: dts: msm: add entry for ssip fuse configuration Add dts entry for ssip fuse configuration on Sun platform. Change-Id: Ia88f0e73d0813c99b7464adc031c4aca8e331440 Signed-off-by: Ping Li --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..e432ad8b 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -420,6 +420,8 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature AI Scaler hardware. +- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. +- nvmem-cell-names: nvmem cell name. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -982,6 +984,9 @@ Example: qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,sde-sspp-vig-blocks { vcm@0 { cell-index = <0>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..578d63e6 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -241,6 +241,9 @@ /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; From f3e72ba454a2d19818c300322c603ce075df2a97 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Tue, 30 Jan 2024 13:09:59 +0800 Subject: [PATCH 047/242] ARM: dts: msm: Update trustedvm device tree board id for Sun MTP and CDP Update the trusted VM devicetree for Sun MTP and CDP. Change-Id: I730350197c25350632bf65adb9aff101685c281d Signed-off-by: Rui Chen --- display/trustedvm-sun-sde-display-cdp-overlay.dts | 2 +- display/trustedvm-sun-sde-display-mtp-overlay.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-sun-sde-display-cdp-overlay.dts b/display/trustedvm-sun-sde-display-cdp-overlay.dts index 8daf5e96..757c0dc7 100644 --- a/display/trustedvm-sun-sde-display-cdp-overlay.dts +++ b/display/trustedvm-sun-sde-display-cdp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x10001 0>; + qcom,board-id = <1 0>; }; diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts index fd2fea89..438ebe59 100644 --- a/display/trustedvm-sun-sde-display-mtp-overlay.dts +++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x10008 0>; + qcom,board-id = <8 0>; }; From febcd23b71babca9c5f838a7abdec2f1ca6acc75 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 11:33:00 -0800 Subject: [PATCH 048/242] ARM: dts: msm: add soccp dtsi property to sun target This change adds the soccp phandle needed for SOCCP power vote for hw-fencing usecases. Change-Id: Ife59c04e9ba166493f7b7078e0b22848d2a444e2 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 779a3da7..b334b16d 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -569,6 +569,8 @@ Optional properties: silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. - qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. +- qcom,sde-soccp-controller: The phandle for the soccp controller. + This value is optional and only required for targets with SOCCP. - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. @@ -911,6 +913,7 @@ Example: qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; + qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 36d306c0..5d73da80 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,6 +265,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-soccp-controller = <&soccp_pas>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; From 945dccd0fde70ff85699e224ced366f2767de00a Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Wed, 24 Jan 2024 15:31:57 -0800 Subject: [PATCH 049/242] ARM: dts: msm: add support to configure hw-fence ctl reg offset This change adds support for configuring mdp hw-fence ctl register offset, as this value can change from target-to-target. Change-Id: I436bec0732473c21cf4753cb292204ce618de512 Signed-off-by: Christina Oliveira --- bindings/sde.txt | 3 +++ display/sun-sde-common.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index b334b16d..6ceef390 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -574,6 +574,8 @@ Optional properties: - qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. - qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used for ipcc registers access. +- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg + offset. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -916,6 +918,7 @@ Example: qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-ipcc-protocol-id = <0x2>; qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 5d73da80..3300a722 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -266,6 +266,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ qcom,sde-reg-dma-off = <0 0x800>; From 672405ce89b79e671032c1bf3a8596af643efa87 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Tue, 30 Jan 2024 14:14:50 -0800 Subject: [PATCH 050/242] ARM: dts: msm: enable hw-fences in display driver for Sun Enable the use of hw-fences as the preferred synchronization primitives in the display driver for Sun target. Change-Id: I6f7d769f0a9002d27e68bac55095a3958587e47b Signed-off-by: Christina Oliveira --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 2 ++ 2 files changed, 7 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6ceef390..48cba952 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -103,6 +103,10 @@ Optional properties: -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - qcom,sde-hw-version: A u32 value indicates the MDSS hw version +- qcom,hw-fence-sw-version: A u32 value to indicate the hw fencing version. If set to a value + greather than zero, driver will attempt to enable the feature (if + supported by the HW). Otherwise, if this value is not set or set + to zero, feature will remain disabled. - qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. - qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. - qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. @@ -718,6 +722,7 @@ Example: #power-domain-cells = <0>; qcom,sde-hw-version = <0x70000000>; + qcom,hw-fence-sw-version = <0x1>; qcom,sde-emulated-env; qcom,sde-off = <0x1000>; qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..8188c462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -219,6 +219,8 @@ clock-rate = <0 0 575000000 575000000 19200000 575000000>; clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + qcom,hw-fence-sw-version = <0x1>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; From 3d852df744721286bd59cc0b5d2e5d6bcbfee496 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 1 Feb 2024 18:55:55 +0800 Subject: [PATCH 051/242] ARM: dts: msm: enable dfps on sun target This change enable dfps for video mode panel on sun target. Change-Id: I9ee3e2bd916b064550d2a0b64b67e6be0335610c Signed-off-by: Jinfeng Gu --- display/sun-sde-display-common.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 54797f5e..a8bff957 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -375,6 +375,10 @@ &dsi_nt37801_amoled_video_cphy { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; @@ -414,6 +418,10 @@ &dsi_nt37801_amoled_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; From d545fbead9bd81d4aa9ba45fa3c0e0ef9255efe2 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Fri, 26 Jan 2024 13:18:24 -0800 Subject: [PATCH 052/242] ARM: dts: msm: add entry for ssip fuse configuration Add dts entry for ssip fuse configuration on Sun platform. Change-Id: Ia88f0e73d0813c99b7464adc031c4aca8e331440 Signed-off-by: Ping Li Signed-off-by: Vaishali Gupta --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 2abbe5a5..cfe9127e 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -412,6 +412,8 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR hardware. +- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. +- nvmem-cell-names: nvmem cell name. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -974,6 +976,9 @@ Example: qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,sde-sspp-vig-blocks { vcm@0 { cell-index = <0>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..578d63e6 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -241,6 +241,9 @@ /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; From 317cfa341d2d4e75ef7d20263f6c7b36e3defdaf Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 2 Feb 2024 10:20:02 +0800 Subject: [PATCH 053/242] ARM: dts: msm: enable partial update on sun target This change enable partial update for cmd mode panel on sun target. Change-Id: I26eeaca7e8a5a59ca9155f5882c1977c66f4ff23 Signed-off-by: Jinfeng Gu --- display/sun-sde-display.dtsi | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 398e121f..1797a0be 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde.dtsi" @@ -139,6 +139,29 @@ qcom,ulps-enabled; }; +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 540 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; }; From 8cc1a7778de16a5d92b167bb526cf676e3092817 Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Wed, 31 Jan 2024 15:26:17 -0500 Subject: [PATCH 054/242] ARM: dts: msm: add supported platform variants for sun target Add Kiwi, v8 Power Grid, v8 Power Grid with Kiwi on RCM platform and 3.5mm on MTP platform for sun target. Add APQ SOC id and add more models for compatible property on Kiwi CDP and MTP platforms for sun target. Change-Id: I443e45414ba663cbb0672e686e9757e861379f5c Signed-off-by: Jayasri Sampath Kumaran --- Kbuild | 6 +++++- display/sun-sde-display-cdp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-3-5mm-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-mtp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-overlay.dts | 4 ++-- display/sun-sde-display-rcm-kiwi-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-kiwi-v8-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-v8-overlay.dts | 16 ++++++++++++++++ 8 files changed, 77 insertions(+), 9 deletions(-) create mode 100644 display/sun-sde-display-mtp-3-5mm-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-v8-overlay.dts create mode 100644 display/sun-sde-display-rcm-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 3060fd20..56042b05 100644 --- a/Kbuild +++ b/Kbuild @@ -15,7 +15,11 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo \ - display/sun-sde-display-atp-overlay.dtbo + display/sun-sde-display-atp-overlay.dtbo \ + display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-rcm-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts index acfc23ea..4ba523d6 100644 --- a/display/sun-sde-display-cdp-kiwi-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; - compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20001 0>; }; diff --git a/display/sun-sde-display-mtp-3-5mm-overlay.dts b/display/sun-sde-display-mtp-3-5mm-overlay.dts new file mode 100644 index 00000000..e7b19c30 --- /dev/null +++ b/display/sun-sde-display-mtp-3-5mm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60008 0>; +}; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts index 6d755f25..7dd3d0f1 100644 --- a/display/sun-sde-display-mtp-kiwi-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20008 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index 48ad6325..ba89d90c 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts new file mode 100644 index 00000000..21abbbbf --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x40015 0>; +}; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..18bdb0e6 --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x20015 0>; +}; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts new file mode 100644 index 00000000..1c7308f2 --- /dev/null +++ b/display/sun-sde-display-rcm-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x30015 0>; +}; From 5abba20156978e2d296f2761fbd1b00ea73166d9 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 23 Jan 2024 15:08:34 -0800 Subject: [PATCH 055/242] ARM: dts: msm: add panel configs for MTP and QRD Adds panel configuration blocks for panels that aren't physically on Pakala MTP and QRD to their respective device tree files. This enables using these panels in simulation mode on these devices. Change-Id: Ic9532583b2371f17879e69869924f86fe181ff93 Signed-off-by: Kirill Shpin --- display/sun-sde-display-mtp.dtsi | 86 +++++++++++++++++++- display/sun-sde-display-qrd.dtsi | 134 +++++++++++++++++++++++++++++++ 2 files changed, 219 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 3154f2e3..b3ebded1 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -1,10 +1,46 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -25,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -35,6 +81,44 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 9ffcea89..38786570 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -5,6 +5,42 @@ #include "sun-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -45,6 +81,104 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; From 4195a29a99c607be4bde16e70c58028e8266b8d5 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Thu, 8 Feb 2024 11:20:08 -0800 Subject: [PATCH 056/242] ARM: dts: msm: move soccp property for sun target This change moves the soccp phandle property needed for soccp power vote. Change-Id: I506c814517a2019a13450822f86d16e2c9a535e4 Signed-off-by: Christina Oliveira --- display/sun-sde-common.dtsi | 1 - display/sun-sde.dtsi | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 3300a722..0b2c0bb1 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,7 +265,6 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; - qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..b7ea2b0d 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -224,6 +224,8 @@ qti,smmu-proxy-cb-id = ; + qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; /* data and reg bus scale settings */ From 33797c66a4c1382550d47480cb1d04fe7b5effe7 Mon Sep 17 00:00:00 2001 From: Christopher Braga Date: Thu, 1 Feb 2024 11:11:08 -0500 Subject: [PATCH 057/242] ARM: dts: msm: introduce disp cc memory region To support MDP LUT retention, programming of the disp cc memory region is required. Update the sun DTSI definition to define the minimal disp cc memory region needed for LUT retention functionality. Change-Id: I88eb0860a540e5f83ae86e5491f31aa19fbdac38 Signed-off-by: Christopher Braga --- display/sun-sde-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 0b2c0bb1..6602d6d2 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af08000 0x24>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "disp_cc"; /* interrupt config */ interrupts = ; From 5468eee8ade549445dd96be7e0ee1a2b57fd93fa Mon Sep 17 00:00:00 2001 From: Ping Li Date: Fri, 26 Jan 2024 13:18:24 -0800 Subject: [PATCH 058/242] ARM: dts: msm: add entry for ssip fuse configuration Add dts entry for ssip fuse configuration on Sun platform. Change-Id: Ia88f0e73d0813c99b7464adc031c4aca8e331440 Signed-off-by: Ping Li (cherry picked from commit ab7e80ddd8f1e9537e5afe84dbe582061ebb0b01) --- bindings/sde.txt | 5 +++++ display/sun-sde.dtsi | 3 +++ 2 files changed, 8 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index 6ceef390..68e5ce20 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -420,6 +420,8 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature AI Scaler hardware. +- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. +- nvmem-cell-names: nvmem cell name. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -988,6 +990,9 @@ Example: qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,sde-sspp-vig-blocks { vcm@0 { cell-index = <0>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18c83c8e..578d63e6 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -241,6 +241,9 @@ /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; From 10aa7ec653a368cbeb4ac94b7f7a7c93d9384745 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Wed, 14 Feb 2024 18:27:50 +0530 Subject: [PATCH 059/242] ARM: dts: msm: Add trustedvm device tree support for Sun MTP-V8 target Add the trusted VM devicetree nodes for Sun MTP-V8 target. Change-Id: I404667e153c7295b5868cac18c013dd084e18a1f Signed-off-by: Akash Gajjar --- display/trustedvm-sun-sde-display-mtp-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-sun-sde-display-mtp-overlay.dts b/display/trustedvm-sun-sde-display-mtp-overlay.dts index 438ebe59..0871ba20 100644 --- a/display/trustedvm-sun-sde-display-mtp-overlay.dts +++ b/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <8 0>; + qcom,board-id = <8 0>, <0x40008 0>; }; From e407c7c62a2a0c74b796b24cb79228dc470defd5 Mon Sep 17 00:00:00 2001 From: Bruce Levy Date: Wed, 14 Feb 2024 22:43:48 -0800 Subject: [PATCH 060/242] Revert "ARM: dts: msm: add entry for ssip fuse configuration" This reverts commit d545fbead9bd81d4aa9ba45fa3c0e0ef9255efe2. Change-Id: I575aaa6b4c6659849e7340a706f45ace39f21c30 Signed-off-by: Bruce Levy --- bindings/sde.txt | 5 ----- display/sun-sde.dtsi | 3 --- 2 files changed, 8 deletions(-) diff --git a/bindings/sde.txt b/bindings/sde.txt index cfe9127e..2abbe5a5 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -412,8 +412,6 @@ Optional properties: hardware. - qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR hardware. -- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. -- nvmem-cell-names: nvmem cell name. - qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. - qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. - qcom,sde-vbif-id: Array of vbif ids corresponding to the @@ -976,9 +974,6 @@ Example: qcom,sde-reg-dma-xin-id = <7>; qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - nvmem-cells = <&ssip_config>; - nvmem-cell-names = "ssip_config"; - qcom,sde-sspp-vig-blocks { vcm@0 { cell-index = <0>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 578d63e6..18c83c8e 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -241,9 +241,6 @@ /* offsets are based off dspp 0, 1, 2, and 3 */ qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; - nvmem-cells = <&ssip_config>; - nvmem-cell-names = "ssip_config"; - qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; From c64196b0d010b3f9fcca3feffd044c0a14f7ca54 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 19 Feb 2024 21:08:43 -0800 Subject: [PATCH 061/242] ARM: dts: msm: modify cont-splash memory region on pakala target Modify the continuous splash memory region to match UEFI configured address. Add a gap in HLOS unsecure context-bank to avoid using the splash memory region. Change-Id: Ifa7927b8ecccd0542ef3f37cf781a97f594102b3 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 4 ++-- display/sun-sde.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 072e04fe..4e8a2575 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -48,14 +48,14 @@ }; disp_rdump_memory: disp_rdump_region@0xd5500000 { - reg = <0xd5500000 0x00800000>; + reg = <0xfc800000 0x00800000>; label = "disp_rdump_region"; }; }; &reserved_memory { splash_memory: splash_region { - reg = <0x0 0xd5500000 0x0 0x02b00000>; + reg = <0x0 0xfc800000 0x0 0x02b00000>; label = "cont_splash_region"; }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index d5cdf800..61a0bb97 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -184,7 +184,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, <&smmu_sde_unsec 0xd4e23000 0x002dd000>, - <&smmu_sde_unsec 0xd5500000 0x02b00000>, + <&smmu_sde_unsec 0xfc800000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 5521491e0241149e784565a76ce64dac7cc585b3 Mon Sep 17 00:00:00 2001 From: Yuchao Ma Date: Wed, 22 Nov 2023 18:46:08 +0800 Subject: [PATCH 062/242] ARM: dts: msm: updates demura version and size The change updates demura version and size. Change-Id: Ie3a71c6a04f38054d4a192c1b538fb53aa02e135 Signed-off-by: Yuchao Ma Signed-off-by: Alisha Thapaliya --- display/sun-sde-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 0b2c0bb1..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -192,8 +192,8 @@ qcom,sde-dspp-spr-version = <0x00020000>; qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>; - qcom,sde-dspp-demura-size = <0xe4>; - qcom,sde-dspp-demura-version = <0x00020000>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; qcom,sde-dspp-aiqe-version = <0x00010000>; From bd64dc56a2ac2525d5e6c0cb42fe1ff694925094 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 31 Jan 2024 20:58:49 +0800 Subject: [PATCH 063/242] ARM: dts: msm: add multiple timing nodes for nt37801 panel This change add multiple timing nodes for nt37801 on sun target. Change-Id: I36f3271c86a6765ca62bda60b23954d7d5efbf14 Signed-off-by: Jinfeng Gu --- ...-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 213 ++++++ .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 646 ++++++++++++++++++ display/sun-sde-display-common.dtsi | 56 ++ display/sun-sde-display.dtsi | 40 ++ 4 files changed, 955 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 5612ec26..4e2eeca5 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -53,6 +53,17 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 06 F0 55 AA 52 08 01 39 01 00 00 00 00 02 6F 01 @@ -110,6 +121,208 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <808730000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e417cdb2..105e1938 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -58,6 +58,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 02 8F 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 ]; qcom,mdss-dsi-on-command = [ @@ -137,6 +145,14 @@ 39 01 00 00 00 00 05 2A 00 00 04 37 39 01 00 00 00 00 05 2B 00 00 09 5F 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 ]; qcom,mdss-dsi-on-command = [ @@ -193,6 +209,636 @@ qcom,mdss-dsc-bit-per-pixel = <8>; qcom,mdss-dsc-block-prediction-enable; }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 04 04 00 01 + 04 04 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 04 04 00 01 + 04 04 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-framerate = <20>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 05 05 00 01 + 05 05 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 05 05 00 01 + 05 05 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; }; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index a8bff957..f2ecb087 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -370,6 +370,48 @@ qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06 + 06 06 06 02 04 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04 + 04 04 03 02 04 0e 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 03 02 02 04 0c 08]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 03 02 02 04 0b 08]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@7 { + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 02 04 0a 07]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; }; }; @@ -412,6 +454,20 @@ qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 03 + 19 03 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; }; }; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4e8a2575..13c6655e 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -162,6 +162,36 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <540 40 40 40 540 40>; }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@5 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@6 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@7 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; }; }; @@ -171,6 +201,16 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 40 40 40 720 40>; }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 40 40 720 40>; + }; }; }; From 3ac8b0243caf36bc3f9eb41d33cb691c5460f2dd Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 22 Jan 2024 22:43:57 -0800 Subject: [PATCH 064/242] ARM: dts: msm: add ATP variant DT support on sun target Add DT support for ATP variant on sun target. Change-Id: I3860457c497e311e625884dad6972496cc3729c0 Signed-off-by: Veera Sundaram Sankaran Signed-off-by: Bruce Levy --- Kbuild | 3 ++- display/sun-sde-display-atp-overlay.dts | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-atp-overlay.dts diff --git a/Kbuild b/Kbuild index 93ff5622..982f5250 100644 --- a/Kbuild +++ b/Kbuild @@ -14,7 +14,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-nfc-overlay.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ - display/sun-sde-display-mtp-v8-overlay.dtbo + display/sun-sde-display-mtp-v8-overlay.dtbo \ + display/sun-sde-display-atp-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts new file mode 100644 index 00000000..d3b24f2d --- /dev/null +++ b/display/sun-sde-display-atp-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun ATP"; + compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x10021 0>; +}; From 2275601a159e08cef7356fbdcb56ac2e42b05cda Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Wed, 31 Jan 2024 15:26:17 -0500 Subject: [PATCH 065/242] ARM: dts: msm: add supported platform variants for sun target Add Kiwi, v8 Power Grid, v8 Power Grid with Kiwi on RCM platform and 3.5mm on MTP platform for sun target. Add APQ SOC id and add more models for compatible property on Kiwi CDP and MTP platforms for sun target. Change-Id: I443e45414ba663cbb0672e686e9757e861379f5c Signed-off-by: Jayasri Sampath Kumaran Signed-off-by: Bruce Levy --- Kbuild | 6 +++++- display/sun-sde-display-cdp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-3-5mm-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-mtp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-overlay.dts | 4 ++-- display/sun-sde-display-rcm-kiwi-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-kiwi-v8-overlay.dts | 16 ++++++++++++++++ display/sun-sde-display-rcm-v8-overlay.dts | 16 ++++++++++++++++ 8 files changed, 77 insertions(+), 9 deletions(-) create mode 100644 display/sun-sde-display-mtp-3-5mm-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-overlay.dts create mode 100644 display/sun-sde-display-rcm-kiwi-v8-overlay.dts create mode 100644 display/sun-sde-display-rcm-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 982f5250..56a64758 100644 --- a/Kbuild +++ b/Kbuild @@ -15,7 +15,11 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo \ - display/sun-sde-display-atp-overlay.dtbo + display/sun-sde-display-atp-overlay.dtbo \ + display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-rcm-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts index acfc23ea..4ba523d6 100644 --- a/display/sun-sde-display-cdp-kiwi-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; - compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20001 0>; }; diff --git a/display/sun-sde-display-mtp-3-5mm-overlay.dts b/display/sun-sde-display-mtp-3-5mm-overlay.dts new file mode 100644 index 00000000..e7b19c30 --- /dev/null +++ b/display/sun-sde-display-mtp-3-5mm-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x60008 0>; +}; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts index 6d755f25..7dd3d0f1 100644 --- a/display/sun-sde-display-mtp-kiwi-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <0x20008 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index 48ad6325..ba89d90c 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts new file mode 100644 index 00000000..21abbbbf --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x40015 0>; +}; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..18bdb0e6 --- /dev/null +++ b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x20015 0>; +}; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts new file mode 100644 index 00000000..1c7308f2 --- /dev/null +++ b/display/sun-sde-display-rcm-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x30015 0>; +}; From f5b13b7e342505b1190597c08f4fab38a1a17bd2 Mon Sep 17 00:00:00 2001 From: Christina Oliveira Date: Thu, 8 Feb 2024 11:20:08 -0800 Subject: [PATCH 066/242] ARM: dts: msm: move soccp property for sun target This change moves the soccp phandle property needed for soccp power vote. Change-Id: I506c814517a2019a13450822f86d16e2c9a535e4 Signed-off-by: Christina Oliveira Signed-off-by: Bruce Levy --- display/sun-sde-common.dtsi | 1 - display/sun-sde.dtsi | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 3300a722..0b2c0bb1 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,7 +265,6 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; - qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 578d63e6..f365936b 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -224,6 +224,8 @@ qti,smmu-proxy-cb-id = ; + qcom,sde-soccp-controller = <&soccp_pas>; + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; /* data and reg bus scale settings */ From ead1903cced91a3a4bf81aadc79479ee256aa1b8 Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Mon, 22 Jan 2024 13:11:45 -0500 Subject: [PATCH 067/242] ARM: dts: msm: update iommu address range for sun target Update unsecure iommu address pool to exclude memory region allocated to HW-Fence. Change-Id: I20ae5e357da5346e663044bbc1565135ff3a1ca7 Signed-off-by: Jayasri Sampath Kumaran Signed-off-by: Vaishali Gupta --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f365936b..8fabaad4 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd4e23000 0x002dd000>, <&smmu_sde_unsec 0xd5500000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 6bd6115123989ec78b57306535a3c7b7790b66ba Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 19 Feb 2024 21:08:43 -0800 Subject: [PATCH 068/242] ARM: dts: msm: modify cont-splash memory region on pakala target Modify the continuous splash memory region to match UEFI configured address. Add a gap in HLOS unsecure context-bank to avoid using the splash memory region. Change-Id: Ifa7927b8ecccd0542ef3f37cf781a97f594102b3 Signed-off-by: Veera Sundaram Sankaran Signed-off-by: Vaishali Gupta --- display/sun-sde-display.dtsi | 4 ++-- display/sun-sde.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 072e04fe..4e8a2575 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -48,14 +48,14 @@ }; disp_rdump_memory: disp_rdump_region@0xd5500000 { - reg = <0xd5500000 0x00800000>; + reg = <0xfc800000 0x00800000>; label = "disp_rdump_region"; }; }; &reserved_memory { splash_memory: splash_region { - reg = <0x0 0xd5500000 0x0 0x02b00000>; + reg = <0x0 0xfc800000 0x0 0x02b00000>; label = "cont_splash_region"; }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 8fabaad4..b29a9f0c 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -184,7 +184,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, <&smmu_sde_unsec 0xd4e23000 0x002dd000>, - <&smmu_sde_unsec 0xd5500000 0x02b00000>, + <&smmu_sde_unsec 0xfc800000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 8794f7fa807a4fbcf0629704ffb8891e7999e91e Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Fri, 23 Feb 2024 15:26:47 -0500 Subject: [PATCH 069/242] ARM: dts: msm: add support for MTP QMP1000 variants for sun target Add QMP1000 with v6 and v8 power grid for MTP platforms for sun target. Change-Id: If9a6c99f15add5fa7d86bb821587dc971bd87619 Signed-off-by: Jayasri Sampath Kumaran --- Kbuild | 4 +++- display/sun-sde-display-mtp-qmp1000-overlay.dts | 16 ++++++++++++++++ .../sun-sde-display-mtp-qmp1000-v8-overlay.dts | 16 ++++++++++++++++ 3 files changed, 35 insertions(+), 1 deletion(-) create mode 100644 display/sun-sde-display-mtp-qmp1000-overlay.dts create mode 100644 display/sun-sde-display-mtp-qmp1000-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 56a64758..1d451b47 100644 --- a/Kbuild +++ b/Kbuild @@ -19,7 +19,9 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ display/sun-sde-display-rcm-kiwi-overlay.dtbo \ display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ - display/sun-sde-display-rcm-v8-overlay.dtbo + display/sun-sde-display-rcm-v8-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-mtp-qmp1000-overlay.dts b/display/sun-sde-display-mtp-qmp1000-overlay.dts new file mode 100644 index 00000000..00e92d1b --- /dev/null +++ b/display/sun-sde-display-mtp-qmp1000-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x10108 0>; +}; diff --git a/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts new file mode 100644 index 00000000..ce16eb03 --- /dev/null +++ b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x40108 0>; +}; From c8fc77e24c0b4ec017c3a2394b29ee70468e20a4 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Tue, 20 Feb 2024 18:58:57 +0800 Subject: [PATCH 070/242] ARM: dts: msm: add NT37801 10 bits video mode panel support This change add NT37801 10 bits video mode panel support. Change-Id: I7c82b55ed49d6e361278f8285a6ff4373febc3ed Signed-off-by: Jinfeng Gu --- .../dsi-panel-nt37801-dsc-10bit-video.dtsi | 118 ++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 13 +- display/sun-sde-display-common.dtsi | 24 ++++ display/sun-sde-display-mtp.dtsi | 13 +- 4 files changed, 166 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-10bit-video.dtsi diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi new file mode 100644 index 00000000..d7d968d6 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_video: qcom,mdss_dsi_nt37801_amoled_dsc_10b_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 c2 81 + 39 01 00 00 00 00 06 f0 55 aa 52 08 03 + 39 01 00 00 00 00 02 c6 a2 + 39 01 00 00 00 00 06 f0 55 aa 52 08 05 + 39 01 00 00 00 00 02 6f 08 + 39 01 00 00 00 00 06 ec 10 00 00 00 ff + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 2a 00 28 f1 + 9a 02 68 03 92 00 0e 03 14 02 56 10 + ec + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 04 56 77 + 77 77 99 9b f0 00 02 78 9a bb bc dd + ee ff 00 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 7c979c54..2936b501 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -67,6 +67,16 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -175,7 +185,8 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index f2ecb087..d905cd34 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -495,6 +496,29 @@ }; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index b3ebded1..52cbb310 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -61,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -168,7 +178,8 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_video>; }; }; From 33a37fea084f57bf61c98724dcd206df65b1da69 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 27 Feb 2024 17:06:43 -0800 Subject: [PATCH 071/242] ARM: dts: msm: add license/copyright to panels Adds missing license and copyright information to all panel files, which don't currently have them. Change-Id: I73b6b6da76a28a4d3e9f86924c8d2732b41f90de Signed-off-by: Kirill Shpin --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 +++++ display/dsi-panel-sharp-dsc-4k-cmd.dtsi | 5 +++++ display/dsi-panel-sharp-dsc-4k-video.dtsi | 5 +++++ display/dsi-panel-sim-cmd-au.dtsi | 5 +++++ display/dsi-panel-sim-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dsc-10bit-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dsc375-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi | 5 +++++ display/dsi-panel-sim-dualmipi-video.dtsi | 5 +++++ display/dsi-panel-sim-sec-hd-cmd.dtsi | 5 +++++ display/dsi-panel-sim-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi | 5 +++++ display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi | 5 +++++ .../dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi | 5 +++++ 21 files changed, 105 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 5612ec26..43b67ad0 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_cmd_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_cphy { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index e417cdb2..a532daeb 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_cmd: qcom,mdss_dsi_nt37801_wqhd_plus_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 53de247a..d9c48cd4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_video_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_vid_cphy { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index d4647340..8a36fe29 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_nt37801_amoled_video: qcom,mdss_dsi_nt37801_wqhd_plus_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi index 4231b746..e303a6d5 100644 --- a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi index a687b5ff..efe59f9b 100644 --- a/display/dsi-panel-sharp-dsc-4k-video.dtsi +++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; diff --git a/display/dsi-panel-sim-cmd-au.dtsi b/display/dsi-panel-sim-cmd-au.dtsi index 3815307f..fcb8df52 100644 --- a/display/dsi-panel-sim-cmd-au.dtsi +++ b/display/dsi-panel-sim-cmd-au.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au { qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au"; diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi index c10c3bce..813fe166 100644 --- a/display/dsi-panel-sim-cmd.dtsi +++ b/display/dsi-panel-sim-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi index 6c624c30..8e5cba14 100644 --- a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi index 0211f659..bed6ed91 100644 --- a/display/dsi-panel-sim-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi index b16c48d5..275c0960 100644 --- a/display/dsi-panel-sim-dualmipi-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi index e59bfb05..28f2c96f 100644 --- a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi +++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi index 537a0181..e977a78b 100644 --- a/display/dsi-panel-sim-dualmipi-video.dtsi +++ b/display/dsi-panel-sim-dualmipi-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi index dd948313..3172af60 100644 --- a/display/dsi-panel-sim-sec-hd-cmd.dtsi +++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi index 78d18c82..02fd6ca9 100644 --- a/display/dsi-panel-sim-video.dtsi +++ b/display/dsi-panel-sim-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_sim_vid: qcom,mdss_dsi_sim_video { qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi index 4096eb88..30dfc315 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi index 6f0e924b..bd6bbec8 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi index 4fcb45d3..45850567 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi index df28a81f..4c4886f9 100644 --- a/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi index c14db0a0..5143cf11 100644 --- a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd { qcom,mdss-dsi-panel-name = diff --git a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi index 6948326c..baa8e311 100644 --- a/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi +++ b/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi @@ -1,3 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + &mdss_mdp { dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video { qcom,mdss-dsi-panel-name = From 10a1d04ea4bbef0d45fc21e644dbaa5eb4746e13 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 22 Feb 2024 17:58:49 +0800 Subject: [PATCH 072/242] ARM: dts: msm: update partial update roi for csot panel This change updates the partial update roi for csot cmd mode panel. Change-Id: Iafdbe00243a5a2f3162e2dbfc2a79143ab4a29ff Signed-off-by: Jinfeng Gu --- display/sun-sde-display.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 13c6655e..f58720d7 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -155,42 +155,42 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 40 40 40 540 40>; + qcom,panel-roi-alignment = <0 0 540 40 1080 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@3 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@4 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@5 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@6 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@7 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; }; }; @@ -199,17 +199,17 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 40 40 720 40>; + qcom,panel-roi-alignment = <0 0 720 40 1440 40>; }; }; }; From 310142dab60ba20d60c7d76aa8e081cdfad0daf2 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 27 Feb 2024 14:56:58 -0800 Subject: [PATCH 073/242] ARM: dts: msm: add CSOT with SPR config Adds new variant of the CSOT command mode panel with SPR enabled on AP side, as opposed to DDIC side. Change-Id: I94cfc2150e7b714822349a5ff9392351e2e22356 Signed-off-by: Kirill Shpin --- ...i-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 132 ++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 21 ++- display/sun-sde-display-common.dtsi | 21 +++ display/sun-sde-display-mtp.dtsi | 16 ++- display/trustedvm-sun-sde-display-cdp.dtsi | 9 ++ display/trustedvm-sun-sde-display-mtp.dtsi | 9 ++ 6 files changed, 203 insertions(+), 5 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi new file mode 100644 index 00000000..76401ecf --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_spr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_spr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and AP SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsc-version = <0x12>; + qcom,src-chroma-format = <1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 A0 F0 00 32 D1 + 00 01 E2 01 9B 00 3C 02 20 08 A4 11 + 50 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 02 DE 00 + 39 01 00 00 00 00 02 6F 09 + 39 01 00 00 00 00 07 DE 10 34 25 30 14 25 + 39 01 00 00 00 00 05 FF AA 55 A5 81 + 39 01 00 00 00 00 02 6F 1D + 39 01 00 00 00 00 02 FB 6F + + 39 01 00 00 00 00 06 F0 55 AA 52 08 07 + 39 01 00 00 00 00 02 B0 24 + 39 01 00 00 00 00 02 03 10 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 2936b501..548ccf02 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "sun-sde-display.dtsi" @@ -77,6 +77,19 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -185,8 +198,9 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_dsc_10b_video>; + &dsi_nt37801_amoled_cmd_spr>; }; }; @@ -196,6 +210,7 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index d905cd34..14929b06 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -8,6 +8,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -519,6 +520,26 @@ }; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 52cbb310..ea129f5c 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -71,6 +71,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -179,7 +189,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_dsc_10b_video>; + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr>; }; }; @@ -187,5 +198,6 @@ qcom,display-panels = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; }; diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 26a92cf5..4f7bd4ec 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -54,6 +54,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index 8094ced6..61c97670 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -23,6 +23,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; From 3c8a246c1f0c9381e9766e50e4f3f9a2c8585f9e Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Fri, 1 Mar 2024 14:31:06 -0800 Subject: [PATCH 074/242] ARM: dts: msm: remove long regulator sleep Lowers the TVDD regulator's post on sleep duration from 2000ms. Change-Id: I4a0aed93eb56aab93f5b4f792c79ede1ac1fd4fc Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 14929b06..37faa1f5 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -86,7 +86,7 @@ qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; - qcom,supply-post-on-sleep = <2000>; + qcom,supply-post-on-sleep = <20>; }; }; From 39f6c30dc49c057ebedbeb0bbf18ce1e26b15c3b Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 1 Mar 2024 17:30:43 +0800 Subject: [PATCH 075/242] ARM: dts: msm: add NT37801 10 bits cmd mode panel support This change add NT37801 10 bits cmd mode panel support. Change-Id: I0e5472ea28b0e7e1725194d8b23e67b6c79509b5 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 121 +++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 11 ++ display/sun-sde-display-common.dtsi | 21 ++++ display/sun-sde-display-mtp.dtsi | 11 ++ 4 files changed, 164 insertions(+) create mode 100644 display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi new file mode 100644 index 00000000..499ea14e --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_cmd: qcom,mdss_dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 28 00 28 f2 + 00 02 c2 03 e1 00 0a 03 14 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 03 04 55 77 + 77 77 99 9b 10 00 1e 48 9a bb bc de + f0 11 30 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 548ccf02..98d492ee 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -67,6 +67,16 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -198,6 +208,7 @@ panel = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr>; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 14929b06..d7cfcb99 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -7,6 +7,7 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" @@ -497,6 +498,26 @@ }; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-supported-dfps-list = <120 110 100 90 80>; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index ea129f5c..a3792376 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -61,6 +61,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_dsc_10b_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -189,6 +199,7 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_cmd &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr>; }; From 2f2c7b99e1d2b9240ae119858243f5d12f5f9a88 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Mon, 4 Mar 2024 11:02:32 +0800 Subject: [PATCH 076/242] ARM: dts: msm: add TUI display support Add TUI touch support on vm display panel. Change-Id: I610a67f73837399b652950001251ffb1cdeec80b Signed-off-by: Rui Chen --- display/trustedvm-sun-sde-display-cdp.dtsi | 22 ++++++++++++++++++++++ display/trustedvm-sun-sde-display-mtp.dtsi | 11 +++++++++++ display/trustedvm-sun-sde-display-qrd.dtsi | 8 ++++++++ 3 files changed, 41 insertions(+) diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 4f7bd4ec..24679ff3 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -150,3 +150,25 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; + }; +}; + +&qupv3_se15_i2c { + status = "disabled"; + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr>; + }; +}; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index 61c97670..eda8e972 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -76,3 +76,14 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr>; + }; +}; diff --git a/display/trustedvm-sun-sde-display-qrd.dtsi b/display/trustedvm-sun-sde-display-qrd.dtsi index bee9aabe..cac8c524 100644 --- a/display/trustedvm-sun-sde-display-qrd.dtsi +++ b/display/trustedvm-sun-sde-display-qrd.dtsi @@ -49,3 +49,11 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video>; + }; +}; From 344e1a69e9054ee9ca3d4d2b77d78e959640afea Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 6 Mar 2024 12:00:04 +0800 Subject: [PATCH 077/242] ARM: dts: msm: enable qsync for csot panel on sun target This change enable qsync for csot panel on sun target. Change-Id: I50068d98a263f28bc68a300b445125ce5ee73dff Signed-off-by: Jinfeng Gu --- ...-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 138 ++++++++++++++++++ ...panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 137 +++++++++++++++++ ...t37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 120 +++++++++++++++ ...nel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 119 +++++++++++++++ display/sun-sde-display-cdp.dtsi | 30 +++- display/sun-sde-display-common.dtsi | 82 +++++++++++ display/sun-sde-display-mtp.dtsi | 24 ++- display/sun-sde-display-qrd.dtsi | 24 ++- 8 files changed, 671 insertions(+), 3 deletions(-) create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi create mode 100644 display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi new file mode 100644 index 00000000..be7213c7 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi new file mode 100644 index 00000000..acc300b4 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi new file mode 100644 index 00000000..7f33dd6f --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi new file mode 100644 index 00000000..7c3eadd2 --- /dev/null +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 548ccf02..dd2dac2e 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -90,6 +90,32 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -200,7 +226,9 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 37faa1f5..c9bf3e20 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -9,6 +9,10 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -540,6 +544,84 @@ }; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index ea129f5c..a5777c6a 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -81,6 +81,26 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -190,7 +210,9 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_dsc_10b_video - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video>; }; }; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index 38786570..a7ae76f7 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -81,6 +81,26 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -188,7 +208,9 @@ panel = <&dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd - &dsi_nt37801_amoled_video>; + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; }; }; From b1d94b03e7292f43c799da982fe0a14aa04da1b6 Mon Sep 17 00:00:00 2001 From: Sabarinath M B Date: Mon, 11 Mar 2024 21:22:46 +0530 Subject: [PATCH 078/242] ARM: dts: msm: modify panel-roi-alignment for csot panel Update panel-roi-alignment with correct alignment values. Change-Id: I783ff3a32008db53c59f8fa11d72b9b44cab6575 Signed-off-by: Sabarinath M B --- display/sun-sde-display.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index f58720d7..04ebf19f 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -155,42 +155,42 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 540 40 1080 40>; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@3 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@4 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@5 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@6 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@7 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; }; }; @@ -199,17 +199,17 @@ qcom,mdss-dsi-display-timings { timing@0 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@2 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <0 0 720 40 1440 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; }; }; From 249cc53776713940f2cbce584f0ac695ed000c17 Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 10:22:10 -0700 Subject: [PATCH 079/242] Revert "ARM: dts: msm: modify cont-splash memory region on pakala target" This reverts commit 6bd6115123989ec78b57306535a3c7b7790b66ba. Signed-off-by: Vaishali Gupta Change-Id: I254f85bd62967a899ce4b4cceab0d8a326932846 --- display/sun-sde-display.dtsi | 4 ++-- display/sun-sde.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4e8a2575..072e04fe 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -48,14 +48,14 @@ }; disp_rdump_memory: disp_rdump_region@0xd5500000 { - reg = <0xfc800000 0x00800000>; + reg = <0xd5500000 0x00800000>; label = "disp_rdump_region"; }; }; &reserved_memory { splash_memory: splash_region { - reg = <0x0 0xfc800000 0x0 0x02b00000>; + reg = <0x0 0xd5500000 0x0 0x02b00000>; label = "cont_splash_region"; }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index b29a9f0c..8fabaad4 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -184,7 +184,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, <&smmu_sde_unsec 0xd4e23000 0x002dd000>, - <&smmu_sde_unsec 0xfc800000 0x02b00000>, + <&smmu_sde_unsec 0xd5500000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From b774964d58c680e5b567de0b059ed73a5fae1f7a Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 10:22:14 -0700 Subject: [PATCH 080/242] Revert "ARM: dts: msm: update iommu address range for sun target" This reverts commit ead1903cced91a3a4bf81aadc79479ee256aa1b8. Signed-off-by: Vaishali Gupta Change-Id: I33c03ab81c2df6a430811eaa956aaf37aa4e15c6 --- display/sun-sde.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 8fabaad4..f365936b 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -183,7 +183,6 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, - <&smmu_sde_unsec 0xd4e23000 0x002dd000>, <&smmu_sde_unsec 0xd5500000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From a95e4ca4bb094f1cfa6dc5336e253c57bcdef81a Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 10:22:17 -0700 Subject: [PATCH 081/242] Revert "ARM: dts: msm: move soccp property for sun target" This reverts commit f5b13b7e342505b1190597c08f4fab38a1a17bd2. Signed-off-by: Vaishali Gupta Change-Id: Ief1505bb7c9f3f12729022d4ab006e08adf251ce --- display/sun-sde-common.dtsi | 1 + display/sun-sde.dtsi | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 0b2c0bb1..3300a722 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -265,6 +265,7 @@ qcom,sde-ipcc-protocol-id = <0x4>; qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-soccp-controller = <&soccp_pas>; qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; /* offsets are relative to "mdp_phys + qcom,sde-off */ diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f365936b..578d63e6 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -224,8 +224,6 @@ qti,smmu-proxy-cb-id = ; - qcom,sde-soccp-controller = <&soccp_pas>; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; /* data and reg bus scale settings */ From b2d965edd2fe6af401fff1f03db05b8f220c2fd1 Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 10:22:20 -0700 Subject: [PATCH 082/242] Revert "ARM: dts: msm: add supported platform variants for sun target" This reverts commit 2275601a159e08cef7356fbdcb56ac2e42b05cda. Signed-off-by: Vaishali Gupta Change-Id: I64176a9917a14c10b4e17dd9a3428787193e5a9f --- Kbuild | 6 +----- display/sun-sde-display-cdp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-3-5mm-overlay.dts | 16 ---------------- display/sun-sde-display-mtp-kiwi-overlay.dts | 6 +++--- display/sun-sde-display-mtp-overlay.dts | 4 ++-- display/sun-sde-display-rcm-kiwi-overlay.dts | 16 ---------------- display/sun-sde-display-rcm-kiwi-v8-overlay.dts | 16 ---------------- display/sun-sde-display-rcm-v8-overlay.dts | 16 ---------------- 8 files changed, 9 insertions(+), 77 deletions(-) delete mode 100644 display/sun-sde-display-mtp-3-5mm-overlay.dts delete mode 100644 display/sun-sde-display-rcm-kiwi-overlay.dts delete mode 100644 display/sun-sde-display-rcm-kiwi-v8-overlay.dts delete mode 100644 display/sun-sde-display-rcm-v8-overlay.dts diff --git a/Kbuild b/Kbuild index 56a64758..982f5250 100644 --- a/Kbuild +++ b/Kbuild @@ -15,11 +15,7 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ display/sun-sde-display-mtp-v8-overlay.dtbo \ - display/sun-sde-display-atp-overlay.dtbo \ - display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ - display/sun-sde-display-rcm-kiwi-overlay.dtbo \ - display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ - display/sun-sde-display-rcm-v8-overlay.dtbo + display/sun-sde-display-atp-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts index 4ba523d6..acfc23ea 100644 --- a/display/sun-sde-display-cdp-kiwi-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; - compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; qcom,board-id = <0x20001 0>; }; diff --git a/display/sun-sde-display-mtp-3-5mm-overlay.dts b/display/sun-sde-display-mtp-3-5mm-overlay.dts deleted file mode 100644 index e7b19c30..00000000 --- a/display/sun-sde-display-mtp-3-5mm-overlay.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "sun-sde-display-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x60008 0>; -}; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts index 7dd3d0f1..6d755f25 100644 --- a/display/sun-sde-display-mtp-kiwi-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>; qcom,board-id = <0x20008 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index ba89d90c..48ad6325 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -10,7 +10,7 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; - compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts deleted file mode 100644 index 21abbbbf..00000000 --- a/display/sun-sde-display-rcm-kiwi-overlay.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "sun-sde-display-rcm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; - compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <0x40015 0>; -}; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts deleted file mode 100644 index 18bdb0e6..00000000 --- a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "sun-sde-display-rcm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; - compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <0x20015 0>; -}; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts deleted file mode 100644 index 1c7308f2..00000000 --- a/display/sun-sde-display-rcm-v8-overlay.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "sun-sde-display-rcm.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; - compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <0x30015 0>; -}; From 4774f5f688779dae9fce858b91fa4b9eea0e878a Mon Sep 17 00:00:00 2001 From: Vaishali Gupta Date: Mon, 18 Mar 2024 10:22:23 -0700 Subject: [PATCH 083/242] Revert "ARM: dts: msm: add ATP variant DT support on sun target" This reverts commit 3ac8b0243caf36bc3f9eb41d33cb691c5460f2dd. Signed-off-by: Vaishali Gupta Change-Id: I6a505916c5c8c536c7e7ad292a77d5ce313f21a0 --- Kbuild | 3 +-- display/sun-sde-display-atp-overlay.dts | 16 ---------------- 2 files changed, 1 insertion(+), 18 deletions(-) delete mode 100644 display/sun-sde-display-atp-overlay.dts diff --git a/Kbuild b/Kbuild index 982f5250..93ff5622 100644 --- a/Kbuild +++ b/Kbuild @@ -14,8 +14,7 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-cdp-nfc-overlay.dtbo \ display/sun-sde-display-mtp-nfc-overlay.dtbo \ display/sun-sde-display-cdp-v8-overlay.dtbo \ - display/sun-sde-display-mtp-v8-overlay.dtbo \ - display/sun-sde-display-atp-overlay.dtbo + display/sun-sde-display-mtp-v8-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts deleted file mode 100644 index d3b24f2d..00000000 --- a/display/sun-sde-display-atp-overlay.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; -/plugin/; - -#include "sun-sde-display-mtp.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. Sun ATP"; - compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; - qcom,board-id = <0x10021 0>; -}; From c136e385826a22185422dfae47238b65a5fdc285 Mon Sep 17 00:00:00 2001 From: Xhoendi Collaku Date: Fri, 22 Mar 2024 16:01:23 +0530 Subject: [PATCH 084/242] ARM: dts: msm: add disp cc address in pakala tvm device tree This change fixes the TUI test aapplication failure due to sgl entries mismatch by adding disp cc address in device tree. Change-Id: I3013e985e669a2051c420df8da1c48f53d0e13e9 Signed-off-by: Akash Gajjar Signed-off-by: Xhoendi Collaku --- display/trustedvm-sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 22855dd8..6aaf4850 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -36,6 +36,7 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,tvm-include-reg = <0x0af08000 0x24>; qcom,sde-hw-version =<0xC0000000>; From 6e95e5d4d0a6857aed54fd3b6fceb14fd0d00da5 Mon Sep 17 00:00:00 2001 From: yadwan Date: Thu, 21 Mar 2024 14:20:56 +0800 Subject: [PATCH 085/242] ARM: dts: msm: update demura memory regions for sun This change adds demura memory entries to reservered memory regions. Change-Id: I2050ba028c2aa2cfa192d8eac817921af7d8fac6 Signed-off-by: yadwan --- display/sun-sde-display.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 04ebf19f..0395bc34 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -58,6 +58,19 @@ reg = <0x0 0xfc800000 0x0 0x02b00000>; label = "cont_splash_region"; }; + /* + * Demura memory regions are to be commented out if + * feature not in use. + */ + demura_memory_0: demura_region_0 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 0"; + }; + + demura_memory_1: demura_region_1 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 1"; + }; }; &sde_dsi { From 5b87ecc6bdb521086ea800a484dece10e2173cd2 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Sun, 17 Dec 2023 22:56:45 -0800 Subject: [PATCH 086/242] ARM: dts: msm: enable display cesta on sun target Add display cesta related DT node and configs on sun target. Move the GDSC & MDP core clk from mdp to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT for incoming io validation during the transition. Change-Id: I1f5ebf59db2169dfae3801f572c80af9e016e667 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 3 +- display/sun-sde.dtsi | 64 ++++++++++++++++++++++++---------- display/trustedvm-sun-sde.dtsi | 8 +++++ 3 files changed, 56 insertions(+), 19 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 04ebf19f..a371c74d 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -119,7 +119,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_dp &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 61a0bb97..18a66616 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -204,26 +204,63 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <575000000 575000000>; + clock-max-rate = <575000000 575000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 575000000 575000000 19200000 575000000>; - clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; - clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + + clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 575000000>; + clock-max-rate = <0 0 19200000 575000000>; qcom,hw-fence-sw-version = <0x1>; - vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ; @@ -262,15 +299,6 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; - - qcom,platform-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; }; }; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 22855dd8..93aa250c 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,6 +37,14 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,tvm-include-reg = <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 7791bd1e32a4c8749da84d4f06ed2a3e289b171b Mon Sep 17 00:00:00 2001 From: Jatin Srivastava Date: Mon, 5 Feb 2024 12:05:10 +0530 Subject: [PATCH 087/242] ARM: dts: msm: replace dtsi bindings with yaml Replace existing display dtsi bindings in text format with yaml format. Change-Id: I9964bfe20f474746739f63a5615726f3ebb7683d Signed-off-by: Jatin Srivastava --- bindings/dsi.txt | 278 ----- bindings/dsi.yaml | 226 ++++ bindings/dsi_phy.yaml | 161 +++ bindings/mdss-dsi-panel.txt | 1005 ---------------- bindings/mdss-dsi-panel.yaml | 1923 +++++++++++++++++++++++++++++++ bindings/msm_hdcp.txt | 14 - bindings/msm_hdcp.yaml | 28 + bindings/sde-dp.txt | 297 ----- bindings/sde-dp.yaml | 579 ++++++++++ bindings/sde-dsi.txt | 130 --- bindings/sde-dsi.yaml | 360 ++++++ bindings/sde-wb.txt | 23 - bindings/sde-wb.yaml | 36 + bindings/sde.txt | 1147 ------------------- bindings/sde.yaml | 2076 ++++++++++++++++++++++++++++++++++ 15 files changed, 5389 insertions(+), 2894 deletions(-) delete mode 100644 bindings/dsi.txt create mode 100644 bindings/dsi.yaml create mode 100644 bindings/dsi_phy.yaml delete mode 100644 bindings/mdss-dsi-panel.txt create mode 100644 bindings/mdss-dsi-panel.yaml delete mode 100644 bindings/msm_hdcp.txt create mode 100644 bindings/msm_hdcp.yaml delete mode 100644 bindings/sde-dp.txt create mode 100644 bindings/sde-dp.yaml delete mode 100644 bindings/sde-dsi.txt create mode 100644 bindings/sde-dsi.yaml delete mode 100644 bindings/sde-wb.txt create mode 100644 bindings/sde-wb.yaml delete mode 100644 bindings/sde.txt create mode 100644 bindings/sde.yaml diff --git a/bindings/dsi.txt b/bindings/dsi.txt deleted file mode 100644 index a3f2fc10..00000000 --- a/bindings/dsi.txt +++ /dev/null @@ -1,278 +0,0 @@ -Qualcomm Technologies Inc. snapdragon DSI output - -DSI Controller: -Required properties: -- compatible: - * "qcom,mdss-dsi-ctrl" -- reg: Physical base address and length of the registers of controller -- reg-names: The names of register regions. The following regions are required: - * "dsi_ctrl" -- interrupts: The interrupt signal from the DSI block. -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. -- clock-names: the following clocks are required: - * "mdp_core" - * "iface" - * "bus" - * "core_mmss" - * "byte" - * "pixel" - * "core" - For DSIv2, we need an additional clock: - * "src" - For DSI6G v2.0 onwards, we need also need the clock: - * "byte_intf" -- assigned-clocks: Parents of "byte" and "pixel" for the given platform. -- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided - by a DSI PHY block. See [1] for details on clock bindings. -- vdd-supply: phandle to vdd regulator device node -- vddio-supply: phandle to vdd-io regulator device node -- vdda-supply: phandle to vdda regulator device node -- phys: phandle to DSI PHY device node -- phy-names: the name of the corresponding PHY device -- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) -- ports: Contains 2 DSI controller ports as child nodes. Each port contains - an endpoint subnode as defined in [2] and [3]. - -Optional properties: -- panel@0: Node of panel connected to this DSI controller. - See files in [4] for each supported panel. -- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is - driving a panel which needs 2 DSI links. -- qcom,master-dsi: Boolean value indicating if the DSI controller is driving - the master link of the 2-DSI panel. -- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is - driving a 2-DSI panel whose 2 links need receive command simultaneously. -- pinctrl-names: the pin control state names; should contain "default" -- pinctrl-0: the default pinctrl state (active) -- pinctrl-n: the "sleep" pinctrl state -- ports: contains DSI controller input and output ports as children, each - containing one endpoint subnode. -- qcom,dsi-ctrl-shared: Boolean value indicating if the DSI controller is - shared between dual displays. - - DSI Endpoint properties: - - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's - input endpoint. For port@1, set to the MDP interface output. See [2] for - device graph info. - - - data-lanes: this describes how the physical DSI data lanes are mapped - to the logical lanes on the given platform. The value contained in - index n describes what physical lane is mapped to the logical lane n - (DATAn, where n lies between 0 and 3). The clock lane position is fixed - and can't be changed. Hence, they aren't a part of the DT bindings. See - [3] for more info on the data-lanes property. - - For example: - - data-lanes = <3 0 1 2>; - - The above mapping describes that the logical data lane DATA0 is mapped to - the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 - to phys DATA1 and logic DATA3 to phys DATA2. - - There are only a limited number of physical to logical mappings possible: - <0 1 2 3> - <1 2 3 0> - <2 3 0 1> - <3 0 1 2> - <0 3 2 1> - <1 0 3 2> - <2 1 0 3> - <3 2 1 0> - -DSI PHY: -Required properties: -- compatible: Could be the following - * "qcom,dsi-phy-28nm-hpm" - * "qcom,dsi-phy-28nm-lp" - * "qcom,dsi-phy-20nm" - * "qcom,dsi-phy-28nm-8960" - * "qcom,dsi-phy-14nm" - * "qcom,dsi-phy-10nm" -- reg: Physical base address and length of the registers of PLL, PHY. Some - revisions require the PHY regulator base address, whereas others require the - PHY lane base address. See below for each PHY revision. -- reg-names: The names of register regions. The following regions are required: - For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_regulator" - For DSI 14nm and 10nm PHYs: - * "dsi_pll" - * "dsi_phy" - * "dsi_phy_lane" -- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating - 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- power-domains: Should be <&mmcc MDSS_GDSC>. -- clocks: Phandles to device clocks. See [1] for details on clock bindings. -- clock-names: the following clocks are required: - * "iface" - For 28nm HPM/LP, 28nm 8960 PHYs: -- vddio-supply: phandle to vdd-io regulator device node - For 20nm PHY: -- vddio-supply: phandle to vdd-io regulator device node -- vcca-supply: phandle to vcca regulator device node - For 14nm PHY: -- vcca-supply: phandle to vcca regulator device node - For 10nm PHY: -- vdds-supply: phandle to vdds regulator device node - -Optional properties: -- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY - regulator is wanted. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split is enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. - -- frame-threshold-time-us: For command mode panels, this specifies the idle - time for dsi controller where no active data is - send to the panel, as controller is done sending - active pixels. If there is no desired DSI clocks - specified, then clocks will be derived from this - threshold time, which has a default value in chipset - based on the CPU processing power. - -- dsi_pll_codes: Contain an u32 array data to store dsi pll codes which were passed - from UEFI. -- qcom,dsi-phy-shared: Boolean value indicating if the DSI phy is shared - between dual displays. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/graph.txt -[3] Documentation/devicetree/bindings/media/video-interfaces.txt -[4] Documentation/devicetree/bindings/display/panel/ - -Example: - dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; - qcom,dsi-host-index = <0>; - interrupt-parent = <&mdp>; - interrupts = <4 0>; - reg-names = "dsi_ctrl"; - reg = <0xfd922800 0x200>; - power-domains = <&mmcc MDSS_GDSC>; - clock-names = - "bus", - "byte", - "core", - "core_mmss", - "iface", - "mdp_core", - "pixel"; - clocks = - <&mmcc MDSS_AXI_CLK>, - <&mmcc MDSS_BYTE0_CLK>, - <&mmcc MDSS_ESC0_CLK>, - <&mmcc MMSS_MISC_AHB_CLK>, - <&mmcc MDSS_AHB_CLK>, - <&mmcc MDSS_MDP_CLK>, - <&mmcc MDSS_PCLK0_CLK>; - - assigned-clocks = - <&mmcc BYTE0_CLK_SRC>, - <&mmcc PCLK0_CLK_SRC>; - assigned-clock-parents = - <&dsi_phy0 0>, - <&dsi_phy0 1>; - - vdda-supply = <&pma8084_l2>; - vdd-supply = <&pma8084_l22>; - vddio-supply = <&pma8084_l12>; - - phys = <&dsi_phy0>; - phy-names ="dsi-phy"; - - qcom,dual-dsi-mode; - qcom,master-dsi; - qcom,sync-dual-dsi; - qcom,dsi-ctrl-shared; - - qcom,mdss-mdp-transfer-time-us = <12000>; - frame-threshold-time-us = <800>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&dsi_active>; - pinctrl-1 = <&dsi_suspend>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi0_in: endpoint { - remote-endpoint = <&mdp_intf1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi0_out: endpoint { - remote-endpoint = <&panel_in>; - data-lanes = <0 1 2 3>; - }; - }; - }; - - panel: panel@0 { - compatible = "sharp,lq101r1sx01"; - reg = <0>; - link2 = <&secondary>; - - power-supply = <...>; - backlight = <...>; - - port { - panel_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - }; - }; - - dsi_phy0: dsi-phy@fd922a00 { - compatible = "qcom,dsi-phy-28nm-hpm"; - qcom,dsi-phy-index = <0>; - reg-names = - "dsi_pll", - "dsi_phy", - "dsi_phy_regulator"; - reg = <0xfd922a00 0xd4>, - <0xfd922b00 0x2b0>, - <0xfd922d80 0x7b>; - clock-names = "iface"; - clocks = <&mmcc MDSS_AHB_CLK>; - #clock-cells = <1>; - vddio-supply = <&pma8084_l12>; - - qcom,dsi-phy-regulator-ldo-mode; - qcom,panel-allow-phy-poweroff; - qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; - qcom,panel-force-clock-lane-hs; - pll_codes_region = <&dsi_pll_codes_data>; - qcom,dsi-phy-shared; - }; - - dsi_pll_codes_data:dsi_pll_codes { - reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; - label = "dsi_pll_codes"; - }; diff --git a/bindings/dsi.yaml b/bindings/dsi.yaml new file mode 100644 index 00000000..4fc3c0a6 --- /dev/null +++ b/bindings/dsi.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI Controller output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg: + description: Physical base address and length of the registers of controller + + reg-names: + description: The names of register regions. + required: + - "dsi_ctrl" + + interrupts: + description: The interrupt signal from the DSI block. + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + description: > + Clocks necessary for DSI operation. For DSIv2, we need an additional clock "src" and for + DSI6G v2.0 onwards, we also need the clock "byte_intf". + required: + - "mdp_core" + - "iface" + - "bus" + - "core_mmss" + - "byte" + - "pixel" + - "core" + + assigned-clocks: + description: Parents of "byte" and "pixel" for the given platform. + + assigned-clock-parents: + description: > + The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. + + vdd-supply: + description: phandle to vdd regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vddio-supply: + description: phandle to vdd-io regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + phys: + description: phandle to DSI PHY device node + $ref: /schemas/types.yaml#/definitions/phandle + + phy-names: + description: the name of the corresponding PHY device + $ref: /schemas/types.yaml#/definitions/string-array + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2) + $ref: /schemas/types.yaml#/definitions/phandle + + panel@0: + description: > + Node of panel connected to this DSI controller. + See files in [4] for each supported panel. + + qcom,dual-dsi-mode: + description: > + Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. + + qcom,master-dsi: + description: > + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. + + qcom,sync-dual-dsi: + description: > + Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. + + pinctrl-names: + description: the pin control state names; should contain "default" + + pinctrl-0: + description: the default pinctrl state (active) + + pinctrl-n: + description: the "sleep" pinctrl state + + qcom,dsi-ctrl-shared: + description: > + Boolean value indicating if the DSI controller is + shared between dual displays. + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - vdd-supply + - vddio-supply + - vdda-supply + - phys + - phy-names + - syscon-sfpb + - ports + +examples: + - | + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus", + "byte", + "core", + "core_mmss", + "iface", + "mdp_core", + "pixel"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; + + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + qcom,dsi-ctrl-shared; + + qcom,mdss-mdp-transfer-time-us = <12000>; + frame-threshold-time-us = <800>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/bindings/dsi_phy.yaml b/bindings/dsi_phy.yaml new file mode 100644 index 00000000..7d99e278 --- /dev/null +++ b/bindings/dsi_phy.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi_phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI PHY output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + enum: + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8960 + - qcom,dsi-phy-14nm + - qcom,dsi-phy-10nm + + reg: + description: > + Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. + + reg-names: + description: > + The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator" + is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed. + required: + - "dsi_pll" + - "dsi_phy" + + clock-cells: + description: > + Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. See [1] for details on clock bindings. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + const: iface + $ref: /schemas/types.yaml#/definitions/string-array + + vddio-supply: + description: > + For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator + device node + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdds-supply: + description: For 10nm PHY , phandle to vdds regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsi-phy-regulator-ldo-mode: + description: Boolean value indicating if the LDO mode PHY regulator is wanted. + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + $ref: /schemas/types.yaml#/definitions/uint32 + + frame-threshold-time-us: + description: > + For command mode panels, this specifies the idle + time for dsi controller where no active data is + send to the panel, as controller is done sending + active pixels. If there is no desired DSI clocks + specified, then clocks will be derived from this + threshold time, which has a default value in chipset + based on the CPU processing power. + $ref: /schemas/types.yaml#/definitions/uint32 + + dsi_pll_codes: + description: Contain an u32 array data to store dsi pll codes which were passed from UEFI. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-phy-shared: + description: Boolean value indicating if the DSI phy is shared between dual displays. + +required: + - compatible + - reg + - reg-names + - clock-cells + - power-domains + - clocks + - clock-names + - vddio-supply + - vcca-supply + - vdds-supply + +examples: + - | + dsi_phy0: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy-regulator-ldo-mode; + qcom,panel-allow-phy-poweroff; + qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; + qcom,panel-force-clock-lane-hs; + pll_codes_region = <&dsi_pll_codes_data>; + qcom,dsi-phy-shared; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +... diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt deleted file mode 100644 index c65c61e1..00000000 --- a/bindings/mdss-dsi-panel.txt +++ /dev/null @@ -1,1005 +0,0 @@ -QTI mdss-dsi-panel - -mdss-dsi-panel is a dsi panel device which supports panels that -are compatible with MIPI display serial interface specification. - -Required properties: -- compatible: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - This property specifies the version - for DSI HW that this panel will work with - "qcom,dsi-panel-v2" = DSI V2.0 -- status: This property applies to DSI V2 panels only. - This property should not be added for panels - that work based on version "V6.0" - DSI panels that are of different versions - are initialized by the drivers for dsi controller. - A string that has to be set to "okay/ok" - to enable the panel driver. By default this property - will be set to "disable". Will be set to "ok/okay" - status for specific platforms. -- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that - this panel will be mapped to. -- qcom,mdss-dsi-panel-width: Specifies panel width in pixels. -- qcom,mdss-dsi-panel-height: Specifies panel height in pixels. -- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel. - 3 = for rgb111 - 8 = for rgb332 - 12 = for rgb444 - 16 = for rgb565 - 18 = for rgb666 - 24 = for rgb888 -- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel. - "display_1" = DISPLAY_1 - "display_2" = DISPLAY_2 -- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY - timing settings for the panel. -- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane - timing settings for the panel. -- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: Message flags - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on - qcom dsi controller protocol. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: Message flags - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are - sent after displaying an image. -- qcom,platform-reset-gpio: Specifies the reset gpio of primary display, not required for simulation panels. - -Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in -qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, -then 3 options can be tried. - 1. Send the packet as a long packet instead - Byte 0: dcs data type = 05 (DCS short Packet) - Byte 0: dcs data type = 29 (DCS long Packet) - 2. Send the packet in one burst by prepending with the next packet in packet stream - Byte 3 = 00 (indicates this is an individual packet) - Byte 3 = 40 (indicates this will be appended to the next - individual packet in the packet stream) - 3. Prepend a NULL packet to the short packet and send both in one burst instead of - combining multiple short packets and sending them in one burst. - -Optional properties: -- cell-index: Timing node index to help driver maintain the device tree ordering. -- qcom,platform-sec-reset-gpio: Specifies the reset gpio of secondary display. -- qcom,platform-bklight-en-gpio: Specifies the gpio for enabling backlight. -- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel -- qcom,vid-on-commands: same as "qcom,mdss-dsi-on-command" except commands are - only sent for video mode. -- qcom,vid-on-commands-state: String that specifies the ctrl state for sending panel on commands. - for video mode. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,cmd-on-commands: same as "qcom,mdss-dsi-on-command" except commands are - only sent for command mode. -- qcom,cmd-on-commands-state: String that specifies the ctrl state for sending panel on commands. - for command mode. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-physical-type: A string used as a decriptive type of the panel. - "oled" : That indicate it's an OLED panel. - "lcd" : That indicate it's an LCD panel. - If it is not set, consider it is a LCD panel as default. -- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane - timing settings for the panel. This is specific to SDE DRM driver. - The value of 'n' depends on the DSI PHY h/w revision and parsing this - property properly will be taken care in the DSI PHY DRM driver. -- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels. -- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode. -- qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch. -- qcom,poms-align-panel-vsync: Boolean used to align panel TE with timing engine vsync in POMS -- qcom,mdss-dsi-bpp-switch: Boolean used to enable bpp mode switch for non-DSC modes. -- qcom,mdss-dsi-bpp-mode: Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" is set. - 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. - 30 = for rgb101010. -- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block. - Expressed as power of 2. To set as 128 lines, - this should be set to 7. -- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction. -- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3 - compression. -- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel. - Specified color order is used as default value. -- qcom,mdss-dsi-fbc-packing: Component packing. - 0 = default value. -- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation. -- qcom,mdss-dsi-fbc-bias: Bias for CD. - 0 = default value. -- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode. -- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode. -- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode. -- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget. - 0 = default value. -- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level. - 0 = default value. -- qcom,mdss-dsi-fbc-block-budget: Per block budget. - 0 = default value. -- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold. - 0 = default value. -- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value. - 0 = default value. -- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error. - 0 = default value -- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width. - 2 = default value. -- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value. - 0 = default value. -- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel. - 6 = default value. -- qcom,mdss-dsi-v-pulse-width: Vertical pulse width. - 2 = default value. -- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel. - 0 = default value -- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel. - 0 = default value -- qcom,mdss-dsi-v-top-border: Vertical top border in pixel. - 0 = default value -- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel. - 0 = default value -- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the - panel under flow color. - 0xff = default value. -- qcom,mdss-dsi-border-color: Defines the border color value if border is present. - 0 = default value. -- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator - and denominator. It contains two u32 values - numerator - followed by denominator. The jitter configurition causes - the early wakeup if panel needs to adjust before vsync. - Default jitter value is 2.0%. Max allowed value is 10%. -- qcom,dsi-wd-jitter-enable: Boolean used to enable watchdog jitter in simulator panels -- qcom,dsi-wd-ltj-max-jitter: A u32 pair with numerator and denominator specifying the - maximum jitter over a long time. -- qcom,dsi-wd-ltj-time-sec: A u32 value to specify the time over which the jitter increases. -- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to - calculate the backoff time of rsc. - Default value is 16 lines. Max allowed value is vtotal. -- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically. -- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate. - "dfps_suspend_resume_mode"= FPS change request is - implemented during suspend/resume. - "dfps_immediate_clk_mode" = FPS change request is - implemented immediately using DSI clocks. - "dfps_immediate_porch_mode_hfp" = FPS change request is - implemented immediately by changing panel horizontal - front porch values. - "dfps_immediate_porch_mode_vfp" = FPS change request is - implemented immediately by changing panel vertical - front porch values. -- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. -- qcom,dsi-supported-qsync-min-fps-list: The fps value in this list indicates the qsync min fps - corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. - qcom,dsi-supported-qsync-min-fps-list cannot be defined along with - qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be - set along with this property. -- qcom,qsync-mode-min-refresh-rate: This u32 property is used to define qsync min fps per timing node instead - of using same qsync min fps for different timing modes. For defining qsync min - fps per timing node, this property should be defined in all timing nodes or else - to define single qsync fps for all modes, - "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. - "qcom,qsync-enable" property should be set along with this property. -- qcom,dsi-qsync-avr-step-list: The u32 fps values in this optional list indicate the avr step - requirement for qsync/AVR video mode panels. When a late frame is triggered, - AVR will delay the trigger to ensure the frame transfer snaps to the next step - interval. The step rate must be a common multiple of refresh and min-fps rates. - The values in this list should correspond to the dfps-list with same indeces - when DFPS is used, or a single value which applies to all rates. -- qcom,dsi-qsync-mode-avr-step-fps: This u32 property is used to define avr step fps per timing node instead - of using same qsync avr step fps for different timing modes. - For defining avr step fps per timing node, this property should be defined - in all timing nodes or else to define single qsync avr step fps for all modes - use "qcom,mdss-dsi-qsync-avr-step-fps". -- qcom,dsi-qsync-avr-step-fps: A u32 entry to specify avr step rate supported by the panel. - "qcom,qsync-enable" property should be set along with this property. -- qcom,mdss-dsi-transfer-time-us-min Minimum supported mdp transfer time in us. This entry enables support to - dynamically set the transfer time for the given mode within the defined - range. Both min & max must be defined to enable. - qcom,mdss-dsi-transfer-time-us must be greater than this value. -- qcom,mdss-dsi-transfer-time-us-max Maximum supported mdp transfer time in us. This entry enables support to - dynamically set the transfer time for the given mode within the defined - range. Both min & max must be defined to enable. This time should not be - greater than vsync duration. - qcom,mdss-dsi-transfer-time-us must be less than this value. -- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. -- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh - rate is not specified, then the frame rate of the panel in - qcom,mdss-dsi-panel-framerate is used. -- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature - is supported. -- qcom,dsi-dyn-clk-type: A string that specifies the sub-type for the dynamic - clk feature. If dyn clk type is not specified, default - value "legacy" is used. - "legacy" = FPS is not maintained after dynamic clock switch. - "constant-fps-adjust-hfp" = FPS is maintained even after - dynamic clock switch by changing panel horizontal front - porch values. - "constant-fps-adjust-vfp" = FPS is maintained even after - dynamic clock switch by changing panel vertical front - porch values. - This dyn-clk-type entry is an optional binding which is - contingent on the enabling of dynamic clock switch. -- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight - control for this panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight - control for secondary panel. - "bl_ctrl_pwm" = Backlight controlled by PWM gpio. - "bl_ctrl_wled" = Backlight controlled by WLED. - "bl_ctrl_dcs" = Backlight controlled by DCS commands. - "bl_ctrl_external" = Backlight controlled by externally - other: Unknown backlight control. (default) -- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip. -- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight. - Required if backlight pmic control type is PWM -- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel. - 0 = default value. -- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel. - 255 = default value. -- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value. - When this boolean is set, will inverted display brightness value. -- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands. - "dsi_hs_mode" = DSI high speed mode (default) - "dsi_lp_mode" = DSI low power mode - If the string was not set, dsi_hs_mode will be set as default mode. -- qcom,mdss-brightness-max-level: Specifies the max brightness level supported. - 255 = default value. -- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel. - "delay_until_first_frame" = Delay backlight update of the panel - until the first frame is received from the HW. -- qcom,mdss-dsi-interleave-mode: Specifies interleave mode. - 0 = default value. -- qcom,mdss-dsi-panel-type: Specifies the panel operating mode. - "dsi_video_mode" = enable video mode (default). - "dsi_cmd_mode" = enable command mode. -- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost. -- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration. -- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal - for command mode panel. By default, panel TE will be used to generate the vsync. -- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync. -- qcom,qsync-enable: Boolean property to indicate if qsync is enabled/disabled. -- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. - "qcom,qsync-enable" property should be set along with this property. -- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature. -- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature. -- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode. - 0 = TE through embedded dcs command - 1 = TE through TE gpio pin. (default) -- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command. - 1 = default value. -- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start. - 0x2c = default value. -- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue. - 0x3c = default value. -- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel. - 0 = Don't send hsa/he following vs/ve packet(default) - 1 = Send hsa/he following vs/ve packet -- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during - horizontal front porch (HFP) blanking period. -- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during - horizontal back porch (HBP) blanking period. -- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during - horizontal sync active (HSA) mode. -- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line - interleave flag needs to be enabled. -- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) EOF mode. -- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during - blanking low power period (BLLP) mode. -- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode. - "non_burst_sync_pulse" = non burst with sync pulses (default). - "non_burst_sync_event" = non burst with sync start event. - "burst_mode" = burst mode. -- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666). - "tight" = Tight packing (default value). - "loose" = Loose packing. -- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier. - 0 = default value. -- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering. - "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) - "rgb_swap_rbg" = DSI_RGB_SWAP_RBG - "rgb_swap_brg" = DSI_RGB_SWAP_BRG - "rgb_swap_grb" = DSI_RGB_SWAP_GRB - "rgb_swap_gbr" = DSI_RGB_SWAP_GBR -- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled. -- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled. -- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled. -- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled. -- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch. - 0x00 = default value. -- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch. - 0x00 = default value. -- qcom,mdss-dsi-stream: Specifies the packet stream to be used. - 0 = stream 0 (default) - 1 = stream 1 -- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path. - "none" = no trigger - "trigger_te" = Tear check signal line used for trigger - "trigger_sw" = Triggered by software (default) - "trigger_sw_seof" = Software trigger and start/end of frame trigger. - "trigger_sw_te" = Software trigger and TE -- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel. - 60 = 60 frames per second (default) -- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz. - 0 = default value. -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - 14000 = default value. -- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds - to the physical width in the framebuffer information. -- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds - to the physical height in the framebuffer information. -- qcom,mdss-dsi-panel-test-pin: Specifies the panel test gpio. -- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel - (such as single-port/dual-port), if qcom,panel-mode-gpio - binding is defined in dsi controller. - "dual_port" = Set GPIO to LOW - "single_port" = Set GPIO to HIGH - "high" = Set GPIO to HIGH - "low" = Set GPIO to LOW - The default value is "dual_port". -- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid - tearing. Other tear-check properties are ignored if this property is present. - The below tear check configuration properties can be individually tuned if - tear check is enabled. -- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines. - The default value is 0xfff0. -- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded - at vsync edge. The reader pointer refers to the line number of - panel buffer that is currently being updated. - The default value is panel height. -- qcom,mdss-tear-check-sync-threshold-start: - Allows the first ROI line write to an panel when read pointer is - between the range of ROI start line and ROI start line plus this - setting. - The default value is 4. -- qcom,mdss-tear-check-sync-threshold-continue: - The minimum number of lines the write pointer needs to be - above the read pointer so that it is safe to write to the panel. - (This check is not done for the first ROI line write of an update) - The default value is 4. -- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is - added and write is kicked off if the read pointer falls within that - region. - The default value is panel height. -- qcom,mdss-tear-check-rd-ptr-trigger-intr: - Specify the read pointer value at which an interrupt has to be - generated. - The default value is panel height + 1. -- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the - timing of TE simulation with more precision. - The default value is 6000 with 60 fps. -- qcom,mdss-dsi-reset-sequence: An array that lists the - sequence of reset gpio values and sleeps - Each command will have the format defined - as below: - --> Reset GPIO value - --> Sleep value (in ms) -- qcom,partial-update-enabled: String used to enable partial - panel update for command mode panels. - "none": partial update is disabled - "single_roi": default enable mode, only single roi is sent to panel - "dual_roi": two rois are merged into one big roi. Panel ddic should be able - to process two roi's along with the DCS command to send two rois. - disabled if property is not specified. This property is specified - per timing node to support resolution restrictions. -- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating - additional idle time in dsi clock cycles that is needed - to compensate for smaller line width. -- qcom,partial-update-roi-merge: Boolean indicates roi combination is need - and function has been provided for dcs - 2A/2B command. This property is specified per timing node to support - resolution restrictions. -- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent - through the left DSI controller only in a dual-dsi configuration -- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel. -- qcom,mdss-dsi-panel-hdr-color-primaries: - Array of 8 unsigned integers denoting chromaticity of panel.These - values are specified in nits units. The value range is 0 through 50000. - To obtain real chromacity, these values should be divided by factor of - 50000. The structure of array is defined in below order - value 1: x value of white chromaticity of display panel - value 2: y value of white chromaticity of display panel - value 3: x value of red chromaticity of display panel - value 4: y value of red chromaticity of display panel - value 5: x value of green chromaticity of display panel - value 6: y value of green chromaticity of display panel - value 7: x value of blue chromaticity of display panel - value 8: y value of blue chromaticity of display panel -- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value - typical value becomes peak brightness. Value is specified in nits units. - To obtain real peak brightness, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as - ratio of peak brightness to contrast. Value is specified in nits units. - To obtain real blackness level, this value should be divided by factor of - 10000. -- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11) - before issuing hardware reset line. -- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11 - mode. This master delay (t_init_delay as per DSI spec) should be sum - of DSI internal delay to reach fuctional after power up and minimum - delay required by panel to reach functional. -- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets. -- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets. -- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode. -- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state. -- qcom,spr-pack-type: String to specify the SPR pack type of panel pixel layout - Expected string for the pack types supported by MDSS are, - "pentile", "rgbw", "yygm", "yygw" -- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its - left, top, width, height alignments and minimum width and - height values. This property is specified per timing node to support - resolution's alignment restrictions. -- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature. -- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on - qcom dsi controller protocol, to read the panel status. - This value is used to kick in the ESD recovery. - byte 0: dcs data type - byte 1: Unused - byte 2: virtual channel number - byte 3: expect ack from client (dcs read command) - byte 4: wait number of specified ms after dcs command - transmitted - byte 5, 6: 16 bits length in network byte order - byte 7 and beyond: number byte of payload -- qcom,mdss-dsi-panel-status-command-mode: - String that specifies the ctrl state for reading the panel status. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp1-command: An optional byte stream to request low - power mode on a panel -- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra - low power mode on a panel -- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low - power and ultra low power panel modes -- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for - setting the panel power mode. - "dsi_lp_mode" = DSI low power mode - "dsi_hs_mode" = DSI high speed mode -- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery. - "bta_check" = Uses BTA to check the panel status - "reg_read" = Reads panel status register to check the panel status - "reg_read_nt35596" = Reads panel status register to check the panel - status for NT35596 panel. - "te_signal_check" = Uses TE signal behaviour to check the panel status -- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values - for each of panel registers. Each length is corresponding to number of - returned parameters of register introduced in specification. -- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check - for each of register. - Some panel need only check the first few values returned from panel. - So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, - then just ignore this one. -- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register - which is used to check the panel status. The size of each array is the sum of - length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. - This can cover that Some panel may return several alternative values. -- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register - read that can be ignored before treating that the panel has gone bad. -- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports - dynamic switching from video mode to command mode - and vice versa. -- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch. - If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is - dynamic-switch-suspend-resume. - "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will - go blank during transition. - "dynamic-switch-immediate"= Switch on next frame update. Panel will - not go blank for this transition. - "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will - not go blank for this transition. -- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel - after panel has switch modes. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-out-commands: List of commands that need to be sent - to panel in order to switch out command mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-out-commands-state: String that specifies the ctrl state for sending command mode switch out - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,cmd-mode-switch-in-commands: List of commands that need to be sent - to panel in order to switch in command mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,cmd-mode-switch-in-commands-state: String that specifies the ctrl state for sending command mode switch in - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,video-mode-switch-out-commands: List of commands that need to be sent - to panel in order to switch out video mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,video-mode-switch-out-commands-state: String that specifies the ctrl state for sending video mode switch out - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,video-mode-switch-in-commands: List of commands that need to be sent - to panel in order to switch in video mode dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,video-mode-switch-in-commands-state: String that specifies the ctrl state for sending video mode switch in - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent, - either before or after switch commands during dynamic resolution - switch in DSC panels. If the property is not present, the default - behavior is to send PPS commands after the switch commands. -- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel - "180" = panel is flipped in both horizontal and vertical directions - "hflip" = panel is flipped in horizontal direction - "vflip" = panel is flipped in vertical direction -- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel - for any commands that we send. -- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always. -- qcom,panel-cphy-mode: Boolean to specify whether panel is using cphy. -- qcom,compression-mode: Select compression mode for panel. - "fbc" - frame buffer compression - "dsc" - display stream compression. - "vdc" - VESA display compression. - If "dsc" or "vdc" compression is used then config subnodes needs to be defined. -- qcom,panel-supply-entries: A node that lists the elements of the supply used to - power the DSI panel. There can be more than one instance - of this binding, in which case the entry would be appended - with the supply entry index. For a detailed description of - fields in the supply entry, refer to the qcom,ctrl-supply-entries - binding above. -- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3] - provides information about minor version while Bits[4.7] provides - major version information. It supports only DSC rev 1(Major).1(Minor) - right now. -- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates - current SCR revision information supported by panel. -- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used - to drive data stream to DSI. - Default value is 1 and max value is 2. - 2 encoder should be used only if qcom,mdss-lm-split or - qcom,split-mode with pingpong-split is used. -- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height. -- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width. - Multiple of slice width should be equal to panel-width. - Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders - are used then minimum slice width is equal to panel-width/4. -- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet. -- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression. -- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression. -- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder. -- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps - instead of standard dcs type 0x0A. -- qcom,vdc-version: An 8 bit value indicates the VDC version supported by panel. Bits[0.3] - provides information about minor version while Bits[4.7] provides - major version information. It supports only VDC rev 1(Major).2(Minor) - right now. -- qcom,vdc-version-release: An 8 bit value indicated VDC version release. This has to be set to 0. -- qcom,vdc-slice-height: An u32 value which indicates slice height. This should be at least 16 lines. -- qcom,vdc-slice-width: An u32 value which indicates slice width. This should be at least 64 pixels and - should also be a multiple of 8 -- qcom,vdc-slice-per-pkt: An u32 value indicates the slice per dsi packet. -- qcom,vdc-bit-per-component: An u32 value indicates the bits per component before compression. -- qcom,vdc-bit-per-pixel: An u32 value indicates the bits per pixel after compression. -- qcom,src-color-space: An u32 value indicating the source color space. It can either be RGB or YUV. - Default value is assumed to be RGB - 0 - RGB - 1 - YUV -- qcom,src-chroma-format: An u32 value indicating the source color space. It can either be 444, 420 or 422. - Default value is assumed to be 444 - 0 - 444 - 1 - 422 - 2 - 420 -- qcom,mdss-pps-delay-ms: An u32 value that indicates post PPS command - delay in milliseconds. If no value is specified, it chooses zero by default. -- qcom,display-topology: Array of u32 values which specifies the list of topologies available - for the display. A display topology is defined by a - set of 3 values in the order: - - number of mixers - - number of compression encoders - - number of interfaces - Therefore, the array should always contain a tuple of 3 elements. -- qcom,default-topology-index: An u32 value which indexes the topology set - specified by the node "qcom,display-topology" - to identify the default topology for the - display. The first set is indexed by the - value 0. -- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. -- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active - region for video mode panels and line number after TE for command mode - panels, at which command DMA needs to be triggered. -- qcom,mdss-dsi-dma-schedule-window: An integer value indicates the width of the DMA window during which a - DCS command will be triggered for command mode panels -- qcom,mdss-dsi-mdp-idle-ctrl-en: A boolean to enable LP11 insertion after transmission of every line. - This requires command mdp burst mode to be disabled. -- qcom,mdss-dsi-mdp-idle-ctrl-len: An u32 value indicating the number of dsi pclk cycles of idle time - to insert between command mode mdp packets. This time must be long - enough to cover the time link takes to switch between HS to LP11 mode. -- qcom,vert-padding-value: An u32 value indicating the second display height while using two displays - in shared display feature. - -Required properties for sub-nodes: None -Optional properties: -- qcom,dba-panel: Indicates whether the current panel is used as a display bridge - to a non-DSI interface. -- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name - is required if qcom,dba-panel is defined for the panel. -- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate - s/w delay while configuring the event timer wakeup logic. - -- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports. - Each child represents timings settings for a specific resolution. -- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional - to show proper display. -- qcom,mdss-dsi-video-mode: A boolean to indicates current timing can only work in video mode. -- qcom,mdss-dsi-cmd-mode: A boolean to indicates current timing can only work in command mode. - -Additional properties added to the second level nodes that represent timings properties: -- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default - timing configuration that will be used. -- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent - to panel when the resolution/timing switch happens dynamically. - Refer to "qcom,mdss-dsi-on-command" section for adding commands. -- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch - commands. - "dsi_lp_mode" = DSI low power mode (default) - "dsi_hs_mode" = DSI high speed mode -- qcom,dsi-dyn-clk-list: An u32 array of all the supported dsi bit clock - frequencies in Hz for the given mode, listed in - order of preference. -- qcom,disable-rsc-solver: Timing node property to dynamically disable RSC solver for - high FPS usecase due to lower bitclk rate. - -Note, if a given optional qcom,* binding is not present, then the driver will configure -the default values specified. - -Example: -&mdss_mdp { - dsi_sim_vid: qcom,mdss_dsi_sim_video { - qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; - qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; - qcom,mdss-dsi-panel-height = <1280>; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-bpp = <24>; - qcom,mdss-dsi-pixel-packing = <0>; - qcom,mdss-dsi-panel-destination = "display_1"; - qcom,cmd-sync-wait-broadcast; - qcom,mdss-dsi-fbc-enable; - qcom,mdss-dsi-panel-mode-switch; - qcom,poms-align-panel-vsync; - qcom,mdss-dsi-bpp-switch; - qcom,mdss-dsi-fbc-slice-height = <5>; - qcom,mdss-dsi-fbc-2d-pred-mode; - qcom,mdss-dsi-fbc-ver2-mode; - qcom,mdss-dsi-fbc-bpp = <0>; - qcom,mdss-dsi-fbc-packing = <0>; - qcom,mdss-dsi-fbc-quant-error; - qcom,mdss-dsi-fbc-bias = <0>; - qcom,mdss-dsi-fbc-pat-mode; - qcom,mdss-dsi-fbc-vlc-mode; - qcom,mdss-dsi-fbc-bflc-mode; - qcom,mdss-dsi-fbc-h-line-budget = <0>; - qcom,mdss-dsi-fbc-budget-ctrl = <0>; - qcom,mdss-dsi-fbc-block-budget = <0>; - qcom,mdss-dsi-fbc-lossless-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-threshold = <0>; - qcom,mdss-dsi-fbc-rgb-threshold = <0>; - qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; - qcom,mdss-dsi-fbc-max-pred-err = <2>; - qcom,mdss-dsi-h-front-porch = <140>; - qcom,mdss-dsi-h-back-porch = <164>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <6>; - qcom,mdss-dsi-v-front-porch = <1>; - qcom,mdss-dsi-v-pulse-width = <1>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-border-color = <0>; - qcom,mdss-dsi-underflow-color = <0xff>; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = < 15>; - qcom,mdss-brightness-max-level = <255>; - qcom,bl-update-flag = "delay_until_first_frame"; - qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-interleave-mode = <0>; - qcom,mdss-dsi-panel-type = "dsi_video_mode"; - qcom,mdss-dsi-te-check-enable; - qcom,mdss-dsi-te-using-wd; - qcom,mdss-dsi-te-using-te-pin; - qcom,qsync-enable; - qcom,mdss-dsi-qsync-min-refresh-rate = <30>; - qcom,mdss-dsi-te-dcs-command = <1>; - qcom,mdss-dsi-wr-mem-continue = <0x3c>; - qcom,mdss-dsi-wr-mem-start = <0x2c>; - qcom,mdss-dsi-te-pin-select = <1>; - qcom,mdss-dsi-h-sync-pulse = <1>; - qcom,mdss-dsi-hfp-power-mode; - qcom,mdss-dsi-hbp-power-mode; - qcom,mdss-dsi-hsa-power-mode; - qcom,mdss-dsi-bllp-eof-power-mode; - qcom,mdss-dsi-bllp-power-mode; - qcom,mdss-dsi-last-line-interleave; - qcom,mdss-dsi-traffic-mode = <0>; - qcom,mdss-dsi-virtual-channel-id = <0>; - qcom,mdss-dsi-color-order = <0>; - qcom,mdss-dsi-lane-0-state; - qcom,mdss-dsi-lane-1-state; - qcom,mdss-dsi-lane-2-state; - qcom,mdss-dsi-lane-3-state; - qcom,mdss-dsi-t-clk-post = <0x20>; - qcom,mdss-dsi-t-clk-pre = <0x2c>; - qcom,mdss-dsi-stream = <0>; - qcom,mdss-dsi-mdp-trigger = <0>; - qcom,mdss-dsi-dma-trigger = <0>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 - 22 27 1e 03 04 00]; - qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 20 06 09 05 03 04 a0 - 23 2e 06 08 05 03 04 a0]; - qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 FF 99]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; - qcom,dsi-supported-dfps-list = <30 45 60>; - qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; - qcom,dsi-qsync-avr-step-list = <0 360 660>; - qcom,dsi-qsync-avr-step-fps = <360>; - qcom,min-refresh-rate = <30>; - qcom,max-refresh-rate = <60>; - qcom,mdss-dsi-bl-pmic-bank-select = <0>; - qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; - qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; - qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; - qcom,mdss-pan-physical-width-dimension = <60>; - qcom,mdss-pan-physical-height-dimension = <140>; - qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; - qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; - qcom,mdss-tear-check-sync-init-val = <1280>; - qcom,mdss-tear-check-sync-threshold-start = <4>; - qcom,mdss-tear-check-sync-threshold-continue = <4>; - qcom,mdss-tear-check-start-pos = <1280>; - qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; - qcom,mdss-tear-check-frame-rate = <6000>; - qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; - qcom,dcs-cmd-by-left; - qcom,mdss-dsi-lp11-init; - qcom,mdss-dsi-init-delay-us = <100>; - mdss-dsi-rx-eot-ignore; - mdss-dsi-tx-eot-append; - qcom,ulps-enabled; - qcom,suspend-ulps-enabled; - qcom,esd-check-enabled; - qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; - qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-panel-status-check-mode = "reg_read"; - qcom,mdss-dsi-panel-status-read-length = <8>; - qcom,mdss-dsi-panel-max-error-count = <3>; - qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; - qcom,dynamic-mode-switch-enabled; - qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; - qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 - 29 01 00 00 10 00 02 B0 03]; - qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B - 15 01 00 00 00 00 02 C2 08]; - qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; - qcom,send-pps-before-switch; - qcom,panel-ack-disabled; - qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, - <40 120 128>, - <128 240 64>; - qcom,mdss-dsi-panel-orientation = "180" - qcom,mdss-dsi-panel-jitter = <0x8 0x10>; - qcom,mdss-dsi-panel-prefill-lines = <0x10>; - qcom,mdss-dsi-force-clock-lane-hs; - qcom,compression-mode = "dsc"; - qcom,adjust-timer-wakeup-ms = <1>; - qcom,platform-reset-gpio = <&tlmm 0 0>; - - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; - - qcom,mdss-dsi-display-timings { - wqhd { - cell-index = <0>; - qcom,mdss-dsi-cmd-mode; - qcom,mdss-dsi-video-mode; - qcom,mdss-dsi-bpp-mode = <24>; - qcom,mdss-dsi-timing-default; - qcom,mdss-dsi-panel-width = <720>; - qcom,mdss-dsi-panel-height = <2560>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <8>; - qcom,mdss-dsi-h-pulse-width = <8>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <4>; - qcom,mdss-dsi-v-front-porch = <728>; - qcom,mdss-dsi-v-pulse-width = <4>; - qcom,mdss-dsi-panel-framerate = <60>; - qcom,mdss-dsi-panel-clockrate = <424000000>; - qcom,mdss-mdp-transfer-time-us = <12500>; - qcom,dsi-wd-jitter-enable; - qcom,mdss-dsi-panel-jitter = <0x2 0x1>; - qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; - qcom,dsi-wd-ltj-time-sec = <3600>; - qcom,mdss-mdp-transfer-time-us-min = <10000>; - qcom,mdss-mdp-transfer-time-us-max = <15000>; - qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; - qcom,mdss-dsi-t-clk-post = <0x02>; - qcom,mdss-dsi-t-clk-pre = <0x2a>; - qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 - 05 01 00 00 02 00 02 29 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-timing-switch-command = [ - 29 00 00 00 00 00 02 B0 04 - 29 00 00 00 00 00 02 F1 00]; - qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; - qcom,qsync-mode-min-refresh-rate = <48>; - qcom,dsi-qsync-mode-avr-step-fps = <360>; - qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; - qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; - qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; - qcom,video-mode-switch-out-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; - qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; - qcom,video-mode-switch-in-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; - qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; - qcom,cmd-mode-switch-in-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; - qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; - qcom,cmd-mode-switch-out-commands = [ - 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; - qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; - - qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; - - qcom,vert-padding-value = <2940>; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>; - qcom,default-topology-index = <0>; - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <4 4 2 2 20 20>; - }; - }; - qcom,panel-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,panel-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <2800000>; - qcom,supply-max-voltage = <2800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - - qcom,panel-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; - qcom,supply-enable-load = <100000>; - qcom,supply-disable-load = <100>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - qcom,dba-panel; - qcom,bridge-name = "adv7533"; - qcom,mdss-dsc-version = <0x11>; - qcom,mdss-dsc-scr-version = <0x1>; - qcom,mdss-dsc-slice-height = <16>; - qcom,mdss-dsc-slice-width = <360>; - qcom,mdss-dsc-slice-per-pkt = <2>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - qcom,mdss-dsc-config-by-manufacture-cmd; - qcom,display-topology = <1 1 1>, - <2 2 1>; - qcom,default-topology-index = <0>; - qcom,vdc-version = <0x12>; - qcom,vdc-version-release = <0>; - qcom,vdc-slice-height = <256>; - qcom,vdc-slice-width = <720>; - qcom,vdc-slice-per-pkt = <2>; - qcom,vdc-bit-per-component = <8>; - qcom,vdc-bit-per-pixel = <6>; - qcom,src-color-space = <0>; - qcom,src-chroma-format = <0>; - qcom,mdss-dsi-dma-schedule-line = <5>; - qcom,mdss-dsi-dma-schedule-window = <50>; - }; -}; diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml new file mode 100644 index 00000000..54e88f3a --- /dev/null +++ b/bindings/mdss-dsi-panel.yaml @@ -0,0 +1,1923 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mdss-dsi-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QTI mdss-dsi-panel + +description: > + mdss-dsi-panel is a dsi panel device which supports panels that + are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + This property specifies the version + for DSI HW that this panel will work with + "qcom,dsi-panel-v2" = DSI V2.0 + + status: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + A string that has to be set to "okay/ok" + to enable the panel driver. By default this property + will be set to "disable". Will be set to "ok/okay" + status for specific platforms. + default: disable + + qcom,mdss-dsi-panel-controller: + description: > + Specifies the phandle for the DSI controller that + this panel will be mapped to. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,mdss-dsi-panel-width: + description: Specifies panel width in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-height: + description: Specifies panel height in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bpp: + description: > + Specifies the panel bits per pixel. + 3 = for rgb111 + 8 = for rgb332 + 12 = for rgb444 + 16 = for rgb565 + 18 = for rgb666 + 24 = for rgb888 + enum: [3, 8, 12, 16, 18, 24] + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-destination: + description: > + A string that specifies the destination display for the panel. + "display_1" = DISPLAY_1 + "display_2" = DISPLAY_2 + $ref: /schemas/types.yaml#/definitions/string-array + enum: [display_1, display_2] + + qcom,mdss-dsi-panel-timings: + description: > + An array of length 12 that specifies the PHY timing settings for + the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 12 + maxItems: 12 + + qcom,mdss-dsi-panel-timings-8996: + description: > + An array of length 40 char that specifies the 8996 PHY lane + timing settings for the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 40 + maxItems: 40 + + qcom,mdss-dsi-on-command: + description: > + A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: Message flags + byte 4: wait number of specified ms after dcs command transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in + qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, + then 3 options can be tried. + 1. Send the packet as a long packet instead + Byte 0: dcs data type = 05 (DCS short Packet) + Byte 0: dcs data type = 29 (DCS long Packet) + 2. Send the packet in one burst by prepending with the next packet in packet stream + Byte 3 = 00 (indicates this is an individual packet) + Byte 3 = 40 (indicates this will be appended to the next + individual packet in the packet stream) + 3. Prepend a NULL packet to the short packet and send both in one burst instead of + combining multiple short packets and sending them in one burst. + + qcom,mdss-dsi-off-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol. + Refer to qcom,mdss-dsi-on-command for command format. + + qcom,mdss-dsi-post-panel-on-command: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + sent after displaying an image. + + qcom,platform-reset-gpio: + description: > + Specifies the reset gpio of primary display, not required for simulation + panels. + + cell-index: + description: Timing node index to help driver maintain the device tree ordering. + + qcom,platform-sec-reset-gpio: + description: Specifies the reset gpio of secondary display. + + qcom,platform-bklight-en-gpio: + description: Specifies the gpio for enabling backlight. + + qcom,mdss-dsi-panel-name: + description: A string used as a descriptive name of the panel + + qcom,vid-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for video mode. + + qcom,vid-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for video mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + default: dsi_lp_mode + + qcom,cmd-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for command mode. + + qcom,cmd-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for command mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + + qcom,mdss-dsi-physical-type: + description: > + A string used as a decriptive type of the panel. + "oled" : That indicate it's an OLED panel. + "lcd" : That indicate it's an LCD panel. + If it is not set, consider it is a LCD panel as default. + default: lcd + enum: [oled, lcd] + + qcom,mdss-dsi-panel-phy-timings: + description: > + An array of length 'n' char that specifies the DSI PHY lane + timing settings for the panel. This is specific to SDE DRM driver. + The value of 'n' depends on the DSI PHY h/w revision and parsing this + property properly will be taken care in the DSI PHY DRM driver. + + qcom,cmd-sync-wait-broadcast: + description: Boolean used to broadcast dcs command to panels. + + qcom,mdss-dsi-fbc-enable: + description: Boolean used to enable frame buffer compression mode. + + qcom,mdss-dsi-panel-mode-switch: + description: Boolean used to enable panel operating mode switch. + + qcom,poms-align-panel-vsync: + description: Boolean used to align panel TE with timing engine vsync in POMS + + qcom,mdss-dsi-bpp-switch: + description: Boolean used to enable bpp mode switch for non-DSC modes. + + qcom,mdss-dsi-bpp-mode: + description: > + Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" + is set. + 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. + 30 = for rgb101010. + enum: [24, 30] + + qcom,mdss-dsi-fbc-slice-height: + description: > + Slice height(in lines) of compressed block. + Expressed as power of 2. To set as 128 lines, + this should be set to 7. + + qcom,mdss-dsi-fbc-2d-pred-mode: + description: Boolean to enable 2D map prediction. + + qcom,mdss-dsi-fbc-ver2-mode: + description: Boolean to enable FBC 2.0 that supports 1/3 compression. + + qcom,mdss-dsi-fbc-bpp: + description: > + Compressed bpp supported by the panel. + Specified color order is used as default value. + + qcom,mdss-dsi-fbc-packing: + description: Component packing. 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-quant-error: + description: Boolean used to enable quantization error calculation. + + qcom,mdss-dsi-fbc-bias: + description: > + Bias for CD. + 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-pat-mode: + description: Boolean used to enable PAT mode. + + qcom,mdss-dsi-fbc-vlc-mode: + description: Boolean used to enable VLC mode. + + qcom,mdss-dsi-fbc-bflc-mode: + description: Boolean used to enable BFLC mode. + + qcom,mdss-dsi-fbc-h-line-budget: + description: > + Per line extra budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-budget-ctrl: + description: > + Extra budget level. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-block-budget: + description: Per block budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossless-threshold: + description: > + Lossless mode threshold. + 0 = default value.. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-threshold: + description: > + Lossy mode threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-rgb-threshold: + description: > + Lossy RGB threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-mode-idx: + description: > + Lossy mode index value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-max-pred-err: + description: > + Max quantization prediction error. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-back-porch: + description: > + Horizontal back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-front-porch: + description: > + Horizontal front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-pulse-width: + description: > + Horizontal pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-skew: + description: > + Horizontal sync skew value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-back-porch: + description: > + Vertical back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-front-porch: + description: > + Vertical front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-pulse-width: + description: > + Vertical pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-left-border: + description: > + Horizontal left border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-right-border: + description: > + Horizontal right border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-top-border: + description: > + Vertical top border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-bottom-border: + description: > + Vertical bottom border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-underflow-color: + description: > + Specifies the controller settings for the + panel under flow color. + 0xff = default value. + default: 0xff + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-border-color: + description: > + Defines the border color value if border is present. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-jitter: + description: > + Panel jitter value is expressed in terms of numerator + and denominator. It contains two u32 values - numerator + followed by denominator. The jitter configurition causes + the early wakeup if panel needs to adjust before vsync. + Default jitter value is 2.0%. Max allowed value is 10%. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + minItems: 2 + items: + - description: numerator of jitter configuration + - description: denominator of jitter configuration + + qcom,dsi-wd-jitter-enable: + description: Boolean used to enable watchdog jitter in simulator panels + + qcom,dsi-wd-ltj-max-jitter: + description: > + A u32 pair with numerator and denominator specifying the + maximum jitter over a long time. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + qcom,dsi-wd-ltj-time-sec: + description: A u32 value to specify the time over which the jitter increases. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-prefill-lines: + description: > + An integer value defines the panel prefill lines required to + calculate the backoff time of rsc. + Default value is 16 lines. Max allowed value is vtotal. + default: 16 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-pan-enable-dynamic-fps: + description: Boolean used to enable change in frame rate dynamically. + + qcom,mdss-dsi-pan-fps-update: + description: > + A string that specifies when to change the frame rate. + "dfps_suspend_resume_mode"= FPS change request is + implemented during suspend/resume. + "dfps_immediate_clk_mode" = FPS change request is + implemented immediately using DSI clocks. + "dfps_immediate_porch_mode_hfp" = FPS change request is + implemented immediately by changing panel horizontal + front porch values. + "dfps_immediate_porch_mode_vfp" = FPS change request is + implemented immediately by changing panel vertical + front porch values. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-supported-dfps-list: + description: List containing all the supported refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-supported-qsync-min-fps-list: + description: > + The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be + set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,qsync-mode-min-refresh-rate: + description: > + This u32 property is used to define qsync min fps per timing node instead + of using same qsync min fps for different timing modes. For defining qsync min + fps per timing node, this property should be defined in all timing nodes or else + to define single qsync fps for all modes, + "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-list: + description: > + The u32 fps values in this optional list indicate the avr step + requirement for qsync/AVR video mode panels. When a late frame is triggered, + AVR will delay the trigger to ensure the frame transfer snaps to the next step + interval. The step rate must be a common multiple of refresh and min-fps rates. + The values in this list should correspond to the dfps-list with same indeces + when DFPS is used, or a single value which applies to all rates. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-mode-avr-step-fps: + description: > + This u32 property is used to define avr step fps per timing node instead + of using same qsync avr step fps for different timing modes. + For defining avr step fps per timing node, this property should be defined + in all timing nodes or else to define single qsync avr step fps for all modes + use "qcom,mdss-dsi-qsync-avr-step-fps". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-fps: + description: > + A u32 entry to specify avr step rate supported by the panel. + "qcom,qsync-enable" property should be set along with this property + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-min: + description: > + Minimum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. + qcom,mdss-dsi-transfer-time-us must be greater than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-max: + description: > + Maximum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. This time should not be + greater than vsync duration. + qcom,mdss-dsi-transfer-time-us must be less than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,min-refresh-rate: + description: Minimum refresh rate supported by the panel. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,max-refresh-rate: + description: > + Maximum refresh rate supported by the panel. If max refresh + rate is not specified, then the frame rate of the panel in + qcom,mdss-dsi-panel-framerate is used. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-dyn-clk-enable: + description: > + Boolean to indicate dsi dynamic clock switch feature + is supported. + + qcom,dsi-dyn-clk-type: + description: > + A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. + $ref: /schemas/types.yaml#/definitions/string-array + default: legacy + + qcom,mdss-dsi-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for this panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-sec-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for secondary panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-bl-pwm-pmi: + description: Boolean to indicate that PWM control is through second pmic chip. + + qcom,mdss-dsi-bl-pmic-bank-select: + description: > + LPG channel for backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-pmic-pwm-frequency: + description: > + PWM period in microseconds. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-pwm-gpio: + description: > + PMIC gpio binding to backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-min-level: + description: > + Specifies the min backlight level supported by the panel. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-max-level: + description: > + Specifies the max backlight level supported by the panel. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-inverted-dbv: + description: > + A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. + + qcom,bl-dsc-cmd-state: + description: > + String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_hs_mode + enum: [dsi_hs_mode, dsi_lp_mode] + + qcom,mdss-brightness-max-level: + description: > + Specifies the max brightness level supported. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,bl-update-flag: + description: > + A string that specifies controls for backlight update of the panel. + "delay_until_first_frame" = Delay backlight update of the panel + until the first frame is received from the HW. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-interleave-mode: + description: > + Specifies interleave mode. + 0 = default value. + default: 0 + + qcom,mdss-dsi-panel-type: + description: > + Specifies the panel operating mode. + "dsi_video_mode" = enable video mode (default). + "dsi_cmd_mode" = enable command mode. + default: dsi_video_mode + + qcom,5v-boost-gpio: + description: Specifies the panel gpio for display 5v boost. + + qcom,mdss-dsi-te-check-enable: + description: Boolean to enable Tear Check configuration. + + qcom,mdss-dsi-te-using-wd: + description: > + Boolean entry enables the watchdog timer support to generate the vsync signal + for command mode panel. By default, panel TE will be used to generate the vsync. + + qcom,mdss-dsi-te-using-te-pin: + description: Boolean to specify whether using hardware vsync. + + qcom,qsync-enable: + description: Boolean property to indicate if qsync is enabled/disabled. + + qcom,mdss-dsi-qsync-min-refresh-rate: + description: > + A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-qsync-on-commands: + description: String that specifies the commands to enable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-on-commands-state: + description: > + String that specifies the ctrl state for sending qsync on commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-qsync-off-commands: + description: String that specifies the commands to disable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-off-commands-state: + description: > + String that specifies the ctrl state for sending qsync off commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-te-pin-select: + description: > + Specifies TE operating mode. + 0 = TE through embedded dcs command + 1 = TE through TE gpio pin. (default) + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-te-dcs-command: + description: > + Inserts the dcs command. + 1 = default value. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-start: + description: > + DCS command for write_memory_start. + 0x2c = default value. + default: 0x2c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-continue: + description: > + DCS command for write_memory_continue. + 0x3c = default value. + default: 0x3c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-pulse: + description: > + Specifies the pulse mode option for the panel. + 0 = Don't send hsa/he following vs/ve packet(default) + 1 = Send hsa/he following vs/ve packet + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-hfp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal front porch (HFP) blanking period. + + qcom,mdss-dsi-hbp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal back porch (HBP) blanking period. + + qcom,mdss-dsi-hsa-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal sync active (HSA) mode. + + qcom,mdss-dsi-last-line-interleave: + description: > + Boolean to determine if last line + interleave flag needs to be enabled. + + qcom,mdss-dsi-bllp-eof-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) EOF mode. + + qcom,mdss-dsi-bllp-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) mode. + + qcom,mdss-dsi-traffic-mode: + description: > + Specifies the panel traffic mode. + "non_burst_sync_pulse" = non burst with sync pulses (default). + "non_burst_sync_event" = non burst with sync start event. + "burst_mode" = burst mode. + default: non_burst_sync_pulse + enum: [non_burst_sync_pulse, non_burst_sync_event, burst_mode] + + qcom,mdss-dsi-pixel-packing: + description: > + Specifies if pixel packing is used (in case of RGB666). + "tight" = Tight packing (default value). + "loose" = Loose packing. + default: tight + enum: [tight, loose] + + qcom,mdss-dsi-virtual-channel-id: + description: > + Specifies the virtual channel identefier. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-color-order: + description: > + Specifies the R, G and B channel ordering. + "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) + "rgb_swap_rbg" = DSI_RGB_SWAP_RBG + "rgb_swap_brg" = DSI_RGB_SWAP_BRG + "rgb_swap_grb" = DSI_RGB_SWAP_GRB + "rgb_swap_gbr" = DSI_RGB_SWAP_GBR + default: rgb_swap_rgb + enum: [rgb_swap_rgb, rgb_swap_rbg, rgb_swap_brg, rgb_swap_grb, rgb_swap_gbr] + + qcom,mdss-dsi-lane-0-state: + description: Boolean that specifies whether data lane 0 is enabled. + + qcom,mdss-dsi-lane-1-state: + description: Boolean that specifies whether data lane 1 is enabled. + + qcom,mdss-dsi-lane-2-state: + description: Boolean that specifies whether data lane 2 is enabled. + + qcom,mdss-dsi-lane-3-state: + description: Boolean that specifies whether data lane 3 is enabled. + + qcom,mdss-dsi-t-clk-post: + description: > + Specifies the byte clock cycles after mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-t-clk-pre: + description: > + Specifies the byte clock cycles before mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-stream: + description: > + Specifies the packet stream to be used. + 0 = stream 0 (default) + 1 = stream 1 + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-mdp-trigger: + description: > + Specifies the trigger mechanism to be used for MDP path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_te] + + qcom,mdss-dsi-dma-trigger: + description: > + Specifies the trigger mechanism to be used for DMA path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_seof" = Software trigger and start/end of frame trigger. + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_seof, trigger_sw_te] + + qcom,mdss-dsi-panel-framerate: + description: > + Specifies the frame rate for the panel. + 60 = 60 frames per second (default) + default: 60 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-clockrate: + description: > + A 64 bit value specifies the panel clock speed in Hz. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + 14000 = default value. + default: 14000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-off-command-state: + description: > + String that specifies the ctrl state for sending OFF commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-post-mode-switch-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands post mode switch. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-pan-physical-width-dimension: + description: > + Specifies panel physical width in mm which corresponds + to the physical width in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-pan-physical-height-dimension: + description: > + Specifies panel physical height in mm which corresponds + to the physical height in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-test-pin: + description: Specifies the panel test gpio. + + qcom,mdss-dsi-mode-sel-gpio-state: + description: > + String that specifies the lcd mode for panel + (such as single-port/dual-port), if qcom,panel-mode-gpio + binding is defined in dsi controller. + "dual_port" = Set GPIO to LOW + "single_port" = Set GPIO to HIGH + "high" = Set GPIO to HIGH + "low" = Set GPIO to LOW + The default value is "dual_port". + $ref: /schemas/types.yaml#/definitions/string-array + default: dual_port + enum: [dual_port, single_port, high, low] + + qcom,mdss-tear-check-disable: + description: > + Boolean to disable mdp tear check. Tear check is enabled by default to avoid + tearing. Other tear-check properties are ignored if this property is present. + The below tear check configuration properties can be individually tuned if + tear check is enabled. + + qcom,mdss-tear-check-sync-cfg-height: + description: > + Specifies the vertical total number of lines. + The default value is 0xfff0. + default: 0xfff0 + + qcom,mdss-tear-check-sync-init-val: + description: > + Specifies the init value at which the read pointer gets loaded + at vsync edge. The reader pointer refers to the line number of + panel buffer that is currently being updated. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-start: + description: > + Allows the first ROI line write to an panel when read pointer is + between the range of ROI start line and ROI start line plus this + setting. + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-continue: + description: > + The minimum number of lines the write pointer needs to be + above the read pointer so that it is safe to write to the panel. + (This check is not done for the first ROI line write of an update) + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-start-pos: + description: > + Specify the y position from which the start_threshold value is + added and write is kicked off if the read pointer falls within that + region. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-rd-ptr-trigger-intr: + description: > + Specify the read pointer value at which an interrupt has to be + generated. + The default value is panel height + 1. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-frame-rate: + description: > + Specify the value to be a real frame rate(fps) x 100 factor to tune the + timing of TE simulation with more precision. + The default value is 6000 with 60 fps. + $ref: /schemas/types.yaml#/definitions/uint32 + + qqcom,mdss-dsi-reset-sequence: + description: > + An array that lists the + sequence of reset gpio values and sleeps + Each command will have the format defined + as below: + --> Reset GPIO value + --> Sleep value (in ms) + + qcom,partial-update-enabled: + description: > + String used to enable partial + panel update for command mode panels. + "none": partial update is disabled + "single_roi": default enable mode, only single roi is sent to panel + "dual_roi": two rois are merged into one big roi. Panel ddic should be able + to process two roi's along with the DCS command to send two rois. + disabled if property is not specified. This property is specified + per timing node to support resolution restrictions. + $ref: /schemas/types.yaml#/definitions/string-array + default: single_roi + enum: [none, single_roi, dual_roi] + + qcom,mdss-dsi-horizontal-line-idle: + description: > + List of width ranges (EC - SC) in pixels indicating + additional idle time in dsi clock cycles that is needed + to compensate for smaller line width. + + qcom,partial-update-roi-merge: + description: > + Boolean indicates roi combination is need + and function has been provided for dcs + 2A/2B command. This property is specified per timing node to support + resolution restrictions. + + qcom,dcs-cmd-by-left: + description: > + Boolean to indicate that dcs command are sent + through the left DSI controller only in a dual-dsi configuration + + qcom,mdss-dsi-panel-hdr-enabled: + description: > + Boolean to indicate HDR support in panel. + + qcom,mdss-dsi-panel-hdr-color-primaries: + description: > + Array of 8 unsigned integers denoting chromaticity of panel.These + values are specified in nits units. The value range is 0 through 50000. + To obtain real chromacity, these values should be divided by factor of + 50000. The structure of array is defined in below order + value 1: x value of white chromaticity of display panel + value 2: y value of white chromaticity of display panel + value 3: x value of red chromaticity of display panel + value 4: y value of red chromaticity of display panel + value 5: x value of green chromaticity of display panel + value 6: y value of green chromaticity of display panel + value 7: x value of blue chromaticity of display panel + value 8: y value of blue chromaticity of display panel + $ref: /schemas/types.yaml#/definitions/uint32-array + minimum: 0 + maximum: 50000 + items: + - description: x value of white chromaticity of display panel + - description: y value of white chromaticity of display panel + - description: x value of red chromaticity of display panel + - description: y value of red chromaticity of display panel + - description: x value of green chromaticity of display panel + - description: y value of green chromaticity of display panel + - description: x value of blue chromaticity of display panel + - description: y value of blue chromaticity of display panel + + qcom,mdss-dsi-panel-peak-brightness: + description: > + Maximum brightness supported by panel.In absence of maximum value + typical value becomes peak brightness. Value is specified in nits units. + To obtain real peak brightness, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-panel-blackness-level: + description: > + Blackness level supported by panel. Blackness level is defined as + ratio of peak brightness to contrast. Value is specified in nits units. + To obtain real blackness level, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-lp11-init: + description: > + Boolean used to enable the DSI clocks and data lanes (low power 11) + before issuing hardware reset line. + + qcom,mdss-dsi-init-delay-us: + description: > + Delay in microseconds(us) before performing any DSI activity in lp11 + mode. This master delay (t_init_delay as per DSI spec) should be sum + of DSI internal delay to reach fuctional after power up and minimum + delay required by panel to reach functional. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-rx-eot-ignore: + description: Boolean used to enable ignoring end of transmission packets. + + qcom,mdss-dsi-tx-eot-append: + description: Boolean used to enable appending end of transmission packets. + + qcom,ulps-enabled: + description: Boolean to enable support for Ultra Low Power State (ULPS) mode. + + qcom,suspend-ulps-enabled: + description: Boolean to enable support for ULPS mode for panels during suspend state. + + qcom,spr-pack-type: + description: > + String to specify the SPR pack type of panel pixel layout + Expected string for the pack types supported by MDSS are, + "pentile", "rgbw", "yygm", "yygw" + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-roi-alignment: + description: | + Specifies the panel ROI alignment restrictions on its + left, top, width, height alignments and minimum width and + height values. This property is specified per timing node to support + resolution's alignment restrictions. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,esd-check-enabled: + description: Boolean used to enable ESD recovery feature. + + qcom,mdss-dsi-panel-status-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol, to read the panel status. + This value is used to kick in the ESD recovery. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + + qcom,mdss-dsi-panel-status-command-mode: + description: > + String that specifies the ctrl state for reading the panel status. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp1-command: + description: > + An optional byte stream to request low + power mode on a panel + + qcom,mdss-dsi-lp1-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp2-command: + description: > + An optional byte stream to request ultra + low power mode on a panel + + qcom,mdss-dsi-lp2-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-nolp-command: + description: An optional byte stream to disable low power and ultra low power panel modes + + qcom,mdss-dsi-nolp-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-panel-status-check-mode: + description: > + Specifies the panel status check method for ESD recovery. + "bta_check" = Uses BTA to check the panel status + "reg_read" = Reads panel status register to check the panel status + "reg_read_nt35596" = Reads panel status register to check the panel + status for NT35596 panel. + "te_signal_check" = Uses TE signal behaviour to check the panel status + enum: [bta_check, reg_read, reg_read_nt35596, te_signal_check] + + qcom,mdss-dsi-panel-status-read-length: + description: > + Integer array that specify the expected read-back length of values + for each of panel registers. Each length is corresponding to number of + returned parameters of register introduced in specification. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-valid-params: + description: > + Integer array that specify the valid returned values which need to check + for each of register. + Some panel need only check the first few values returned from panel. + So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, + then just ignore this one. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-value: + description: > + Multiple integer arrays, each specifies the values of the panel status register + which is used to check the panel status. The size of each array is the sum of + length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. + This can cover that Some panel may return several alternative values. + + qcom,mdss-dsi-panel-max-error-count: + description: > + Integer value that specifies the maximum number of errors from register + read that can be ignored before treating that the panel has gone bad. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dynamic-mode-switch-enabled: + description: > + Boolean used to mention whether panel supports + dynamic switching from video mode to command mode + and vice versa. + + qcom,dynamic-mode-switch-type: + description: > + A string specifies how to perform dynamic mode switch. + If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is + dynamic-switch-suspend-resume. + "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will + go blank during transition. + "dynamic-switch-immediate"= Switch on next frame update. Panel will + not go blank for this transition. + "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will + not go blank for this transition. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-post-mode-switch-on-command: + description: > + Multiple dcs packets used for turning on DSI panel + after panel has switch modes. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,cmd-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,send-pps-before-switch: + description: > + Boolean propety to indicate when PPS commands should be sent, + either before or after switch commands during dynamic resolution + switch in DSC panels. If the property is not present, the default + behavior is to send PPS commands after the switch commands. + + qcom,mdss-dsi-panel-orientation: + description: > + String used to indicate orientation of panel + "180" = panel is flipped in both horizontal and vertical directions + "hflip" = panel is flipped in horizontal direction + "vflip" = panel is flipped in vertical direction + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-ack-disabled: + description: > + A boolean property to indicate, whether we need to wait for any ACK from the panel + for any commands that we send. + + qcom,mdss-dsi-force-clock-lane-hs: + description: Boolean to force dsi clock lanes to HS mode always. + + qcom,panel-cphy-mode: + description: Boolean to specify whether panel is using cphy. + + qcom,compression-mode: + description: > + Select compression mode for panel. + "fbc" - frame buffer compression + "dsc" - display stream compression. + "vdc" - VESA display compression. + If "dsc" or "vdc" compression is used then config subnodes needs to be defined. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-supply-entries: + description: > + A node that lists the elements of the supply used to + power the DSI panel. There can be more than one instance + of this binding, in which case the entry would be appended + with the supply entry index. For a detailed description of + fields in the supply entry, refer to the qcom,ctrl-supply-entries + binding above. + + qcom,mdss-dsc-version: + description: > + An 8 bit value indicates the DSC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only DSC rev 1(Major).1(Minor) + right now. + + qcom,mdss-dsc-scr-version: + description: > + Each DSC version can have multiple SCR. This 8 bit value indicates + current SCR revision information supported by panel. + + qcom,mdss-dsc-encoders: + description: > + An integer value indicating how many DSC encoders should be used + to drive data stream to DSI. + Default value is 1 and max value is 2. + 2 encoder should be used only if qcom,mdss-lm-split or + qcom,split-mode with pingpong-split is used. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + qcom,mdss-dsc-slice-height: + description: An integer value indicates the dsc slice height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-width: + description: > + An integer value indicates the dsc slice width. + Multiple of slice width should be equal to panel-width. + Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders + are used then minimum slice width is equal to panel-width/4. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-per-pkt: + description: An integer value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-component: + description: An integer value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-pixel: + description: An integer value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-block-prediction-enable: + description: A boolean value to enable/disable the block prediction at decoder. + + qcom,mdss-dsc-config-by-manufacture-cmd: + description: > + A boolean to indicates panel use manufacture command to setup pps + instead of standard dcs type 0x0A. + + qcom,vdc-version: + description: > + An 8 bit value indicates the VDC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only VDC rev 1(Major).2(Minor) + right now. + + qqcom,vdc-version-release: + description: An 8 bit value indicated VDC version release. This has to be set to 0. + const: 0 + + qcom,vdc-slice-height: + description: An u32 value which indicates slice height. This should be at least 16 lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-width: + description: > + An u32 value which indicates slice width. This should be at least 64 pixels and + should also be a multiple of 8 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-per-pkt: + description: An u32 value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-component: + description: An u32 value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-pixel: + description: An u32 value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,src-color-space: + description: > + An u32 value indicating the source color space. It can either be RGB or YUV. + Default value is assumed to be RGB + 0 - RGB + 1 - YUV + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0,1] + + qcom,src-chroma-format: + description: > + An u32 value indicating the source color space. It can either be 444, 420 or 422. + Default value is assumed to be 444 + 0 - 444 + 1 - 422 + 2 - 420 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0, 1, 2] + + qcom,mdss-pps-delay-ms: + description: > + An u32 value that indicates post PPS command + delay in milliseconds. If no value is specified, it chooses zero by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,display-topology: + description: > + Array of u32 values which specifies the list of topologies available + for the display. A display topology is defined by a + set of 3 values in the order: + - number of mixers + - number of compression encoders + - number of interfaces + Therefore, the array should always contain a tuple of 3 elements. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + - description: number of mixers + - description: number of compression encoders + - description: number of interfaces + + qcom,default-topology-index: + description: > + An u32 value which indexes the topology set + specified by the node "qcom,display-topology" + to identify the default topology for the + display. The first set is indexed by the + value 0. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-ext-bridge-mode: + description: External bridge chip is connected instead of panel. + + qcom,mdss-dsi-dma-schedule-line: + description: > + An integer value indicates the line number after vertical active + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-dma-schedule-window: + description: > + An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-mdp-idle-ctrl-en: + description: > + A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. + + qcom,mdss-dsi-mdp-idle-ctrl-len: + description: > + An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vert-padding-value: + description: > + An u32 value indicating the second display height while using two displays + in shared display feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dba-panel: + description: > + Indicates whether the current panel is used as a display bridge + to a non-DSI interface. + + qcom,bridge-name: + description: > + A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name + is required if qcom,dba-panel is defined for the panel. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,adjust-timer-wakeup-ms: + description: > + An integer value to indicate the timer delay(in ms) to accommodate + s/w delay while configuring the event timer wakeup logic. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-display-timings: + description: > + Parent node that lists the different resolutions that the panel supports. + Each child represents timings settings for a specific resolution. + + qcom,mdss-dsi-post-init-delay: + description: > + Specifies required number of frames to wait so that panel can be functional + to show proper display. + + qcom,mdss-dsi-video-mode: + description: A boolean to indicates current timing can only work in video mode. + + qcom,mdss-dsi-cmd-mode: + description: A boolean to indicates current timing can only work in command mode. + +# Additional properties added to the second level nodes that represent timings properties: + + qcom,mdss-dsi-timing-default: + description: > + Property that specifies the current child as the default + timing configuration that will be used. + + qcom,mdss-dsi-timing-switch-command: + description: > + List of commands that need to be sent + to panel when the resolution/timing switch happens dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,mdss-dsi-timing-switch-command-state: + description: > + String that specifies the ctrl state for sending resolution switch + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,dsi-dyn-clk-list: + description: > + An u32 array of all the supported dsi bit clock + frequencies in Hz for the given mode, listed in + order of preference. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,disable-rsc-solver: + description: > + Timing node property to dynamically disable RSC solver for + high FPS usecase due to lower bitclk rate. + +required: + - compatible + - status + - qcom,mdss-dsi-panel-controller + - qcom,mdss-dsi-panel-width + - qcom,mdss-dsi-panel-height + - qcom,mdss-dsi-bpp + - qcom,mdss-dsi-panel-destination + - qcom,mdss-dsi-panel-timings + - qcom,mdss-dsi-panel-timings-8996 + - qcom,mdss-dsi-on-command + - qcom,mdss-dsi-off-command + - qcom,mdss-dsi-post-panel-on-command + - qcom,platform-reset-gpio + +if: + properties: + contains: + const: bl_ctrl_pwm +then: + required: + - qcom,mdss-dsi-bl-pmic-bank-select + - qcom,mdss-dsi-bl-pmic-pwm-frequency + - qcom,mdss-dsi-pwm-gpio + +examples: + - | + &mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-pixel-packing = <0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-fbc-enable; + qcom,mdss-dsi-panel-mode-switch; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-bpp-switch; + qcom,mdss-dsi-fbc-slice-height = <5>; + qcom,mdss-dsi-fbc-2d-pred-mode; + qcom,mdss-dsi-fbc-ver2-mode; + qcom,mdss-dsi-fbc-bpp = <0>; + qcom,mdss-dsi-fbc-packing = <0>; + qcom,mdss-dsi-fbc-quant-error; + qcom,mdss-dsi-fbc-bias = <0>; + qcom,mdss-dsi-fbc-pat-mode; + qcom,mdss-dsi-fbc-vlc-mode; + qcom,mdss-dsi-fbc-bflc-mode; + qcom,mdss-dsi-fbc-h-line-budget = <0>; + qcom,mdss-dsi-fbc-budget-ctrl = <0>; + qcom,mdss-dsi-fbc-block-budget = <0>; + qcom,mdss-dsi-fbc-lossless-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-threshold = <0>; + qcom,mdss-dsi-fbc-rgb-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; + qcom,mdss-dsi-fbc-max-pred-err = <2>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <1>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = < 15>; + qcom,mdss-brightness-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-interleave-mode = <0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-last-line-interleave; + qcom,mdss-dsi-traffic-mode = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = <0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-mdp-trigger = <0>; + qcom,mdss-dsi-dma-trigger = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 2e 06 08 05 03 04 a0]; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 FF 99]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; + qcom,dsi-qsync-avr-step-list = <0 360 660>; + qcom,dsi-qsync-avr-step-fps = <360>; + qcom,min-refresh-rate = <30>; + qcom,max-refresh-rate = <60>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; + qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; + qcom,mdss-pan-physical-width-dimension = <60>; + qcom,mdss-pan-physical-height-dimension = <140>; + qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; + qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; + qcom,mdss-tear-check-sync-init-val = <1280>; + qcom,mdss-tear-check-sync-threshold-start = <4>; + qcom,mdss-tear-check-sync-threshold-continue = <4>; + qcom,mdss-tear-check-start-pos = <1280>; + qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; + qcom,mdss-tear-check-frame-rate = <6000>; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-init-delay-us = <100>; + mdss-dsi-rx-eot-ignore; + mdss-dsi-tx-eot-append; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <8>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 B0 03]; + qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B + 15 01 00 00 00 00 02 C2 08]; + qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; + qcom,send-pps-before-switch; + qcom,panel-ack-disabled; + qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, + <40 120 128>, + <128 240 64>; + qcom,mdss-dsi-panel-orientation = "180" + qcom,mdss-dsi-panel-jitter = <0x8 0x10>; + qcom,mdss-dsi-panel-prefill-lines = <0x10>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,compression-mode = "dsc"; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,platform-reset-gpio = <&tlmm 0 0>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,mdss-dsi-display-timings { + wqhd { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-bpp-mode = <24>; + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <728>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <424000000>; + qcom,mdss-mdp-transfer-time-us = <12500>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-mdp-transfer-time-us-min = <10000>; + qcom,mdss-mdp-transfer-time-us-max = <15000>; + qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2a>; + qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 00 00 00 00 00 02 B0 04 + 29 00 00 00 00 00 02 F1 00]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,qsync-mode-min-refresh-rate = <48>; + qcom,dsi-qsync-mode-avr-step-fps = <360>; + qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + + qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + + qcom,vert-padding-value = <2940>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <4 4 2 2 20 20>; + }; + }; + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <0>; + qcom,vdc-version = <0x12>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; + }; + }; +... diff --git a/bindings/msm_hdcp.txt b/bindings/msm_hdcp.txt deleted file mode 100644 index 8d5f55d7..00000000 --- a/bindings/msm_hdcp.txt +++ /dev/null @@ -1,14 +0,0 @@ -MSM HDCP driver - -Standalone driver managing HDCP related communications -between TZ and HLOS for MSM chipset. - -Required properties: - -compatible = "qcom,msm-hdcp"; - -Example: - -qcom_msmhdcp: qcom,msm_hdcp { - compatible = "qcom,msm-hdcp"; -}; diff --git a/bindings/msm_hdcp.yaml b/bindings/msm_hdcp.yaml new file mode 100644 index 00000000..8ce3fccf --- /dev/null +++ b/bindings/msm_hdcp.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm_hdcp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM HDCP driver + +description: | + Standalone driver managing HDCP related communications between TZ and HLOS for MSM chipset. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,msm-hdcp + +required: + - compatible + +examples: + - | + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; +... diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt deleted file mode 100644 index fb48ae98..00000000 --- a/bindings/sde-dp.txt +++ /dev/null @@ -1,297 +0,0 @@ -Qualcomm Technologies, Inc. -sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification. -DP Controller: Required properties: -- compatible: Should be "qcom,dp-display". -- reg: Base address and length of DP hardware's memory mapped regions. -- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. - "dp_ahb" - AHB memory region. - "dp_aux" - AUX memory region. - "dp_link" - LINK memory region. - "dp_p0" - PCLK0 memory region. - "dp_phy" - PHY memory region. - "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. - "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. - "dp_mmss_cc" - Display Clock Control memory region. - "dp_pll" - USB3 DP combo PLL memory region. - "usb3_dp_com" - USB3 DP PHY combo memory region. - "hdcp_physical" - DP HDCP memory region. - "dp_p1" - DP PCLK1 memory region. - "gdsc" - DISPCC GDSC memory region. -- cell-index: Specifies the controller instance. -- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs) -- clocks: Clocks required for Display Port operation. -- clock-names: Names of the clocks corresponding to handles. Following clocks are required: - "core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk", - "link_clk_src", "link_iface_clk", "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk". -- vdda-1p2-supply: phandle to vdda 1.2V regulator node. -- vdda-0p9-supply: phandle to vdda 0.9V regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first - entry in this array corresponds to the register offset - within DP AUX, while the remaining entries indicate the - programmable values. -- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port. -- qcom,mst-enable: MST feature enable control node. -- qcom,dsc-feature-enable: DSC feature enable control node. -- qcom,fec-feature-enable: FEC feature enable control node. -- qcom,qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask -- qcom,qos-cpu-latency-us: A u32 value indicating desired PM QoS CPU latency in usec -- qcom,altmode-dev: Phandle for the AltMode GLink driver. -- usb-controller: Phandle for the USB controller. -- qcom,pll-revision: PLL hardware revision. -- usb-phy: Phandle for USB PHY driver. This is used to register for USB cable events. -- qcom,dsc-continuous-pps: Control node for sending PPS every frame in hardware for DSC over DP. - This is needed by certain bridge chips where there is such a requirement to do so. -- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. -- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. -- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. -- qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types" - can be "core", "ctrl", "pll" and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off - -msm_ext_disp is a device which manages the interaction between external -display interfaces, e.g. Display Port, and the audio subsystem. - -Optional properties: -- clock-mmrm: List of the clocks that enable setting the clk rate through MMRM driver. - The order of the list must match the 'clocks' and 'clock-names' - properties. The 'DISP_CC' ID of the clock must be used to enable - the property for the respective clock, whereas a value of zero - disables the property. -- vdd_mx-supply: phandle to vdda MX regulator node -- qcom,aux-en-gpio: Specifies the aux-channel enable gpio. -- qcom,aux-sel-gpio: Specifies the aux-channel select gpio. -- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio. -- qcom,ext-disp: phandle for msm-ext-display module -- compatible: Must be "qcom,msm-ext-disp" -- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node -- qcom,phy-version: Phy version -- qcom,pn-swap-lane-map: P/N swap configuration of each lane -- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node - Refer to pinctrl-bindings.txt -- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin - controller. These pin configurations are installed in the pinctrl - device node. Refer to pinctrl-bindings.txt -- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port. -- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one -- qcom,hbr-rbr-voltage-swing: Specifies the voltage swing levels for HBR and RBR rates. -- qcom,hbr-rbr-pre-emphasis: Specifies the pre-emphasis levels for HBR and RBR rates. -- qcom,hbr2-3-voltage-swing: Specifies the voltage swing levels for HBR2 and HBR3 rates. -- qcom,hbr2-3-pre-emphasis: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. - -[Optional child nodes]: These nodes are for devices which are -dependent on msm_ext_disp. If msm_ext_disp is disabled then -these devices will be disabled as well. Ex. Audio Codec device. - -- ext_disp_audio_codec: Node for Audio Codec. -- compatible : "qcom,msm-ext-disp-audio-codec-rx"; - -Example: - -ext_disp: qcom,msm-ext-disp { - compatible = "qcom,msm-ext-disp"; - - ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { - compatible = "qcom,msm-ext-disp-audio-codec-rx"; - }; -}; - -sde_dp: qcom,dp_display@0 { - cell-index = <0>; - compatible = "qcom,dp-display"; - - qcom,dp-aux-switch = <&fsa4480>; - qcom,ext-disp = <&ext_disp>; - qcom,altmode-dev = <&altmode 0>; - usb-controller = <&usb0>; - - reg = <0xae90000 0x0dc>, - <0xae90200 0x0c0>, - <0xae90400 0x508>, - <0xae91000 0x094>, - <0x88eaa00 0x200>, - <0x88ea200 0x200>, - <0x88ea600 0x200>, - <0xaf02000 0x1a0>, - <0x88ea000 0x200>, - <0x88e8000 0x20>, - <0x0aee1000 0x034>, - <0xae91400 0x094>, - <0xaf03000 0x8>; - reg-names = "dp_ahb", "dp_aux", "dp_link", - "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", - "dp_mmss_cc", "dp_pll", "usb3_dp_com", - "hdcp_physical", "dp_p1", "gdsc"; - - interrupt-parent = <&mdss_mdp>; - interrupts = <12 0>; - - #clock-cells = <1>; - clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&clock_rpmh RPMH_CXO_CLK>, - <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, - <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, - <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; - clock-names = "core_aux_clk", "core_usb_ref_clk_src", - "core_usb_pipe_clk", "link_clk", "link_clk_src", - "link_iface_clk", "pixel_clk_rcg", "pixel_parent", - "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; - clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; - - qcom,pll-revision = "5nm-v1"; - qcom,phy-version = <0x420>; - qcom,dp-aux-switch = <&fsa4480>; - - qcom,aux-cfg0-settings = [1c 00]; - qcom,aux-cfg1-settings = [20 13 23 1d]; - qcom,aux-cfg2-settings = [24 00]; - qcom,aux-cfg3-settings = [28 00]; - qcom,aux-cfg4-settings = [2c 0a]; - qcom,aux-cfg5-settings = [30 26]; - qcom,aux-cfg6-settings = [34 0a]; - qcom,aux-cfg7-settings = [38 03]; - qcom,aux-cfg8-settings = [3c bb]; - qcom,aux-cfg9-settings = [40 03]; - qcom,max-pclk-frequency-khz = <593470>; - qcom,mst-enable; - qcom,dsc-feature-enable; - qcom,fec-feature-enable; - qcom,dsc-continuous-pps; - qcom,qos-cpu-mask = <0xf>; - qcom,qos-cpu-latency-us = <300>; - vdda-1p2-supply = <&L6B>; - vdda-0p9-supply = <&L1B>; - vdd_mx-supply = <&VDD_MXA_LEVEL>; - - qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, - <0x11 0x1e 0x1f 0xff>, - <0x16 0x1f 0xff 0xff>, - <0x1f 0xff 0xff 0xff>; - qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, - <0x00 0x0e 0x15 0xff>, - <0x00 0x0e 0xff 0xff>, - <0x02 0xff 0xff 0xff>; - - qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, - <0x09 0x19 0x1f 0xff>, - <0x10 0x1f 0xff 0xff>, - <0x1f 0xff 0xff 0xff>; - qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, - <0x02 0x0e 0x16 0xff>, - <0x02 0x11 0xff 0xff>, - <0x04 0xff 0xff 0xff>; - - qcom,ctrl-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,ctrl-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-1p2"; - qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1200000>; - qcom,supply-enable-load = <21700>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,phy-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,phy-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdda-0p9"; - qcom,supply-min-voltage = <912000>; - qcom,supply-max-voltage = <912000>; - qcom,supply-enable-load = <115000>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,core-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,core-supply-entry@0 { - reg = <0>; - qcom,supply-name = "refgen"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; - - qcom,pll-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - - qcom,pll-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd_mx"; - qcom,supply-min-voltage = - ; - qcom,supply-max-voltage = - ; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; - }; -}; diff --git a/bindings/sde-dp.yaml b/bindings/sde-dp.yaml new file mode 100644 index 00000000..b8907930 --- /dev/null +++ b/bindings/sde-dp.yaml @@ -0,0 +1,579 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE DP + +description: | + sde-dp is the master Display Port device which supports DP host controllers that are compatible + with VESA Display Port interface specification. + msm_ext_disp is a device which manages the interaction between external + display interfaces, e.g. Display Port, and the audio subsystem. + [Optional child nodes]: These nodes are for devices which are + dependent on msm_ext_disp. If msm_ext_disp is disabled then + these devices will be disabled as well. Ex. Audio Codec device. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,dp-display + + reg: + description: | + Base address and length of DP hardware's memory mapped regions. + + reg-names: + description: | + A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. + + cell-index: + description: Specifies the controller instance. + + '#clock-cells': + description: Denotes the DP driver as a clock producer (has one or more clock outputs) + + clocks: + description: Clocks required for Display Port operation. + + clock-names: + items: + - const: core_aux_clk + - const: core_usb_ref_clk_src + - const: core_usb_pipe_clk + - const: link_clk + - const: link_clk_src + - const: link_iface_clk + - const: pixel_clk_rcg + - const: pixel_parent + - const: pixel1_clk_rcg + - const: strm0_pixel_clk + - const: strm1_pixel_clk + + vdda-1p2-supply: + description: phandle to vdda 1.2V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-0p9-supply: + description: phandle to vdda 0.9V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,aux-cfg0-settings: + description: | + Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg1-settings: + description: | + Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg2-settings: + description: | + Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg3-settings: + description: | + Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg4-settings: + description: | + Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg5-settings: + description: | + Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg6-settings: + description: | + Specifies the DP AUX configuration 6 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg7-settings: + description: | + Specifies the DP AUX configuration 7 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg8-settings: + description: | + Specifies the DP AUX configuration 8 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg9-settings: + description: | + Specifies the DP AUX configuration 9 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,max-pclk-frequency-khz: + description: An integer specifying the max. pixel clock in KHz supported by Display Port. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mst-enable: + description: MST feature enable control node. + + qcom,dsc-feature-enable: + description: DSC feature enable control node. + + qcom,fec-feature-enable: + description: FEC feature enable control node. + + qcom,qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,qos-cpu-latency-us: + description: A u32 value indicating desired PM QoS CPU latency in usec + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,altmode-dev: + description: Phandle for the AltMode GLink driver. + $ref: /schemas/types.yaml#/definitions/phandle + + usb-controller: + description: Phandle for the USB controller. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,pll-revision: + description: PLL hardware revision. + + usb-phy: + description: Phandle for USB PHY driver. This is used to register for USB cable events. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsc-continuous-pps: + description: | + Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. + + qcom,dp-aux-switch: + description: Phandle for the driver used to program the AUX switch for Display Port orientation. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dp-hpd-gpio: + description: HPD gpio for direct DP connector without USB PHY or AUX switch. + + qcom,dp-gpio-aux-switch: + description: Gpio DP AUX switch chipset support. + + clock-mmrm: + description: | + List of the clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' + properties. The 'DISP_CC' ID of the clock must be used to enable + the property for the respective clock, whereas a value of zero + disables the property. + + vdd_mx-supply: + description: phandle to vdda MX regulator node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,aux-en-gpio: + description: Specifies the aux-channel enable gpio. + + qcom,aux-sel-gpio: + description: Specifies the aux-channel select gpio. + + qcom,usbplug-cc-gpio: + description: Specifies the usbplug orientation gpio. + + qcom,ext-disp: + description: phandle for msm-ext-display module + $ref: /schemas/types.yaml#/definitions/phandle + + compatible: + const: qcom,msm-ext-disp + + qcom,dp-low-power-hw-hpd: + description: Low power hardware HPD feature enable control node + + qcom,phy-version: + description: Phy version + + pinctrl-names: + description: | + List of names to assign mdss pin states defined in pinctrl device node + Refer to pinctrl-bindings.txt + + pinctrl-<0..n>: + description: | + Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl + device node. Refer to pinctrl-bindings.txt + + qcom,max-lclk-frequency-khz: + description: An integer specifying the max. link clock in KHz supported by Display Port. + + qcom,mst-fixed-topology-ports: + description: u32 values of which MST output port to reserve, start from one + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hbr-rbr-voltage-swing: + description: Specifies the voltage swing levels for HBR and RBR rates. + + qcom,hbr-rbr-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR and RBR rates. + + qcom,hbr2-3-voltage-swing: + description: Specifies the voltage swing levels for HBR2 and HBR3 rates. + + qcom,hbr2-3-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. + + compatible: + const: qcom,msm-ext-disp-audio-codec-rx + + ext_disp_audio_codec: + description: Node for Audio Codec. + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - reg-names + - cell-index + - '#clock-cells' + - clocks + - clock-names + - vdda-1p2-supply + - vdda-0p9-supply + - interrupt-parent + - interrupts + - qcom,aux-cfg0-settings + - qcom,aux-cfg1-settings + - qcom,aux-cfg2-settings + - qcom,aux-cfg3-settings + - qcom,aux-cfg4-settings + - qcom,aux-cfg5-settings + - qcom,aux-cfg6-settings + - qcom,aux-cfg7-settings + - qcom,aux-cfg8-settings + - qcom,aux-cfg9-settings + - qcom,max-pclk-frequency-khz + - qcom,mst-enable + - qcom,dsc-feature-enable + - qcom,fec-feature-enable + - qcom,qos-cpu-mask + - qcom,qos-cpu-latency-us + - qcom,altmode-dev + - usb-controller + - qcom,pll-revision + - usb-phy + - qcom,dp-aux-switch + - qcom,dp-hpd-gpio + - qcom,dp-gpio-aux-switch + - qcom,-supply-entries + +examples: + - | + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + - | + sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +... diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt deleted file mode 100644 index db92a23d..00000000 --- a/bindings/sde-dsi.txt +++ /dev/null @@ -1,130 +0,0 @@ -Qualcomm Technologies, Inc. - -mdss-dsi is the master DSI device which supports multiple DSI host controllers -that are compatible with MIPI display serial interface specification. - -DSI Controller and PHY: -Required properties: -- compatible: Should be "qcom,dsi-ctrl-hw-v". Supported - versions include 2.4, 2.5, and 2.6. - eg: qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, - qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5, - qcom,dsi-ctrl-hw-v2.6 - And for dsi phy driver: - qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, - qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 -- reg: List of base address and length of memory mapped - regions of DSI controller, disp_cc and mdp_intf. -- reg-names: A list of strings that name the list of regs. - "dsi_ctrl" - DSI controller memory region. - "disp_cc_base" - Base address of disp_cc memory region. - "mdp_intf_base" - Base address of mdp_intf memory region. -- cell-index: Specifies the controller instance. -- clocks: Clocks required for DSI controller operation. -- clock-names: Names of the clocks corresponding to handles. Following - clocks are required: - "mdp_core_clk" - "iface_clk" - "core_mmss_clk" - "bus_clk" - "byte_clk" - "pixel_clk" - "core_clk" - "byte_clk_rcg" - "pixel_clk_rcg" -- pll-label Supported versions of DSI PLL: - dsi_pll_5nm -- gdsc-supply: phandle to gdsc regulator node. -- vdda-supply: phandle to vdda regulator node. -- vcca-supply: phandle to vcca regulator node. -- interrupt-parent phandle to the interrupt parent device node. -- interrupts: The interrupt signal from the DSI block. -- qcom,dsi-default-panel: Specifies the default panel. -- qcom,mdp: Specifies the mdp node which can find panel node from this. -- qcom,demura-panel-id: Specifies the u64 demura panel ID as an array <2> - If demura is not used this node must be set to <0,0>. - -Bus Scaling Data: -- qcom,msm-bus,name: String property describing MDSS client. -- qcom,msm-bus,num-cases: This is the number of bus scaling use cases - defined in the vectors property. This must be - set to <2> for MDSS DSI driver where use-case 0 - is used to remove BW votes from the system. Use - case 1 is used to generate bandwidth requestes - when sending command packets. -- qcom,msm-bus,num-paths: This represents number of paths in each bus - scaling usecase. This value depends on number of - AXI master ports dedicated to MDSS for - particular chipset. -- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format - of (src, dst, ab, ib) which is defined at - Documentation/devicetree/bindings/arm/msm/msm_bus.txt. - DSI driver should always set average bandwidth - (ab) to 0 and always use instantaneous - bandwidth(ib) values. - -Optional properties: -- label: String to describe controller. -- qcom,platform-te-gpio: Specifies the gpio used for TE. -- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer. -- qcom,dsi-ctrl: handle to dsi controller device -- qcom,dsi-phy: handle to dsi phy device -- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel -- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel -- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel -- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel -- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel -- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel -- qcom,dsi-display-list: Specifies the list of supported displays. -- qcom,dsi-manager: Specifies dsi manager is present -- qcom,dsi-display: Specifies dsi display is present -- qcom,hdmi-display: Specifies hdmi is present -- qcom,dp-display: Specified dp is present -- qcom,-supply-entries: A node that lists the elements of the supply used by the - a particular "type" of DSI module. The module "types" - can be "core", "ctrl", and "phy". Within the same type, - there can be more than one instance of this binding, - in which case the entry would be appended with the - supply entry index. - e.g. qcom,ctrl-supply-entry@0 - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode - panels in microseconds. Driver uses this number to adjust - the clock rate according to the expected transfer time. - Increasing this value would slow down the mdp processing - and can result in slower performance. - Decreasing this value can speed up the mdp processing, - but this can also impact power consumption. - As a rule this time should not be higher than the time - that would be expected with the processing at the - dsi link rate since anyways this would be the maximum - transfer time that could be achieved. - If ping pong split enabled, this time should not be higher - than two times the dsi link rate time. - If the property is not specified, then the default value is 14000 us. -- qcom,dsi-phy-pll-bypass: A boolean property that enables bypassing hardware access in DSI - PHY/PLL drivers to allow the DSI driver to run on emulation platforms - that might be missing those modules. -- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller. -- ports: This video port is used when external bridge is present. - The connection is modeled using the OF graph bindings - specified in Documentation/devicetree/bindings/graph.txt. - Video port 0 reg 0 is for the bridge output. The remote - endpoint phandle should be mipi_dsi_device device node. -- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. -- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" - or "center-spread". Default is "down-spread" if it is not specified. -- qcom,ssc-frequency-hz: Integer property to specify the spread frequency - to be programmed for the SSC. -- qcom,ssc-ppm: Integer property to specify the Parts per Million - value of SSC. -- qcom,avdd-regulator-gpio: Specifies the gpio pin used for avdd - power supply regulator. diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml new file mode 100644 index 00000000..6e85620c --- /dev/null +++ b/bindings/sde-dsi.yaml @@ -0,0 +1,360 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MDSS DSI + +description: | + mdss-dsi is the master DSI device which supports multiple DSI host controllers + that are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +properties: + compatible: + enum: + - qcom,dsi-ctrl-hw-v2.4 + - qcom,dsi-ctrl-hw-v2.5 + - qcom,dsi-ctrl-hw-v2.6 + - qcom,dsi-ctrl-hw-v2.7 + - qcom,dsi-ctrl-hw-v2.8 + - qcom,dsi-ctrl-hw-v2.9 + - qcom,dsi-phy-v3.0 + - qcom,dsi-phy-v4.0 + - qcom,dsi-phy-v4.1 + - qcom,dsi-phy-v4.2 + - qcom,dsi-phy-v4.3 + - qcom,dsi-phy-v4.3.2 + - qcom,dsi-phy-v5.2 + - qcom,dsi-phy-v7.2 + + reg: + description: | + List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. + + reg-names: + items: + - const: dsi_ctrl + - const: disp_cc_base + - const: mdp_intf_base + + cell-index: + description: Specifies the controller instance. + + clocks: + items: + - const: mdp_core_clk + - const: iface_clk + - const: core_mmss_clk + - const: bus_clk + - const: byte_clk + - const: pixel_clk + - const: core_clk + - const: byte_clk_rcg + - const: pixel_clk_rcg + + pll-label: + description: Supported versions of DSI PLL. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_pll_5nm, dsi_pll_4nm, dsi_pll_3nm] + + gdsc-supply: + description: phandle to gdsc regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: phandle to vcca regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,dsi-default-panel: + description: Specifies the default panel. + + qcom,mdp: + description: Specifies the mdp node which can find panel node from this. + + qcom,demura-panel-id: + description: | + Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,msm-bus,name: + description: String property describing MDSS client. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,msm-bus,num-cases: + description: | + This is the number of bus scaling use cases + defined in the vectors property. This must be + set to <2> for MDSS DSI driver where use-case 0 + is used to remove BW votes from the system. Use + case 1 is used to generate bandwidth requestes + when sending command packets. + + qcom,msm-bus,num-paths: + description: | + This represents number of paths in each bus + scaling usecase. This value depends on number of + AXI master ports dedicated to MDSS for + particular chipset. + + qcom,msm-bus,vectors-KBps: + description: | + A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt. + DSI driver should always set average bandwidth + (ab) to 0 and always use instantaneous + bandwidth(ib) values. + + label: + description: String to describe controller. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,platform-te-gpio: + description: Specifies the gpio used for TE. + + qcom,panel-te-source: + description: Specifies the source pin for Vsync from panel or WD Timer. + + qcom,dsi-ctrl: + description: handle to dsi controller device + + qcom,dsi-phy: + description: handle to dsi phy device + + qcom,dsi-ctrl-num: + description: Specifies the DSI controllers to use for primary panel + + qcom,dsi-sec-ctrl-num: + description: Specifies the DSI controllers to use for secondary panel + + qcom,dsi-phy-num: + description: Specifies the DSI PHYs to use for primary panel + + qcom,dsi-sec-phy-num: + description: Specifies the DSI PHYs to use for secondary panel + + qcom,dsi-select-clocks: + description: Specifies the required clocks to use for primary panel + + qcom,dsi-select-sec-clocks: + description: Specifies the required clocks to use for secondary panel + + qcom,dsi-display-list: + description: Specifies the list of supported displays. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-manager: + description: Specifies dsi manager is present + + qcom,dsi-display: + description: Specifies dsi display is present + + qcom,hdmi-display: + description: Specifies hdmi is present + + qcom,dp-display: + description: Specified dp is present + + qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + + qcom,dsi-phy-pll-bypass: + description: | + A boolean property that enables bypassing hardware access in DSI + PHY/PLL drivers to allow the DSI driver to run on emulation platforms + that might be missing those modules. + + qcom,null-insertion-enabled: + description: A boolean to enable NULL packet insertion feature for DSI controller. + + ports: + description: | + This video port is used when external bridge is present. + The connection is modeled using the OF graph bindings + specified in Documentation/devicetree/bindings/graph.txt. + Video port 0 reg 0 is for the bridge output. The remote + endpoint phandle should be mipi_dsi_device device node. + + qcom,dsi-pll-ssc-en: + description: Boolean property to indicate that ssc is enabled. + + qcom,dsi-pll-ssc-mode: + description: | + Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. + $ref: /schemas/types.yaml#/definitions/string-array + default: down-spread + enum: [down-spread, center-spread] + + qcom,ssc-frequency-hz: + description: | + Integer property to specify the spread frequency + to be programmed for the SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,ssc-ppm: + description: Integer property to specify the Parts per Million value of SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,avdd-regulator-gpio: + description: Specifies the gpio pin used for avdd power supply regulator. + +required: + - compatible + - reg + - reg-names + - cell-index + - clocks + - clock-names + - pll-label + - gdsc-supply + - vdda-supply + - vcca-supply + - interrupt-parent + - qcom,dsi-default-panel + - qcom,mdp + - qcom,demura-panel-id + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + +... diff --git a/bindings/sde-wb.txt b/bindings/sde-wb.txt deleted file mode 100644 index 90093e41..00000000 --- a/bindings/sde-wb.txt +++ /dev/null @@ -1,23 +0,0 @@ -Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display - -Required properties: -- compatible: "qcom,wb-display" - -Optional properties: -- cell-index: Index of writeback device instance. - Default to 0 if not specified. -- label: String to describe this writeback display. - Default to "unknown" if not specified. - -Example: - -/ { - ... - - sde_wb: qcom,wb-display { - compatible = "qcom,wb-display"; - cell-index = <2>; - label = "wb_display"; - }; - -}; diff --git a/bindings/sde-wb.yaml b/bindings/sde-wb.yaml new file mode 100644 index 00000000..b87ecaf9 --- /dev/null +++ b/bindings/sde-wb.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-wb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + +properties: + compatible: + const: qcom,wb-display + + cell-index: + description: Index of writeback device instance. Default to 0 if not specified. + default: 0 + + label: + description: String to describe this writeback display. Default to "unknown" if not specified. + default: "unknown" + +required: + - compatible + +examples: + - | + sde_wb: qcom,wb-display { + compatible = "qcom,wb-display"; + cell-index = <2>; + label = "wb_display"; + }; +... diff --git a/bindings/sde.txt b/bindings/sde.txt deleted file mode 100644 index 485ca56d..00000000 --- a/bindings/sde.txt +++ /dev/null @@ -1,1147 +0,0 @@ -Qualcomm Technologies, Inc. SDE KMS - -Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user -interface to different panel interfaces. SDE driver is the core of -display subsystem which manage all data paths to different panel interfaces. - -Required properties -- compatible: Must be "qcom,sde-kms" -- compatible: "msm-hdmi-audio-codec-rx"; -- reg: Offset and length of the register set for the device. -- reg-names : Names to refer to register sets related to this device -- clocks: List of Phandles for clock device nodes - needed by the device. -- clock-names: List of clock names needed by the device. -- mmagic-supply: Phandle for mmagic mdss supply regulator device node. -- vdd-supply: Phandle for vdd regulator device node. -- interrupt-parent: Must be core interrupt controller. -- interrupts: Interrupt associated with MDSS. -- interrupt-controller: Mark the device node as an interrupt controller. -- #interrupt-cells: Should be one. The first cell is interrupt number. -- iommus: Specifies the SID's used by this context bank. -- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information. - A source pipe can be "vig", "rgb", "dma" or "cursor" type. - Number of xin ids defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets - are calculated from register "mdp_phys" defined in - reg property + "sde-off". The number of offsets defined here should - reflect the amount of pipes that can be active in SDE for - this configuration. -- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective source pipes. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-sspp-off. -- qcom,sde-ctl-off: Array of offset addresses for the available ctl - hw blocks within SDE, these offsets are - calculated from register "mdp_phys" defined in - reg property. The number of ctl offsets defined - here should reflect the number of control paths - that can be configured concurrently on SDE for - this configuration. -- qcom,sde-wb-off: Array of offset addresses for the programmable - writeback blocks within SDE. -- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding - to the respective writeback. Number of xin ids - defined should match the number of offsets - defined in property: qcom,sde-wb-off. -- qcom,sde-mixer-off: Array of offset addresses for the available - mixer blocks that can drive data to panel - interfaces. These offsets are be calculated from - register "mdp_phys" defined in reg property. - The number of offsets defined should reflect the - amount of mixers that can drive data to a panel - interface. -- qcom,sde-dspp-top-off: Offset address for the dspp top block. - The offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,sde-dspp-off: Array of offset addresses for the available dspp - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-pp-off: Array of offset addresses for the available - pingpong blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-pp-slave: Array of flags indicating whether each ping pong - block may be configured as a pp slave. -- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block - connected to each pingpong, starting at 0. -- qcom,sde-merge-3d-off: Array of offset addresses for the available - merge 3d blocks. These offsets are calculated - from register "mdp_phys" defined in reg property. -- qcom,sde-intf-off: Array of offset addresses for the available SDE - interface blocks that can drive data to a - panel controller. The offsets are calculated - from "mdp_phys" defined in reg property. The number - of offsets defined should reflect the number of - programmable interface blocks available in hardware. -- qcom,sde-mixer-blend-op-off Array of offset addresses for the available - blending stages. The offsets are relative to - qcom,sde-mixer-off. -- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with - mixer number corresponding to the array index. - -Optional properties: -- clock-rate: List of clock rates in Hz. -- clock-max-rate: List of maximum clock rate in Hz that this device supports. -- clock-mmrm: List of clocks that enable setting the clk rate through MMRM driver. - The order of the list must match the 'clocks' and 'clock-names' properties. - The 'DISP_CC' ID of the clock must be used to enable the property for the - respective clock, whereas a value of zero disables the property. -- qcom,platform-supply-entries: A node that lists the elements of the supply. There - can be more than one instance of this binding, - in which case the entry would be appended with - the supply entry index. - e.g. qcom,platform-supply-entry@0 - -- reg: offset and length of the register set for the device. - -- qcom,supply-name: name of the supply (vdd/vdda/vddio) - -- qcom,supply-min-voltage: minimum voltage level (uV) - -- qcom,supply-max-voltage: maximum voltage level (uV) - -- qcom,supply-enable-load: load drawn (uA) from enabled supply - -- qcom,supply-disable-load: load drawn (uA) from disabled supply - -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on - -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on - -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off - -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off -- qcom,sde-hw-version: A u32 value indicates the MDSS hw version -- qcom,hw-fence-sw-version: A u32 value to indicate the hw fencing version. If set to a value - greather than zero, driver will attempt to enable the feature (if - supported by the HW). Otherwise, if this value is not set or set - to zero, feature will remain disabled. -- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp. -- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer. -- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl. -- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp. -- qcom,sde-intf-size: A u32 value indicates the address range for each intf. -- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc. -- qcom,sde-vdc-size: A u32 value indicates the address range for each vdc. -- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm. -- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong. -- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d. -- qcom,sde-pp-cwb: Array of u32 flags indicating whether each ping pong - block may be configured as a cwb pp block. -- qcom,sde-wb-size: A u32 value indicates the address range for each writeback. -- qcom,sde-len: A u32 entry for SDE address range. -- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on - each interface. -- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width. -- qcom,sde-vig-sspp-linewidth: A u32 value indicates the max vig sspp line width. -- qcom,sde-scaling-linewidth: A u32 value indicates the max vig source pipe line width - for scaling purposes. -- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width. -- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width. -- qcom,sde-wb-linewidth-linear: A u32 value indicates the max line width - supported by WB for linear color formats. -- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp. -- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for - alpha blending. -- qcom,sde-qseed-sw-lib-rev: A string entry indicates qseed sw library revision - supporting the qseed HW block. It supports - "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed - revision. By default "qseedv2" is used if this - optional property is not defined. -- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the - QSEED hardware block -- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb. - It supports "csc" and "csc-10bit" entries for csc - type. -- qcom,sde-highest-bank-bit: Property to specify GPU/Camera/Video highest memory - bank bit used for tile format buffers. First value - in the array represents the ddr type and the second - value is the hbb value corresponding to the ddr type. -- qcom,sde-ubwc-version: Property to specify the UBWC feature version. A u32 UBWC version is based on MDSS support. -- qcom,sde-ubwc-static: Property to specify the default UBWC static - configuration value. -- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth - calculation algorithm -- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle - configuration value. -- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for - split display on smart panel. Possible values: - 0x0 - no alignment - 0xc - align at start of frame - 0xd - align at start of line -- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal - control feature is available on each source pipe. -- qcom,sde-has-src-split: Boolean property to indicate if source split - feature is available or not. -- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer - feature is available or not. -- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle - power collapse feature available or not. -- qcom,sde-wakeup-with-touch: Boolean property to indicate if command mode display - will exit from power collapse based on display input - touch event or not. -- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction - feature available or not. -- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler - feature is available or not. -- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the - maximum input line width to destination scaler. -- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the - maximum output line width of destination scaler. -- qcom,sde-dest-scaler-top-off: A u32 value provides the - offset from mdp base to destination scaler block. -- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top -- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks - offset from destination scaler top offset. -- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block -- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off -- qcom,sde-sspp-clk-status: Array of offsets describing clk status - offsets for clock active state. 1st value - in the array represents offset of the status - register. 2nd value represents bit offset within - status register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-sspp-off. -- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle - support on each sspp. -- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe - priority of secondary rectangles when smart dma - is supported. Number of priority values should - match the number of offsets defined in - qcom,sde-sspp-off node. Zero indicates no support - for smart dma for the sspp. -- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version - supported on the device. Supported entries are - "smart_dma_v1" and "smart_dma_v2". -- qcom,sde-vdc-hw-rev: A string indicating the hw version of vdc. -- qcom,sde-intf-type: Array of string provides the interface type information. - Possible string values - "dsi" - dsi display interface - "dp" - Display Port interface - "hdmi" - HDMI display interface - An interface is considered as "none" if interface type - is not defined. -- qcom,sde-intf-tear-irq-off Array of offset addresses for the available - tear effect (TE) IRQ blocks from "mdp_phys". - There should be one entry per INTF instance with - a zero value for INTFs without TE IRQ block. -- qcom,sde-emulated-env: Boolean property to indicate if the MDSS is running in an - emulated environment. -- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property. -- qcom,sde-cdm-off: Array of offset addresses for the available - cdm blocks. These offsets will be calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-vbif-off: Array of offset addresses for the available - vbif blocks. These offsets will be calculated from - register "vbif_phys" defined in reg property. -- qcom,sde-vbif-size: A u32 value indicates the vbif block address range. -- qcom,sde-uidle-off: A u32 value with the offset for the uidle - block, from the "mdp_phys". -- qcom,sde-uidle-size: A u32 value indicates the uidle block address range. -- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong. - This offset is 0x0 by default. -- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong. -- qcom,sde-te-size: A u32 value indicates the te block address range. -- qcom,sde-te2-size: A u32 value indicates the te2 block address range. -- qcom,sde-dsc-off: Array of offset addresses for the available dsc - blocks. These offsets are calculated from - register "mdp_phys" defined in reg property. -- qcom,sde-dsc-hw-rev: A string value indicates the dsc hw block - version. -- qcom,sde-dsc-enc: Array of offset addresses for the available dsc - encoder blocks. These offsets are calculated from - the corresponding DSC base. -- qcom,sde-dsc-enc-size A u32 value indicates the enc block offset range. -- qcom,sde-dsc-ctl: Array of offset addresses for the available dsc - ctl blocks. These offsets are calculated from - the corresponding DSC base. -- qcom,sde-dsc-ctl-size A u32 value indicates the ctl block offset range. -- qcom,sde-dsc-native422-supp: Array of flags indicating whether corresponding dsc - block can support native 422 and native 420 - encoding. -- qcom,sde-dsc-linewidth: A u32 value indicates the max dsc line width. -- qcom,sde-vdc-off: A u32 offset address for the available vdc blocks. - This offset is calculated from register "mdp_phys" - defined in reg property. -- qcom,sde-vdc-enc-size A u32 value indicates the enc block offset range. -- qcom,sde-vdc-enc: A u32 offset address for the vdc encoder block. This offset is - calculated from qcom,sde-vdc-off. -- qcom,sde-vdc-ctl: A u32 offset address for the vdc ctl block. This offset is - calculated from qcom,sde-vdc-off. -- qcom,sde-vdc-ctl-size A u32 value indicates the ctl block offset range. -- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset. -- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong. -- qcom,sde-dither-version: A u32 value indicates the dither block version. -- qcom,sde-dither-size: A u32 value indicates the dither block address range. -- qcom,sde-cwb-dither: Array of u32 flags indicating whether each dither block - may be configured as a cwb dither block. -- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. There can - be more than one instance of this binding, in which case the - entry would be appended with the vcm entry index. Each entry will - contain the offset and version (if needed) of each feature block. - The presence of a block entry indicates that the SSPP VIG contains - that feature hardware. - e.g. qcom,sde-sspp-vig-blocks - -- vcm@0 - -- cell-index: A u32 index for the sub-block. - -- qcom,sde-vig-top-off: A u32 offset of the sub-block top. - -- qcom,sde-vig-csc-off: offset of CSC hardware - -- qcom,sde-vig-qseed-off: offset of QSEED hardware - -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler. - -- qcom,sde-vig-pcc: offset and version of PCC hardware - -- qcom,sde-vig-hsic: offset and version of global PA adjustment - -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware - -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware - -- qcom,sde-vig-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on VIG pipe - -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware - -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware - -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware - -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware - -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC - IGC hardware - -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC - Unmult hardware - -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC - GC hardware - -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC - CSC hardware - -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC - Alpha Dither hardware -- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There - can be more than one instance of this binding, in which case the - entry would be appended with dgm entry index. Each entry will - contain the offset and version (if needed) of each feature block. - The presence of a block entry indicates that the SSPP DMA contains - that feature hardware. - e.g. qcom,sde-sspp-dma-blocks - -- dgm@0 - -- cell-index: A u32 index for the sub-block. - -- qcom,sde-dma-top-off: A u32 offset of the sub-block top. - -- qcom,sde-dma-igc: offset and version of DMA IGC - -- qcom,sde-dma-gc: offset and version of DMA GC - -- qcom,sde-dma-inverse-pma: Boolean property to indicate if - inverse PMA feature is available on DMA pipe - -- qcom,sde-dma-csc-off: offset of CSC hardware - -- qcom,sde-fp16-igc: u32 offset and version of the FP16 IGC hardware - -- qcom,sde-fp16-unmult: u32 offset and version of the FP16 Unmult hardware - -- qcom,sde-fp16-gc: u32 offset and version of the FP16 GC hardware - -- qcom,sde-fp16-csc: u32 offset and version of the FP16 CSC hardware - -- qcom,sde-ucsc-igc: u32 offset and version of the UCSC - IGC hardware - -- qcom,sde-ucsc-unmult: u32 offset and version of the UCSC - Unmult hardware - -- qcom,sde-ucsc-gc: u32 offset and version of the UCSC - GC hardware - -- qcom,sde-ucsc-csc: u32 offset and version of the UCSC - CSC hardware - -- qcom,sde-ucsc-alpha-dither: u32 offset and version of the UCSC - Alpha Dither hardware -- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the SSPP RGB contains that feature hardware. - e.g. qcom,sde-sspp-rgb-blocks - -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware - -- qcom,sde-rgb-scaler-size: A u32 address range for scaler. - -- qcom,sde-rgb-pcc: offset and version of PCC hardware -- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The - block entries will contain the offset and version of each - feature block. The presence of a block entry indicates that - the DSPP contains that feature hardware. - e.g. qcom,sde-dspp-blocks - -- qcom,sde-dspp-pcc: offset and version of PCC hardware - -- qcom,sde-dspp-gc: offset and version of GC hardware - -- qcom,sde-dspp-igc: offset and version of IGC hardware - -- qcom,sde-dspp-hsic: offset and version of global PA adjustment - -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware - -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware - -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware - -- qcom,sde-dspp-dither: offset and version of dither hardware - -- qcom,sde-dspp-hist: offset and version of histogram hardware - -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware -- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The - block entries will contain the offset and version (if needed) - of each feature block. The presence of a block entry - indicates that the layer mixer contains that feature hardware. - e.g. qcom,sde-mixer-blocks - -- qcom,sde-mixer-gc: offset and version of mixer GC hardware -- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the - DSPP offset. Since AD hardware is represented as part of - DSPP block, the AD offsets must be offset from the - corresponding DSPP base. -- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware -- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) - version of the LTM hardware -- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the - DSPP offsets. Since LTM hardware is represented as part of - DSPP block, the LTM offsets are calculated based on the - corresponding DSPP base. -- qcom,sde-dspp-rc-version: A u32 value indicating the version of the RC hardware. -- qcom,sde-dspp-rc-off: Array of u32 offsets indicate the RC block offsets from the - DSPP offsets. Since RC hardware is represented as part of - DSPP block, the RC offsets are calculated based on the - corresponding DSPP base. -- qcom,sde-dspp-rc-size: A u32 value indicating the RC block address range. -- qcom,sde-dspp-rc-mem-size: A u32 value indicating the RC block shared memory size. -- qcom,sde-dspp-rc-min-region-width: A u32 value indicating the RC block minimum region width. -- qcom,sde-dspp-spr-off: Array of u32 offsets indicate the SPR block offsets from the - corresponding DSPP block offset as base. -- qcom,sde-dspp-spr-size: A u32 value indicating the SPR block register address range -- qcom,sde-dspp-spr-version: A u32 value indicating the version of SPR hardware. -- qcom,sde-dspp-demura-off: Array of u32 offsets indicate the demura block offsets from the - corresponding DSPP block offset as base. -- qcom,sde-dspp-demura-size: A u32 value indicating the demura block register address range -- qcom,sde-dspp-demura-version: A u32 value indicating the version of demura hardware. -- qcom,sde-dspp-aiqe-off: Array of u32 values indicating the offset of each AIQE block - relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-version: A u32 value indicating the version of the AIQE hardware. -- qcom,sde-dspp-aiqe-size: A u32 value indicating the shared memory size of each AIQE - hardware block instance. -- qcom,sde-dspp-aiqe-dither-off: Array of u32 values indicating the offset of each AIQE - dither block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-dither-version: A u32 value indicating the version of the AIQE dither - hardware. -- qcom,sde-dspp-aiqe-dither-size: A u32 value indicating the shared memory size of each AIQE - dither hardware block instance. -- qcom,sde-dspp-aiqe-wrapper-off: Array of u32 values indicating the offset of each AIQE - wrapper block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-wrapper-version: A u32 value indicating the version of the AIQE wrapper - hardware. -- qcom,sde-dspp-aiqe-wrapper-size: A u32 value indicating the shared memory size of each AIQE - wrapper hardware block instance. -- qcom,sde-dspp-aiqe-aiscaler-off: Array of u32 values indicating the offset of each AIQE - AI Scaler block relative to its parent DSPP block. -- qcom,sde-dspp-aiqe-aiscaler-version: A u32 value indicating the version of the AIQE AI Scaler - hardware. -- qcom,sde-dspp-aiqe-aiscaler-size: A u32 value indicating the shared memory size of each AIQE - AI Scaler hardware block instance. -- qcom,sde-aiqe-has-feature-mdnie: Boolean property indicating the presence of AIQE feature mDNIe - hardware. -- qcom,sde-aiqe-has-feature-abc: Boolean property indicating the presence of AIQE feature ABC - hardware. -- qcom,sde-aiqe-has-feature-ssrc: Boolean property indicating the presence of AIQE feature SSRC - hardware. -- qcom,sde-aiqe-has-feature-copr: Boolean property indicating the presence of AIQE feature COPR - hardware. -- qcom,sde-aiqe-has-feature-aiscaler: Boolean property indicating the presence of AIQE feature - AI Scaler hardware. -- nvmem-cells: phandle list to the fuse configuration data provided by a nvmem device. -- nvmem-cell-names: nvmem cell name. -- qcom,sde-lm-noise-off: A u32 value indicating noise layer offset from mixer base. -- qcom,sde-lm-noise-version: A u32 value indicating the noise layer version. -- qcom,sde-vbif-id: Array of vbif ids corresponding to the - offsets defined in property: qcom,sde-vbif-off. -- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit -- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit -- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the read limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format - of (pps, OT limit), where pps is pixel per second and - OT limit is the write limit to apply if the given - pps is not exceeded. -- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0 -- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1 -- qcom,sde-wb-id: Array of writeback ids corresponding to the - offsets defined in property: qcom,sde-wb-off. -- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-wb-off -- qcom,sde-wb-clk-status: Array of 2 cell property describing clk status - offsets for clock active state. 1st value - in the array represents offset of the status - register. 2nd value represents bit offset within - status register. Number of offsets defined should - match the number of offsets defined in - property: qcom,sde-wb-off -- qcom,sde-reg-dma-off: Array of u32 offset addresses of the dma hardware blocks, - relative to "regdma_phys" defined in reg property. -- qcom,sde-reg-dma-id: Array of u32 DMA block type ids corresponding to the - offsets declared in property: qcom,sde-reg-dma-off -- qcom,sde-reg-dma-version: Version of the reg dma hardware blocks. -- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys" - defined in reg property. -- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast - functionality in the register dma hardware block should be used. -- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding - to the LUTDMA block. -- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. -- qcom,sde-dram-channels: This represents the number of channels in the - Bus memory controller. -- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime - paths in each Bus Scaling Usecase. This value depends on - number of AXI ports that are dedicated to non-realtime VBIF - for particular chipset. - These paths must be defined after rt-paths in - "qcom,msm-bus,vectors-KBps" vector request. -- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow. - This is a low bandwidth threshold which should - be applied in most scenarios to be safe from - underflows when unable to satisfy bandwidth - requirements. -- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps - that can be supported without underflow in the - event where there is no VFE. - This is a high bandwidth threshold which can be - applied in scenarios where panel interface can - be more tolerant to memory latency such as - command mode panels. -- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for - core ib calculation. -- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for - core clock calculation. -- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib - vote in Kbps that can be reduced without hitting underflow. - BW calculation logic will choose the IB bandwidth requirement - based on usecase if this floor value is not defined. -- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio - for each supported compressed format on realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio - for each supported compressed format on non-realtime interface. - The string is composed of one or more of - /// - separated with spaces. -- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines. -- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines. -- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines. -- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines. -- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines. -- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines. -- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines. -- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps. -- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines. -- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register - priority for realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register - priority for non-realtime clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register - priority for concurrent writeback clients. First 8 entries are - for rp_remap and the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register - priority for lutdma client. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register - priority for cnoc clients. First 8 entries are for rp_remap and - the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register - priority for offline-wb clients. First 8 entries are for rp_remap - and the next 8 entries are for lvl_remap. -- qcom,sde-vbif-qos-wb-rot-remap: This u32 array is used to program vbif qos remapper register - priority for wb-rotation clients. First 8 entries are for rp_remap - and the next 8 entries are for lvl_remap. -- qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts - qos configuration for different refresh rates. -- qcom,sde-danger-lut: This u32 array of 18 cell property, with a format of - for each entry, - , indicating the danger luts on sspp and wb. -- qcom,sde-safe-lut: This u32 array of 18 cell property, with a format of - for each entry, - , indicating the safe luts on sspp and wb. -- qcom,sde-creq-lut: This u64 array of 18 cell property, with a format of - for each - entry, for qos cases from , with of-node count based - on the qos refresh rates count. -- qcom,sde-cdp-setting: Array of 2 cell property, with a format of - for cdp use cases in - order of , and . -- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask. -- qcom,sde-qos-cpu-mask-performance: Each bit represents a CPU mask. For example - 0xf represents 4 cpu cores. These cores can be - silver or gold or gold+. -- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. -- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. -- qcom,sde-soccp-controller: The phandle for the soccp controller. - This value is optional and only required for targets with SOCCP. -- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature. -- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used - for ipcc registers access. -- qcom,sde-hw-fence-mdp-ctl-offset: An optional u32 value indicating the hw fence mdp reg - offset. -- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline - rotation. -- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, - namely sspp or wb. Number of entries should match - the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control - offsets for dynamic clock gating. 1st value - in the array represents offset of the control - register. 2nd value represents bit offset within - control register. Number of offsets defined should - match the number of xin-ids defined in - property: qcom,sde-inline-rot-xin -- qcom,sde-secure-sid-mask: Array of secure SID masks used during - secure-camera/secure-display usecases. -- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0. -- #list-cells: Number of mdp cells, must be 1. -- qcom,sde-mixer-display-pref: A string array indicating the preferred display type - for the mixer block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block. - for CWB. Possible values: - "cwb" - preferred for cwb - "none" - no preference on display -- qcom,sde-mixer-dcwb-pref: A string array indicating the preferred mixer block. - for Dedicated-CWB. Possible values: - "dcwb" - preferred for dedicated-cwb - "none" - no preference on display -- qcom,sde-ctl-display-pref: A string array indicating the preferred display type - for the ctl block. Possible values: - "primary" - preferred for primary display - "none" - no preference on display -- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe - ordering block - 0: lower priority pipe has to be on the left for a given pair of pipes. - 1: priority have to be explicitly configured for a given pair of pipes. -- qcom,sde-trusted-vm-env: Boolean property to indicate if the device - driver is executing in a trusted VM -- qcom,sde-max-trusted-vm-displays: A u32 property to indicate the maximum - number of concurrent displays supported in the - trusted vm environment -- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which - should be excluded from IO memory validation list - in trusted vm environment -- qcom,tvm-include-reg An array of u32 tuplets indicating the address - ranges of the display sub-device registers -- qcom,vram-size: A u32 value indicating the size of the VRAM in bytes -- qcom,pmic-arb-address: A u32 array of display related SPMI address - bit mask, which is a combination of SID and pheripheral id's. -- qcom,sde-ib-bw-vote: A u32 array of IB bandwidth vote values in kbps for - MNOC, LLCC and DDR/EBI respectively. -- qcom,sde-dnsc-blur-version: A u32 value indicating the downscale blur version -- qcom,sde-dnsc-blur-off: An array of u32 values with the offset for the downscale blur - block, from the "mdp_phys". -- qcom,sde-dnsc-blur-size: A u32 value indicates the downscale blur block address range. -- qcom,sde-dnsc-blur-gaus-lut-off: An array of u32 values with the offset for gaussian LUT - block, from the dnsc-blur-off -- qcom,sde-dnsc-blur-gaus-lut-size: A u32 value indicates the gaussian LUT block address range. -- qcom,sde-dnsc-blur-dither-off: An array of u32 values with the offset for dither - block, from the dnsc-blur-off -- qcom,sde-dnsc-blur-dither-size: A u32 value indicates the dither block address range. - -Bus Scaling: -- interconnects An array of 4 cell properties with the format of - (src-noc master-id dst-noc slave-id) as described in: - Documentation/devicetree/bindings/interconnect/interconnect.txt - One entry for each interconnect path available. - Master/Slave ID bindings can be found at: - include/dt-bindings/interconnect/ -- interconnect-names An array of string properties associated with "interconnects" - each with a unique name used to lookup the respective path. - The following paths are currently supported: qcom,sde-reg-bus, - qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, - qcom,sde-ebi-bus -- qcom,sde-reg-bus,vectors-KBps:A series of 2 cell properties with a format of - (ab, ib) specified in kilobytes-per-second. - Used when applying reg-bus votes and must be - given whenever "qcom,sde-reg-bus" is used. -- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle, - instance id), of inline rotator device. - -SMMU Subnodes: -- smmu_sde_****: Child nodes representing sde smmu virtual - devices - -Subnode properties: -- compatible: Compatible names used for smmu devices. - names should be: - "qcom,smmu_sde_unsec": smmu context bank device - for unsecure sde real time domain. - "qcom,smmu_sde_sec": smmu context bank device - for secure sde real time domain. - "qcom,smmu_sde_nrt_unsec": smmu context bank device - for unsecure sde non-real time domain. - "qcom,smmu_sde_nrt_sec": smmu context bank device - for secure sde non-real time domain. - - -Please refer to ../../interrupt-controller/interrupts.txt for a general -description of interrupt bindings. - -Example: - mdss_mdp: qcom,mdss_mdp@900000 { - compatible = "qcom,sde-kms"; - reg = <0x00900000 0x90000>, - <0x009b0000 0x1040>, - <0x009b8000 0x1040>, - <0x0aeac000 0x00f0>; - reg-names = "mdp_phys", - "vbif_phys", - "vbif_nrt_phys", - "regdma_phys"; - qcom,tvm-include-reg = <0xaf20000 0x4d68>, - <0xaf30000 0x3fd4>; - clocks = <&clock_mmss clk_mdss_ahb_clk>, - <&clock_mmss clk_mdss_axi_clk>, - <&clock_mmss clk_mdp_clk_src>, - <&clock_mmss clk_mdss_mdp_vote_clk>, - <&clock_mmss clk_smmu_mdp_axi_clk>, - <&clock_mmss clk_mmagic_mdss_axi_clk>, - <&clock_mmss clk_mdss_vsync_clk>; - clock-names = "iface_clk", - "bus_clk", - "core_clk_src", - "core_clk", - "iommu_clk", - "mmagic_clk", - "vsync_clk"; - clock-rate = <0>, <0>, <0>; - clock-max-rate= <0 320000000 0>; - clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; - mmagic-supply = <&gdsc_mmagic_mdss>; - vdd-supply = <&gdsc_mdss>; - interrupt-parent = <&intc>; - interrupts = <0 83 0>; - interrupt-controller; - #interrupt-cells = <1>; - iommus = <&mdp_smmu 0>; - #power-domain-cells = <0>; - - qcom,sde-hw-version = <0x70000000>; - qcom,hw-fence-sw-version = <0x1>; - qcom,sde-emulated-env; - qcom,sde-off = <0x1000>; - qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 - 0x00002600 0x00002800>; - qcom,sde-ctl-display-pref = "primary", "none", "none", - "none", "none"; - qcom,sde-mixer-off = <0x00045000 0x00046000 - 0x00047000 0x0004a000>; - qcom,sde-mixer-display-pref = "primary", "none", - "none", "none"; - qcom,sde-mixer-cwb-pref = "none", "none", - "cwb", "none"; - qcom,sde-dspp-top-off = <0x1300>; - qcom,sde-dspp-off = <0x00055000 0x00057000>; - qcom,sde-dspp-ad-off = <0x24000 0x22800>; - qcom,sde-dspp-ad-version = <0x00030000>; - qcom,sde-dspp-rc-version = <0x00010000>; - qcom,sde-dspp-rc-off = <0x15800 0x14c00>; - qcom,sde-dspp-rc-size = <0x100>; - qcom,sde-dspp-rc-min-region-width = <20>; - qcom,sde-dspp-spr-off = <0x15400 0x14400>; - qcom,sde-dspp-spr-size = <0x200>; - qcom,sde-dspp-spr-version = <0x00010000>: - qcom,sde-dspp-demura-off = <0x15600 0x14800>; - qcom,sde-dspp-demura-size = <0x200>; - qcom,sde-dspp-demura-version = <0x00010000>; - qcom,sde-lm-noise-off = <0x320>; - qcom,sde-lm-noise-version = <0x00010000>; - - qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; - qcom,sde-dspp-aiqe-version = <0x00010000>; - qcom,sde-dspp-aiqe-size = <0x3fc>; - - qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; - qcom,sde-dspp-aiqe-dither-version = <0x00010000>; - qcom,sde-dspp-aiqe-dither-size = <0x20>; - - qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; - qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; - qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; - - qcom,sde-aiqe-has-feature-mdnie; - qcom,sde-aiqe-has-feature-abc; - qcom,sde-aiqe-has-feature-ssrc; - qcom,sde-aiqe-has-feature-copr; - - qcom,sde-dspp-rc-mem-size = <2720>; - qcom,sde-dest-scaler-top-off = <0x00061000>; - qcom,sde-dest-scaler-off = <0x800 0x1000>; - qcom,sde-wb-off = <0x00066000>; - qcom,sde-wb-xin-id = <6>; - qcom,sde-intf-off = <0x0006b000 0x0006b800 - 0x0006c000 0x0006c800>; - qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; - qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; - qcom,sde-pp-off = <0x00071000 0x00071800 - 0x00072000 0x00072800>; - qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; - qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; - qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; - qcom,sde-cdm-off = <0x0007a200>; - qcom,sde-dsc-off = <0x00081000 0x00081400>; - qcom,sde-vdc-off = <0x7C000>; - qcom,sde-vdc-size = <0xf10>; - qcom,sde-vdc-hw-rev = "vdc_1_2"; - qcom,sde-vdc-enc = <0x200>; - qcom,sde-vdc-ctl = <0xf00>; - qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; - - qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; - qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 - 0xb0 0xc8 0xe0 0xf8 0x110>; - - qcom,sde-qdss-off = <0x81a00>; - - qcom,sde-sspp-type = "vig", "vig", "vig", - "vig", "rgb", "rgb", - "rgb", "rgb", "dma", - "dma", "cursor", "cursor"; - - qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 - 0x0000b000 0x00015000 0x00017000 - 0x00019000 0x0001b000 0x00025000 - 0x00027000 0x00035000 0x00037000>; - - qcom,sde-sspp-xin-id = <0 4 8 - 12 1 5 - 9 13 2 - 10 7 7>; - - /* offsets are relative to "mdp_phys + qcom,sde-off */ - qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, - <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, - <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, - <0x3b0 16>; - qcom,sde-scaling-linewidth = <2560>; - qcom,sde-mixer-linewidth = <2560>; - qcom,sde-sspp-linewidth = <2560>; - qcom,sde-mixer-blendstages = <0x7>; - qcom,sde-dsc-linewidth = <2048>; - qcom,sde-highest-bank-bit = <0x7 0x2>; - qcom,sde-ubwc-version = <0x10000000>; - qcom,sde-ubwc-static = <0x100>; - qcom,sde-ubwc-swizzle = <0>; - qcom,sde-ubwc-bw-calc-version = <0x1>; - qcom,sde-smart-panel-align-mode = <0xd>; - qcom,sde-panic-per-pipe; - qcom,sde-has-src-split; - qcom,sde-pipe-order-version = <0x1>; - qcom,sde-has-dim-layer; - qcom,sde-sspp-src-size = <0x100>; - qcom,sde-mixer-size = <0x100>; - qcom,sde-ctl-size = <0x100>; - qcom,sde-dspp-top-size = <0xc>; - qcom,sde-dspp-size = <0x100>; - qcom,sde-intf-size = <0x100>; - qcom,sde-dsc-size = <0x100>; - qcom,sde-cdm-size = <0x100>; - qcom,sde-pp-size = <0x100>; - qcom,sde-wb-size = <0x100>; - qcom,sde-dest-scaler-top-size = <0xc>; - qcom,sde-dest-scaler-size = <0x800>; - qcom,sde-len = <0x100>; - qcom,sde-wb-linewidth = <2560>; - qcom,sde-wb-linewidth-linear = <5120>; - qcom,sde-sspp-scale-size = <0x100>; - qcom,sde-mixer-blendstages = <0x8>; - qcom,sde-qseed-sw-lib-rev = "qseedv2"; - qcom,sde-qseed-scalar-version = <0x3000>; - qcom,sde-csc-type = "csc-10bit"; - qcom,sde-highest-bank-bit = <15>; - qcom,sde-has-mixer-gc; - qcom,sde-has-idle-pc; - qcom,sde-wakeup-with-touch; - qcom,fullsize-va-map; - qcom,sde-has-dest-scaler; - qcom,sde-max-trusted-vm-displays = <1>; - qcom,sde-max-dest-scaler-input-linewidth = <2048>; - qcom,sde-max-dest-scaler-output-linewidth = <2560>; - qcom,sde-sspp-max-rects = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-excl-rect = <1 1 1 1 - 1 1 1 1 - 1 1 - 1 1>; - qcom,sde-sspp-smart-dma-priority = <0 0 0 0 - 0 0 0 0 - 0 0 - 1 2>; - qcom,sde-smart-dma-rev = "smart_dma_v2"; - qcom,sde-te-off = <0x100>; - qcom,sde-te2-off = <0x100>; - qcom,sde-te-size = <0xffff>; - qcom,sde-te2-size = <0xffff>; - qcom,sde-trusted-vm-env; - - qcom,sde-wb-id = <2>; - qcom,sde-wb-clk-ctrl = <0x2bc 16>; - qcom,sde-wb-clk-status = <0x3bc 20>; - - qcom,sde-qos-refresh-rates = <60 120>; - qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, - <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, - 0xffff0000 0xffff0000>; - qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, - <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, - 0xff>; - qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 - 0x00112234 0x45566777 0x00112236 0x67777777 - 0x0 0x0 0x0 0x0 - 0x77776666 0x66666540 0x77776666 0x66666540 - 0x77776541 0x00000000 0x77776541 0x00000000 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x55555544 0x33221100 0x55555544 0x33221100>, - <0x02344455 0x56667777 0x02366677 0x77777777 - 0x02344455 0x56667777 0x02366677 0x77777777 - 0x0 0x0 0x0 0x0 - 0x77776666 0x66666540 0x77776666 0x66666540 - 0x77776541 0x00000000 0x77776541 0x00000000 - 0x02344455 0x56667777 0x02366677 0x77777777 - 0x00123445 0x56677777 0x00123667 0x77777777 - 0x55555544 0x33221100 0x55555544 0x33221100>; - - qcom,sde-cdp-setting = <1 1>, <1 0>; - - qcom,sde-qos-cpu-mask = <0x3>; - qcom,sde-qos-cpu-mask-performance = <0xf>; - qcom,sde-qos-cpu-dma-latency = <300>; - qcom,sde-qos-cpu-irq-latency = <300>; - - qcom,sde-soccp-controller = <&soccp_pas>; - qcom,sde-ipcc-protocol-id = <0x2>; - qcom,sde-ipcc-client-dpu-phys-id = <0x19>; - qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; - - qcom,sde-vbif-off = <0 0>; - qcom,sde-vbif-id = <0 1>; - qcom,sde-vbif-default-ot-rd-limit = <32>; - qcom,sde-vbif-default-ot-wr-limit = <16>; - qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, - <124416000 4>, <248832000 16>; - qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; - qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; - - qcom,sde-uidle-off = <0x80000>; - qcom,sde-uidle-size = <0x70>; - - qcom,sde-dram-channels = <2>; - qcom,sde-num-nrt-paths = <1>; - - qcom,sde-max-bw-high-kbps = <9000000>; - qcom,sde-max-bw-low-kbps = <9000000>; - - qcom,sde-core-ib-ff = "1.1"; - qcom,sde-core-clk-ff = "1.0"; - qcom,sde-min-core-ib-kbps = <2400000>; - qcom,sde-min-llcc-ib-kbps = <800000>; - qcom,sde-min-dram-ib-kbps = <800000>; - qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; - qcom,sde-undersized-prefill-lines = <4>; - qcom,sde-xtra-prefill-lines = <5>; - qcom,sde-dest-scale-prefill-lines = <6>; - qcom,sde-macrotile-prefill-lines = <7>; - qcom,sde-yuv-nv12-prefill-lines = <8>; - qcom,sde-linear-prefill-lines = <9>; - qcom,sde-downscaling-prefill-lines = <10>; - qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 - 2400000 2400000 2400000 2400000>; - qcom,sde-amortizable-threshold = <11>; - qcom,sde-secure-sid-mask = <0x200801 0x200c01>; - - qcom,sde-dnsc-blur-version = <0x100>; - qcom,sde-dnsc-blur-off = <0x7D000>; - qcom,sde-dnsc-blur-size = <0x40>; - qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; - qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; - qcom,sde-dnsc-blur-dither-off = <0x5E0>; - qcom,sde-dnsc-blur-dither-size = <0x20>; - - qcom,vram-size = <0x200000>; - qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; - - qcom,sde-ib-bw-vote = <2500000 0 800000>; - - qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; - qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; - qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; - qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; - qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; - - qcom,sde-reg-dma-off = <0 0x400>; - qcom,sde-reg-dma-id = <0 1>; - qcom,sde-reg-dma-version = <0x00020000>; - qcom,sde-reg-dma-trigger-off = <0x119c>; - qcom,sde-reg-dma-broadcast-disabled = <0>; - qcom,sde-reg-dma-xin-id = <7>; - qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; - - nvmem-cells = <&ssip_config>; - nvmem-cell-names = "ssip_config"; - - qcom,sde-sspp-vig-blocks { - vcm@0 { - cell-index = <0>; - qcom,sde-vig-top-off = <0xa00>; - qcom,sde-vig-csc-off = <0x1a00>; - qcom,sde-vig-qseed-off = <0xa00>; - qcom,sde-vig-qseed-size = <0xe0>; - qcom,sde-vig-gamut = <0x1d00 0x00060001>; - qcom,sde-vig-igc = <0x1d00 0x00060000>; - /* Offset from vig top, version of HSIC */ - qcom,sde-vig-hsic = <0x200 0x00010000>; - qcom,sde-vig-memcolor = <0x200 0x00010000>; - qcom,sde-vig-pcc = <0x1780 0x00010000>; - qcom,sde-vig-inverse-pma; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; - }; - - vcm@1 { - cell-index = <1>; - qcom,sde-fp16-igc = <0x280 0x00010000>; - qcom,sde-fp16-unmult = <0x280 0x00010000>; - qcom,sde-fp16-gc = <0x280 0x00010000>; - qcom,sde-fp16-csc = <0x280 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; - }; - }; - - qcom,sde-sspp-dma-blocks { - dgm@0 { - cell-index = <0>; - qcom,sde-dma-top-off = <0x800>; - qcom,sde-dma-igc = <0x400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x200>; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x700 0x00010000>; - qcom,sde-ucsc-unmult = <0x700 0x00010000>; - qcom,sde-ucsc-gc = <0x700 0x00010000>; - qcom,sde-ucsc-csc = <0x700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; - }; - - dgm@1 { - cell-index = <1>; - qcom,sde-dma-igc = <0x1400 0x00050000>; - qcom,sde-dma-gc = <0x600 0x00050000>; - qcom,sde-dma-inverse-pma; - qcom,sde-dma-csc-off = <0x1200>; - qcom,sde-fp16-igc = <0x200 0x00010000>; - qcom,sde-fp16-unmult = <0x200 0x00010000>; - qcom,sde-fp16-gc = <0x200 0x00010000>; - qcom,sde-fp16-csc = <0x200 0x00010000>; - qcom,sde-ucsc-igc = <0x1700 0x00010000>; - qcom,sde-ucsc-unmult = <0x1700 0x00010000>; - qcom,sde-ucsc-gc = <0x1700 0x00010000>; - qcom,sde-ucsc-csc = <0x1700 0x00010000>; - qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; - }; - }; - - qcom,sde-sspp-rgb-blocks { - qcom,sde-rgb-scaler-off = <0x200>; - qcom,sde-rgb-scaler-size = <0x74>; - qcom,sde-rgb-pcc = <0x380 0x00010000>; - }; - - qcom,sde-dspp-blocks { - qcom,sde-dspp-igc = <0x0 0x00010000>; - qcom,sde-dspp-pcc = <0x1700 0x00010000>; - qcom,sde-dspp-gc = <0x17c0 0x00010000>; - qcom,sde-dspp-hsic = <0x0 0x00010000>; - qcom,sde-dspp-memcolor = <0x0 0x00010000>; - qcom,sde-dspp-sixzone = <0x0 0x00010000>; - qcom,sde-dspp-gamut = <0x1600 0x00010000>; - qcom,sde-dspp-dither = <0x0 0x00010000>; - qcom,sde-dspp-hist = <0x0 0x00010000>; - qcom,sde-dspp-vlut = <0x0 0x00010000>; - }; - - qcom,sde-mixer-blocks { - qcom,sde-mixer-gc = <0x3c0 0x00010000>; - }; - - qcom,msm-hdmi-audio-rx { - compatible = "qcom,msm-hdmi-audio-codec-rx"; - }; - - qcom,sde-inline-rotator = <&mdss_rotator 0>; - qcom,sde-inline-rot-xin = <10 11>; - qcom,sde-inline-rot-xin-type = "sspp", "wb"; - qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; - - qcom,platform-supply-entries { - #address-cells = <1>; - #size-cells = <0>; - qcom,platform-supply-entry@0 { - reg = <0>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - qcom,supply-pre-on-sleep = <0>; - qcom,supply-post-on-sleep = <0>; - qcom,supply-pre-off-sleep = <0>; - qcom,supply-post-off-sleep = <0>; - }; - }; - - interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> - <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, - <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, - <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, - <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; - interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", - "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; - qcom,sde-reg-bus,vectors-KBps = <0 0>, - <0 76800>, - <0 150000>, - <0 300000>; - - smmu_kms_unsec: qcom,smmu_kms_unsec_cb { - compatible = "qcom,smmu_sde_unsec"; - iommus = <&mmss_smmu 0>; - }; - - smmu_kms_sec: qcom,smmu_kms_sec_cb { - compatible = "qcom,smmu_sde_sec"; - iommus = <&mmss_smmu 1>; - }; - }; diff --git a/bindings/sde.yaml b/bindings/sde.yaml new file mode 100644 index 00000000..8f7361bc --- /dev/null +++ b/bindings/sde.yaml @@ -0,0 +1,2076 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE KMS + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + - Jatin Srivastava + +description: | + Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user + interface to different panel interfaces. SDE driver is the core of + display subsystem which manage all data paths to different panel interfaces + Please refer to ../../interrupt-controller/interrupts.txt for a general + description of interrupt bindings. + +properties: + compatible: + const: qcom,sde-kms + + qcom,msm-hdmi-audio-rx: + type: object + compatible: + const: qcom,msm-hdmi-audio-codec-rx + + reg: + description: | + Offset and length of the register set for the device.Base address and length of DP hardware's + memory mapped regions. + + reg-names: + description: Names to refer to register sets related to this device + $ref: /schemas/types.yaml#/definitions/string-array + + clocks: + description: List of Phandles for clock device nodes needed by the device. + + clock-names: + description: List of clock names needed by the device. + $ref: /schemas/types.yaml#/definitions/string-array + + mmagic-supply: + description: Phandle for mmagic mdss supply regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdd-supply: + description: Phandle for vdd regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: Must be core interrupt controller. + + interrupts: + description: Interrupt associated with MDSS. + + interrupt-controller: + description: Mark the device node as an interrupt controller. + + '#interrupt-cells': + description: Should be one. The first cell is interrupt number. + + iommus: + description: Specifies the SID's used by this context bank. + + qcom,sde-sspp-type: + description: | + Array of strings for SDE source surface pipes type information. + A source pipe can be "vig", "rgb", "dma" or "cursor" type. + Number of xin ids defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [vig, rgb, dma, cursor] + + qcom,sde-sspp-off: + description: | + Array of offset for SDE source surface pipes. The offsets + are calculated from register "mdp_phys" defined in + reg property + "sde-off". The number of offsets defined here should + reflect the amount of pipes that can be active in SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective source pipes. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ctl-off: + description: | + Array of offset addresses for the available ctl + hw blocks within SDE, these offsets are + calculated from register "mdp_phys" defined in + reg property. The number of ctl offsets defined + here should reflect the number of control paths + that can be configured concurrently on SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-off: + description: | + Array of offset addresses for the programmable + writeback blocks within SDE. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective writeback. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-wb-off.. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-off: + description: | + Array of offset addresses for the available + mixer blocks that can drive data to panel + interfaces. These offsets are be calculated from + register "mdp_phys" defined in reg property. + The number of offsets defined should reflect the + amount of mixers that can drive data to a panel + interface. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-top-off: + description: | + Offset address for the dspp top block. + The offset is calculated from register "mdp_phys" + defined in reg property. + + qcom,sde-dspp-off: + description: | + Array of offset addresses for the available dspp + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-off: + description: | + Array of offset addresses for the available + pingpong blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-slave: + description: | + Array of flags indicating whether each ping pong + block may be configured as a pp slave. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-merge-3d-id: + description: | + Array of index ID values for the merge 3d block + connected to each pingpong, starting at 0. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-merge-3d-off: + description: | + Array of offset addresses for the available + merge 3d blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-intf-off: + description: | + Array of offset addresses for the available SDE + interface blocks that can drive data to a + panel controller. The offsets are calculated + from "mdp_phys" defined in reg property. The number + of offsets defined should reflect the number of + programmable interface blocks available in hardware. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-blend-op-off: + description: | + Array of offset addresses for the available + blending stages. The offsets are relative to + qcom,sde-mixer-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-pair-mask: + description: | + Array of mixer numbers that can be paired with + mixer number corresponding to the array index. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clock-rate: + description: List of clock rates in Hz. + + clock-max-rate: + description: List of maximum clock rate in Hz that this device supports. + + clock-mmrm: + description: | + List of clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' properties. + The 'DISP_CC' ID of the clock must be used to enable the property for the + respective clock, whereas a value of zero disables the property. + + qcom,platform-supply-entries: + description: | + A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + type: object + patternProperties: + "qcom,platform\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-hw-version: + description: A u32 value indicates the MDSS hw version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hw-fence-sw-version: + description: | + A u32 value to indicate the hw fencing version. If set to a value + greather than zero, driver will attempt to enable the feature (if + supported by the HW). Otherwise, if this value is not set or set + to zero, feature will remain disabled. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-src-size: + description: A u32 value indicates the address range for each sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-size: + description: A u32 value indicates the address range for each mixer. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ctl-size: + description: A u32 value indicates the address range for each ctl. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-size: + description: A u32 value indicates the address range for each dspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-size: + description: A u32 value indicates the address range for each intf. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-size: + description: A u32 value indicates the address range for each dsc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-size: + description: A u32 value indicates the address range for each vdc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cdm-size: + description: A u32 value indicates the address range for each cdm. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-size: + description: A u32 value indicates the address range for each pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-merge-3d-size: + description: A u32 value indicates the address range for each merge 3d. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-cwb: + description: | + Array of u32 flags indicating whether each ping pong + block may be configured as a cwb pp block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-size: + description: A u32 value indicates the address range for each writeback. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-len: + description: A u32 entry for SDE address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-max-prefetch-lines: + description: Array of u32 values for max prefetch lines on each interface. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-linewidth: + description: A u32 value indicates the max sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vig-sspp-linewidth: + description: A u32 value indicates the max vig sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-scaling-linewidth: + description: A u32 value indicates the max vig source pipe line width for scaling purposes. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-linewidth: + description: A u32 value indicates the max mixer line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth: + description: A u32 value indicates the max writeback line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth-linear: + description: A u32 value indicates the max line width supported by WB for linear color formats. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-scale-size: + description: A u32 value indicates the scaling block size on sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blendstages: + description: A u32 value indicates the max mixer blend stages for alpha blending. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qseed-sw-lib-rev: + description: | + A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: qseedv2 + + qcom,sde-qseed-scalar-version: + description: A u32 value indicating the HW version of the QSEED hardware block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-csc-type: + description: | + A string entry indicates csc support on sspp and wb. + It supports "csc" and "csc-10bit" entries for csc + type. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [csc, csc-10bit] + + qcom,sde-highest-bank-bit: + description: | + Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. + + qcom,sde-ubwc-version: + description: | + Property to specify the UBWC feature version. A u32 UBWC version is based on + MDSS support. + + qcom,sde-ubwc-static: + description: Property to specify the default UBWC static configuration value. + + qcom,sde-ubwc-bw-calc-version: + description: A u32 property to specify version of UBWC bandwidth calculation algorithm + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ubwc-swizzle: + description: Property to specify the default UBWC swizzle configuration value. + + qcom,sde-smart-panel-align-mode: + description: | + A u32 property to specify the align mode for + split display on smart panel. Possible values: + 0x0 - no alignment + 0xc - align at start of frame + 0xd - align at start of line + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0x0, 0xc, 0xd] + + qcom,sde-panic-per-pipe: + description: | + Boolean property to indicate if panic signal control feature is available on each + source pipe. + + qcom,sde-has-src-split: + description: | + Boolean property to indicate if source split + feature is available or not. + + qcom,sde-has-dim-layer: + description: | + Boolean property to indicate if mixer has dim layer + feature is available or not. + + qcom,sde-has-idle-pc: + description: | + Boolean property to indicate if target has idle + power collapse feature available or not. + + qcom,sde-wakeup-with-touch: + description: | + Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. + + qcom,sde-has-mixer-gc: + description: | + Boolean property to indicate if mixer has gamma correction + feature available or not. + + qcom,sde-has-dest-scaler: + description: | + Boolean property to indicate if destination scaler + feature is available or not. + + qcom,sde-max-dest-scaler-input-linewidth: + description: | + A u32 value indicates the + maximum input line width to destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-dest-scaler-output-linewidth: + description: | + A u32 value indicates the + maximum output line width of destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-off: + description: | + A u32 value provides the + offset from mdp base to destination scaler block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-size: + description: A u32 value indicates the address range for ds top + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-off: + description: | + Array of u32 offsets indicate the qseed3 scaler blocks + offset from destination scaler top offset. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dest-scaler-size: + description: A u32 value indicates the address range for each scaler block + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-clk-status: + description: | + Array of offsets describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-excl-rect: + description: | + Array of u32 values indicating exclusion rectangle + support on each sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-smart-dma-priority: + description: | + Array of u32 values indicating hw pipe + priority of secondary rectangles when smart dma + is supported. Number of priority values should + match the number of offsets defined in + qcom,sde-sspp-off node. Zero indicates no support + for smart dma for the sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-smart-dma-rev: + description: | + A string entry indicating the smart dma version + supported on the device. Supported entries are + "smart_dma_v1" and "smart_dma_v2". + $ref: /schemas/types.yaml#/definitions/string-array + enum: [smart_dma_v1, smart_dma_v2] + + qcom,sde-vdc-hw-rev: + description: A string indicating the hw version of vdc. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-intf-type: + description: | + Array of string provides the interface type information. + Possible string values + "dsi" - dsi display interface + "dp" - Display Port interface + "hdmi" - HDMI display interface + An interface is considered as "none" if interface type + is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: none + enum: [dsi, dp, hdmi] + + qcom,sde-intf-tear-irq-off: + description: | + Array of offset addresses for the available + tear effect (TE) IRQ blocks from "mdp_phys". + There should be one entry per INTF instance with + a zero value for INTFs without TE IRQ block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-emulated-env: + description: | + Boolean property to indicate if the MDSS is running in an + emulated environment. + + qcom,sde-off: + description: SDE offset from "mdp_phys" defined in reg property. + + qcom,sde-cdm-off: + description: | + Array of offset addresses for the available + cdm blocks. These offsets will be calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-off: + description: | + Array of offset addresses for the available + vbif blocks. These offsets will be calculated from + register "vbif_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-size: + description: A u32 value indicates the vbif block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-off: + description: | + A u32 value with the offset for the uidle block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-size: + description: A u32 value indicates the uidle block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-off: + description: | + A u32 offset indicates the te block offset on pingpong. + This offset is 0x0 by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-off: + description: A u32 offset indicates the te2 block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-size: + description: A u32 value indicates the te block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-size: + description: A u32 value indicates the te2 block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-off: + description: | + Array of offset addresses for the available dsc + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-hw-rev: + description: A string value indicates the dsc hw block version. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-dsc-enc: + description: | + Array of offset addresses for the available dsc + encoder blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-ctl: + description: | + Array of offset addresses for the available dsc + ctl blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-native422-supp: + description: | + Array of flags indicating whether corresponding dsc + block can support native 422 and native 420 + encoding. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-linewidth: + description: A u32 value indicates the max dsc line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-off: + description: | + A u32 offset address for the available vdc blocks. + This offset is calculated from register "mdp_phys" + defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc: + description: | + A u32 offset address for the vdc encoder block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl: + description: | + A u32 offset address for the vdc ctl block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qdss-off: + description: A u32 offset indicates the qdss block offset. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-off: + description: A u32 offset indicates the dither block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-version: + description: A u32 value indicates the dither block version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cwb-dither: + description: | + Array of u32 flags indicating whether each dither block + may be configured as a cwb dither block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-vig-blocks: + description: | + A node that lists the blocks inside the VIG hardware. There can + be more than one instance of this binding, in which case the + entry would be appended with the vcm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP VIG contains + that feature hardware. Eg: vcm@0 + type: object + patternProperties: + "vcm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-off: + description: offset of QSEED hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-size: + description: A u32 address range for qseed scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-gamut: + description: offset and version of 3D LUT Gamut hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-igc: + description: offset and version of 1D LUT IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on VIG pipe + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-dma-blocks: + description: | + A node that lists the blocks inside the DMA hardware. There + can be more than one instance of this binding, in which case the + entry would be appended with dgm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP DMA contains + that feature hardware. + e.g. qcom,sde-sspp-dma-blocks + -- dgm@0 + type: object + patternProperties: + "dgm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-igc: + description: offset and version of DMA IGC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-gc: + description: offset and version of DMA GC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on DMA pipe. + qcom,sde-dma-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-rgb-blocks: + description: | + A node that lists the blocks inside the RGB hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP RGB contains that feature hardware. + e.g. qcom,sde-sspp-rgb-blocks + type: object + properties: + qcom,sde-rgb-scaler-off: + description: offset of RGB scaler hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-scaler-size: + description: A u32 address range for scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-pcc: + description: offset and version of PCC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-blocks: + description: | + A node that lists the blocks inside the DSPP hardware. The + block entries will contain the offset and version of each + feature block. The presence of a block entry indicates that + the DSPP contains that feature hardware. + e.g. qcom,sde-dspp-blocks + type: object + properties: + qcom,sde-dspp-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gc: + description: offset and version of GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-igc: + description: offset and version of IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-sixzone: + description: offset and version of PA sixzone hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gamut: + description: offset and version of Gamut mapping hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-dither: + description: offset and version of dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hist: + description: offset and version of histogram hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-vlut: + description: offset and version of PA vLUT hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blocks: + description: | + A node that lists the blocks inside the layer mixer hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the layer mixer contains that feature hardware. + e.g. qcom,sde-mixer-blocks + - qcom,sde-mixer-gc: offset and version of mixer GC hardware + + qcom,sde-dspp-ad-off: + description: | + Array of u32 offsets indicate the ad block offset from the + DSPP offset. Since AD hardware is represented as part of + DSPP block, the AD offsets must be offset from the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-ad-version: + description: A u32 value indicating the version of the AD hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-version: + description: | + A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) + version of the LTM hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-off: + description: | + Array of u32 offsets indicate the LTM block offsets from the + DSPP offsets. Since LTM hardware is represented as part of + DSPP block, the LTM offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-rc-version: + description: A u32 value indicating the version of the RC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-off: + description: | + Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-size: + description: A u32 value indicating the RC block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-mem-size: + description: A u32 value indicating the RC block shared memory size. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-min-region-width: + description: A u32 value indicating the RC block minimum region width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-off: + description: | + Array of u32 offsets indicate the SPR block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-spr-size: + description: A u32 value indicating the SPR block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-version: + description: A u32 value indicating the version of SPR hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-off: + description: | + Array of u32 offsets indicate the demura block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-demura-size: + description: A u32 value indicating the demura block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-version: + description: A u32 value indicating the version of demura hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-off: + description: | + Array of u32 values indicating the offset of each AIQE block + relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-version: + description: A u32 value indicating the version of the AIQE hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-size: + description: | + A u32 value indicating the shared memory size of each AIQE + hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-off: + description: | + Array of u32 values indicating the offset of each AIQE + dither block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-dither-version: + description: A u32 value indicating the version of the AIQE dither hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-size: + description: | + A u32 value indicating the shared memory size of each AIQE + dither hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-off: + description: | + Array of u32 values indicating the offset of each AIQE + wrapper block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-wrapper-version: + description: A u32 value indicating the version of the AIQE wrapper hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-size: + description: | + A u32 value indicating the shared memory size of each AIQE + wrapper hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-off: + description: | + Array of u32 values indicating the offset of each AIQE + AI Scaler block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-aiscaler-version: + description: A u32 value indicating the version of the AIQE AI Scaler hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-size: + description: | + A u32 value indicating the shared memory size of each AIQE + AI Scaler hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-aiqe-has-feature-mdnie: + description: Boolean property indicating the presence of AIQE feature mDNIe hardware. + + qcom,sde-aiqe-has-feature-abc: + description: Boolean property indicating the presence of AIQE feature ABC hardware. + + qcom,sde-aiqe-has-feature-ssrc: + description: Boolean property indicating the presence of AIQE feature SSRC hardware. + + qcom,sde-aiqe-has-feature-copr: + description: Boolean property indicating the presence of AIQE feature COPR hardware. + + qcom,sde-aiqe-has-feature-aiscaler: + description: Boolean property indicating the presence of AIQE feature AI Scaler hardware. + + qcom,sde-lm-noise-off: + description: A u32 value indicating noise layer offset from mixer base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-lm-noise-version: + description: A u32 value indicating the noise layer version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-id: + description: | + Array of vbif ids corresponding to the + offsets defined in property: qcom,sde-vbif-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-default-ot-rd-limit: + description: A u32 value indicates the default read OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-default-ot-wr-limit: + description: A u32 value indicates the default write OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-dynamic-ot-rd-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the read limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-dynamic-ot-wr-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the write limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-memtype-0: + description: Array of u32 vbif memory type settings, group 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-memtype-1: + description: Array of u32 vbif memory type settings, group 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-id: + description: | + Array of writeback ids corresponding to the + offsets defined in property: qcom,sde-wb-off. + + qcom,sde-wb-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-wb-clk-status: + description: | + Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-reg-dma-off: + description: | + Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-id: + description: | + Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-version: + description: Version of the reg dma hardware blocks. + + qcom,sde-reg-dma-trigger-off: + description: | + Offset of the lut dma trigger reg from "mdp_phys" + defined in reg property. + + qcom,sde-reg-dma-broadcast-disabled: + description: | + Boolean property to indicate if broadcast + functionality in the register dma hardware block should be used. + + qcom,sde-reg-dma-xin-id: + description: VBIF clients id (xin) corresponding to the LUTDMA block. + + qcom,sde-reg-dma-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: offset of the control register + - description: bit offset within the control register + + qcom,sde-dram-channels: + description: This represents the number of channels in the Bus memory controller. + + qcom,sde-num-nrt-paths: + description: | + Integer property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. + + qcom,sde-max-bw-low-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow. + This is a low bandwidth threshold which should + be applied in most scenarios to be safe from + underflows when unable to satisfy bandwidth + requirements. + + qcom,sde-max-bw-high-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow in the + event where there is no VFE. + This is a high bandwidth threshold which can be + applied in scenarios where panel interface can + be more tolerant to memory latency such as + command mode panels. + + qcom,sde-core-ib-ff: + description: A string entry indicating the fudge factor for core ib calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-core-clk-ff: + description: | + A string entry indicating the fudge factor for + core clock calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-min-core-ib-kbps: + description: | + This u32 value indicates the minimum mnoc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-llcc-ib-kbps: + description: | + This u32 value indicates the minimum llcc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-dram-ib-kbps: + description: | + This u32 value indicates the minimum dram ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-comp-ratio-rt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-comp-ratio-nrt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on non-realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-undersized-prefill-lines: + description: A u32 value indicates the size of undersized prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-xtra-prefill-lines: + description: A u32 value indicates the extra prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scale-prefill-lines: + description: A u32 value indicates the latency of destination scaler in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-macrotile-prefill-lines: + description: A u32 value indicates the latency of macrotile in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-yuv-nv12-prefill-lines: + description: A u32 value indicates the latency of yuv/nv12 in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-linear-prefill-lines: + description: A u32 value indicates the latency of linear in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-downscaling-prefill-lines: + description: A u32 value indicates the latency of downscaling in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-per-pipe-bw-kbps: + description: Array of u32 value indicates the max per pipe bandwidth in Kbps. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-amortizable-threshold: + description: This value indicates the min for traffic shaping in lines. + + qcom,sde-vbif-qos-rt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-nrt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for non-realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cwb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for concurrent writeback clients. First 8 entries are + for rp_remap and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-lutdma-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for lutdma client. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cnoc-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for cnoc clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-offline-wb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for offline-wb clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-wb-rot-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for wb-rotation clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-qos-refresh-rates: + description: | + This u32 array indicates danger, safe and creq luts + qos configuration for different refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-danger-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the danger luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-safe-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the safe luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-creq-lut: + description: | + This u64 array of 18 cell property, with a format of + for each + entry, for qos cases from , with of-node count based + on the qos refresh rates count. + $ref: /schemas/types.yaml#/definitions/uint64-array + + qcom,sde-cdp-setting: + description: | + Array of 2 cell property, with a format of + for cdp use cases in + order of , and . + + qcom,sde-qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-mask-performance: + description: | + Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. + + qcom,sde-qos-cpu-dma-latency: + description: A u32 value indicating desired PM QoS CPU DMA latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-irq-latency: + description: A u32 value indicating desired PM QoS CPU irq latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-protocol-id: + description: A u32 value indicating ipcc protocol id used for hw fencing feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-client-dpu-phys-id: + description: | + A u32 value indicating ipcc physical client id of dpu used + for ipcc registers access. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-inline-rot-xin: + description: An integer array of xin-ids related to inline rotation. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-inline-rot-xin-type: + description: | + A string array indicating the type of xin, + namely sspp or wb. Number of entries should match + the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/string-array + enum: [sspp, wb] + + qcom,sde-inline-rot-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-secure-sid-mask: + description: Array of secure SID masks used during secure-camera/secure-display usecases. + $ref: /schemas/types.yaml#/definitions/uint32-array + + '#power-domain-cells': + description: Number of cells in a power-domain specifier and should contain 0. + + '#list-cells': + description: Number of mdp cells, must be 1. + + qcom,sde-mixer-display-pref: + description: | + A string array indicating the preferred display type + for the mixer block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-mixer-cwb-pref: + description: | + A string array indicating the preferred mixer block. + for CWB. Possible values: + "cwb" - preferred for cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [cwb, none] + + qcom,sde-mixer-dcwb-pref: + description: | + A string array indicating the preferred mixer block. + for Dedicated-CWB. Possible values: + "dcwb" - preferred for dedicated-cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dcwb, none] + + qcom,sde-ctl-display-pref: + description: | + A string array indicating the preferred display type + for the ctl block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-pipe-order-version: + description: | + A u32 property to indicate version of pipe + ordering block + 0: lower priority pipe has to be on the left for a given pair of pipes. + 1: priority have to be explicitly configured for a given pair of pipes. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,sde-trusted-vm-env: + description: | + Boolean property to indicate if the device + driver is executing in a trusted VM + + qcom,sde-max-trusted-vm-displays: + description: | + A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vm-exclude-reg-names: + description: | + A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,tvm-include-reg: + description: | + An array of u32 tuplets indicating the address + ranges of the display sub-device registers + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,vram-size: + description: A u32 value indicating the size of the VRAM in bytes + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,pmic-arb-address: + description: | + A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ib-bw-vote: + description: | + A u32 array of IB bandwidth vote values in kbps for + MNOC, LLCC and DDR/EBI respectively. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-version: + description: A u32 value indicating the downscale blur version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-off: + description: | + An array of u32 values with the offset for the downscale blur + block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-size: + description: A u32 value indicates the downscale blur block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-gaus-lut-off: + description: | + An array of u32 values with the offset for gaussian LUT + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-gaus-lut-size: + description: A u32 value indicates the gaussian LUT block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-dither-off: + description: | + An array of u32 values with the offset for dither + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + +Bus Scaling: + interconnects: + description: | + An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ + $ref: /schemas/types.yaml#/definitions/uint32-array + + interconnect-names: + description: | + An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-reg-bus,vectors-KBps: + description: | + A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. + + qcom,sde-inline-rotator: + description: | + A 2 cell property, with format of (rotator phandle, + instance id), of inline rotator device. + +patternProperties: + "qcom,smmu_sde_+\w": + description: Child nodes representing sde smmu virtual devices + $ref: /schemas/types.yaml#/definitions/string-array + compatible: + enum: + - qcom,smmu_sde_unsec: + description: smmu context bank device for unsecure sde real time domain. + - qcom,smmu_sde_sec: + description: smmu context bank device for secure sde real time domain. + - qcom,smmu_sde_nrt_unsec: + description: smmu context bank device for unsecure sde non-real time domain. + - qcom,smmu_sde_nrt_sec: + description: smmu context bank device for secure sde non-real time domain. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mmagic-supply + - vdd-supply + - interrupt-parent + - interrupts + - interrupt-controller + - '#interrupt-cells' + - iommus + - qcom,sde-sspp-type + - qcom,sde-sspp-off + - qcom,sde-sspp-xin-id + - qcom,sde-ctl-off + - qcom,sde-wb-off + - qcom,sde-wb-xin-id + - qcom,sde-mixer-off + - qcom,sde-dspp-top-off + - qcom,sde-dspp-off + - qcom,sde-pp-off + - qcom,sde-pp-slave + - qcom,sde-pp-merge-3d-id + - qcom,sde-merge-3d-off + - qcom,sde-intf-off + - qcom,sde-mixer-blend-op-off + - qcom,sde-mixer-pair-mask + +examples: + - | + mdss_mdp: qcom,mdss_mdp@900000 { + compatible = "qcom,sde-kms"; + reg = <0x00900000 0x90000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>, + <0x0aeac000 0x00f0>; + reg-names = "mdp_phys", + "vbif_phys", + "vbif_nrt_phys", + "regdma_phys"; + qcom,tvm-include-reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mdss_mdp_vote_clk>, + <&clock_mmss clk_smmu_mdp_axi_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_mdss_vsync_clk>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "iommu_clk", + "mmagic_clk", + "vsync_clk"; + clock-rate = <0>, <0>, <0>; + clock-max-rate= <0 320000000 0>; + qcom,hw-fence-sw-version = <0x1>; + clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; + mmagic-supply = <&gdsc_mmagic_mdss>; + vdd-supply = <&gdsc_mdss>; + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mdp_smmu 0>; + #power-domain-cells = <0>; + + qcom,sde-hw-version = <0x70000000>; + qcom,sde-emulated-env; + qcom,sde-off = <0x1000>; + qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + qcom,sde-mixer-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,sde-mixer-display-pref = "primary", "none", + "none", "none"; + qcom,sde-mixer-cwb-pref = "none", "none", + "cwb", "none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-off = <0x00055000 0x00057000>; + qcom,sde-dspp-ad-off = <0x24000 0x22800>; + qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-min-region-width = <20>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-wb-off = <0x00066000>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + qcom,sde-pp-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cdm-off = <0x0007a200>; + qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-sspp-type = "vig", "vig", "vig", + "vig", "rgb", "rgb", + "rgb", "rgb", "dma", + "dma", "cursor", "cursor"; + + qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 + 0x0000b000 0x00015000 0x00017000 + 0x00019000 0x0001b000 0x00025000 + 0x00027000 0x00035000 0x00037000>; + + qcom,sde-sspp-xin-id = <0 4 8 + 12 1 5 + 9 13 2 + 10 7 7>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; + qcom,sde-highest-bank-bit = <0x7 0x2>; + qcom,sde-ubwc-version = <0x10000000>; + qcom,sde-ubwc-static = <0x100>; + qcom,sde-ubwc-swizzle = <0>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xd>; + qcom,sde-panic-per-pipe; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-sspp-src-size = <0x100>; + qcom,sde-mixer-size = <0x100>; + qcom,sde-ctl-size = <0x100>; + qcom,sde-dspp-top-size = <0xc>; + qcom,sde-dspp-size = <0x100>; + qcom,sde-intf-size = <0x100>; + qcom,sde-dsc-size = <0x100>; + qcom,sde-cdm-size = <0x100>; + qcom,sde-pp-size = <0x100>; + qcom,sde-wb-size = <0x100>; + qcom,sde-dest-scaler-top-size = <0xc>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-len = <0x100>; + qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-sspp-scale-size = <0x100>; + qcom,sde-mixer-blendstages = <0x8>; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-highest-bank-bit = <15>; + qcom,sde-has-mixer-gc; + qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; + qcom,fullsize-va-map; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-sspp-max-rects = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-smart-dma-priority = <0 0 0 0 + 0 0 0 0 + 0 0 + 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-te-off = <0x100>; + qcom,sde-te2-off = <0x100>; + qcom,sde-te-size = <0xffff>; + qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, + <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, + 0xffff0000 0xffff0000>; + qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, + <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, + 0xff>; + qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 + 0x00112234 0x45566777 0x00112236 0x67777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>, + <0x02344455 0x56667777 0x02366677 0x77777777 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + + qcom,sde-vbif-off = <0 0>; + qcom,sde-vbif-id = <0 1>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <16>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-max-bw-high-kbps = <9000000>; + qcom,sde-max-bw-low-kbps = <9000000>; + + qcom,sde-core-ib-ff = "1.1"; + qcom,sde-core-clk-ff = "1.0"; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-undersized-prefill-lines = <4>; + qcom,sde-xtra-prefill-lines = <5>; + qcom,sde-dest-scale-prefill-lines = <6>; + qcom,sde-macrotile-prefill-lines = <7>; + qcom,sde-yuv-nv12-prefill-lines = <8>; + qcom,sde-linear-prefill-lines = <9>; + qcom,sde-downscaling-prefill-lines = <10>; + qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 + 2400000 2400000 2400000 2400000>; + qcom,sde-amortizable-threshold = <11>; + qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-broadcast-disabled = <0>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0xa00>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + /* Offset from vig top, version of HSIC */ + qcom,sde-vig-hsic = <0x200 0x00010000>; + qcom,sde-vig-memcolor = <0x200 0x00010000>; + qcom,sde-vig-pcc = <0x1780 0x00010000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x800>; + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-rgb-blocks { + qcom,sde-rgb-scaler-off = <0x200>; + qcom,sde-rgb-scaler-size = <0x74>; + qcom,sde-rgb-pcc = <0x380 0x00010000>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00010000>; + qcom,sde-dspp-pcc = <0x1700 0x00010000>; + qcom,sde-dspp-gc = <0x17c0 0x00010000>; + qcom,sde-dspp-hsic = <0x0 0x00010000>; + qcom,sde-dspp-memcolor = <0x0 0x00010000>; + qcom,sde-dspp-sixzone = <0x0 0x00010000>; + qcom,sde-dspp-gamut = <0x1600 0x00010000>; + qcom,sde-dspp-dither = <0x0 0x00010000>; + qcom,sde-dspp-hist = <0x0 0x00010000>; + qcom,sde-dspp-vlut = <0x0 0x00010000>; + }; + + qcom,sde-mixer-blocks { + qcom,sde-mixer-gc = <0x3c0 0x00010000>; + }; + + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + + qcom,sde-inline-rotator = <&mdss_rotator 0>; + qcom,sde-inline-rot-xin = <10 11>; + qcom,sde-inline-rot-xin-type = "sspp", "wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + }; +... From d99e41b0f070cbd9c6326ac93bda867b08a09913 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 11 Mar 2024 22:18:31 +0800 Subject: [PATCH 088/242] ARM: dts: msm: add HDK variant DT support on sun target Add HDK variant DT support on sun target. Change-Id: I18be1e19013713ed0984e087d5f28638ab5c438c Signed-off-by: Lei Chen --- Kbuild | 3 +- display/dsi-panel-ext-bridge-1080p.dtsi | 51 +++++ display/sun-sde-display-common.dtsi | 12 + display/sun-sde-display-hdk-overlay.dts | 16 ++ display/sun-sde-display-hdk.dtsi | 281 ++++++++++++++++++++++++ 5 files changed, 362 insertions(+), 1 deletion(-) create mode 100644 display/dsi-panel-ext-bridge-1080p.dtsi create mode 100644 display/sun-sde-display-hdk-overlay.dts create mode 100644 display/sun-sde-display-hdk.dtsi diff --git a/Kbuild b/Kbuild index 1d451b47..7f851702 100644 --- a/Kbuild +++ b/Kbuild @@ -21,7 +21,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ display/sun-sde-display-rcm-v8-overlay.dtbo \ display/sun-sde-display-mtp-qmp1000-overlay.dtbo \ - display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo + display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo \ + display/sun-sde-display-hdk-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi new file mode 100644 index 00000000..0dc8ae2a --- /dev/null +++ b/display/dsi-panel-ext-bridge-1080p.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p { + qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-ext-bridge-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index ba5cc625..7d774992 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -31,6 +31,7 @@ #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" #include "sun-sde-display-pinctrl.dtsi" @@ -643,6 +644,17 @@ }; }; +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 1a 0c 00]; + qcom,display-topology = <1 0 1>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/sun-sde-display-hdk-overlay.dts b/display/sun-sde-display-hdk-overlay.dts new file mode 100644 index 00000000..ae5e0e66 --- /dev/null +++ b/display/sun-sde-display-hdk-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-hdk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SunP QRD HDK"; + compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk"; + qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>; + qcom,board-id = <0x1001f 0>; +}; diff --git a/display/sun-sde-display-hdk.dtsi b/display/sun-sde-display-hdk.dtsi new file mode 100644 index 00000000..030d0f7a --- /dev/null +++ b/display/sun-sde-display-hdk.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&tlmm { + lt9611_pins: lt9611_pins { + mux { + pins = "gpio69", "gpio60", "gpio214", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio60", "gpio214", "gpio83"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; +}; + +&qupv3_se5_i2c { + status = "ok"; + + lt9611: lt,lt9611@2b { + compatible = "lt,lt9611uxc"; + reg = <0x2b>; + interrupt-parent = <&tlmm>; + interrupts = <44 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 69 0x0>; + lt,reset-gpio = <&tlmm 60 0x0>; + lt,hdmi-3p3-en = <&tlmm 214 0x0>; + lt,hdmi-1p2-en = <&tlmm 83 0x0>; + lt,non-pluggable; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_pins>; + + lt,preferred-mode = "1920x1080"; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-clock-in-khz = <148500>; + }; + + lt,customize-mode-id@1 { + lt,mode-h-active = <3840>; + lt,mode-h-front-porch = <176>; + lt,mode-h-pulse-width = <88>; + lt,mode-h-back-porch = <400>; + lt,mode-h-active-high; + lt,mode-v-active = <2160>; + lt,mode-v-front-porch = <8>; + lt,mode-v-pulse-width = <10>; + lt,mode-v-back-porch = <72>; + lt,mode-v-active-high; + lt,mode-clock-in-khz = <608040>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in_0: endpoint { + remote-endpoint = <&ext_dsi_0_out>; + }; + }; + }; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_0_out: endpoint { + remote-endpoint = <<9611_in_0>; + }; + }; + }; +}; + +&battery_charger { + qcom,display-panels = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video>; +}; From bc2bc865318635ff0dfe70d4ebf6a351444a3a15 Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Wed, 20 Mar 2024 15:37:12 -0400 Subject: [PATCH 089/242] ARM: dts: msm: add package ID to msm-IDs for sun target Add additional device trees and msm-IDs to support an additional package ID. Also update board id for QMP1000 V6 variant on MTP for sun target. Change-Id: Ic6287bc0052cb44321674e16c74631c8a75f2aef Signed-off-by: Jayasri Sampath Kumaran --- Kbuild | 3 ++- display/sun-sde-display-atp-overlay.dts | 2 +- display/sun-sde-display-cdp-kiwi-overlay.dts | 4 +++- .../sun-sde-display-cdp-kiwi-v8-overlay.dts | 6 ++++-- display/sun-sde-display-cdp-nfc-overlay.dts | 6 ++++-- ...sun-sde-display-cdp-no-display-overlay.dts | 19 +++++++++++++++++++ display/sun-sde-display-cdp-no-display.dtsi | 15 +++++++++++++++ display/sun-sde-display-cdp-overlay.dts | 6 ++++-- display/sun-sde-display-cdp-v8-overlay.dts | 6 ++++-- display/sun-sde-display-mtp-3-5mm-overlay.dts | 4 +++- display/sun-sde-display-mtp-kiwi-overlay.dts | 4 +++- .../sun-sde-display-mtp-kiwi-v8-overlay.dts | 6 ++++-- display/sun-sde-display-mtp-nfc-overlay.dts | 6 ++++-- display/sun-sde-display-mtp-overlay.dts | 4 +++- .../sun-sde-display-mtp-qmp1000-overlay.dts | 6 ++++-- ...sun-sde-display-mtp-qmp1000-v8-overlay.dts | 4 +++- display/sun-sde-display-mtp-v8-overlay.dts | 6 ++++-- display/sun-sde-display-qrd-sku1-overlay.dts | 6 ++++-- .../sun-sde-display-qrd-sku1-v8-overlay.dts | 6 ++++-- .../sun-sde-display-qrd-sku2-v8-overlay.dts | 6 ++++-- display/sun-sde-display-rcm-kiwi-overlay.dts | 2 +- .../sun-sde-display-rcm-kiwi-v8-overlay.dts | 2 +- display/sun-sde-display-rcm-overlay.dts | 4 ++-- display/sun-sde-display-rcm-v8-overlay.dts | 2 +- 24 files changed, 101 insertions(+), 34 deletions(-) create mode 100644 display/sun-sde-display-cdp-no-display-overlay.dts create mode 100644 display/sun-sde-display-cdp-no-display.dtsi diff --git a/Kbuild b/Kbuild index 7f851702..1e85878a 100644 --- a/Kbuild +++ b/Kbuild @@ -22,7 +22,8 @@ dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ display/sun-sde-display-rcm-v8-overlay.dtbo \ display/sun-sde-display-mtp-qmp1000-overlay.dtbo \ display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo \ - display/sun-sde-display-hdk-overlay.dtbo + display/sun-sde-display-hdk-overlay.dtbo \ + display/sun-sde-display-cdp-no-display-overlay.dtbo else dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts index d3b24f2d..7f336bb0 100644 --- a/display/sun-sde-display-atp-overlay.dts +++ b/display/sun-sde-display-atp-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun ATP"; compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; qcom,board-id = <0x10021 0>; }; diff --git a/display/sun-sde-display-cdp-kiwi-overlay.dts b/display/sun-sde-display-cdp-kiwi-overlay.dts index 4ba523d6..0cb09597 100644 --- a/display/sun-sde-display-cdp-kiwi-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x20001 0>; }; diff --git a/display/sun-sde-display-cdp-kiwi-v8-overlay.dts b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts index fba63430..d65e13c6 100644 --- a/display/sun-sde-display-cdp-kiwi-v8-overlay.dts +++ b/display/sun-sde-display-cdp-kiwi-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x60001 0>; }; diff --git a/display/sun-sde-display-cdp-nfc-overlay.dts b/display/sun-sde-display-cdp-nfc-overlay.dts index f9aba3ab..2dc93aca 100644 --- a/display/sun-sde-display-cdp-nfc-overlay.dts +++ b/display/sun-sde-display-cdp-nfc-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x40001 0>; }; diff --git a/display/sun-sde-display-cdp-no-display-overlay.dts b/display/sun-sde-display-cdp-no-display-overlay.dts new file mode 100644 index 00000000..59087574 --- /dev/null +++ b/display/sun-sde-display-cdp-no-display-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp-no-display.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP No Display"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x30001 0>; +}; diff --git a/display/sun-sde-display-cdp-no-display.dtsi b/display/sun-sde-display-cdp-no-display.dtsi new file mode 100644 index 00000000..c9bc5c6d --- /dev/null +++ b/display/sun-sde-display-cdp-no-display.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sim_vid>; +}; diff --git a/display/sun-sde-display-cdp-overlay.dts b/display/sun-sde-display-cdp-overlay.dts index a3b29d3c..790386a1 100644 --- a/display/sun-sde-display-cdp-overlay.dts +++ b/display/sun-sde-display-cdp-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun CDP"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <1 0>; }; diff --git a/display/sun-sde-display-cdp-v8-overlay.dts b/display/sun-sde-display-cdp-v8-overlay.dts index dee0d9e7..36812b46 100644 --- a/display/sun-sde-display-cdp-v8-overlay.dts +++ b/display/sun-sde-display-cdp-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid"; compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x50001 0>; }; diff --git a/display/sun-sde-display-mtp-3-5mm-overlay.dts b/display/sun-sde-display-mtp-3-5mm-overlay.dts index e7b19c30..8b6c2343 100644 --- a/display/sun-sde-display-mtp-3-5mm-overlay.dts +++ b/display/sun-sde-display-mtp-3-5mm-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x60008 0>; }; diff --git a/display/sun-sde-display-mtp-kiwi-overlay.dts b/display/sun-sde-display-mtp-kiwi-overlay.dts index 7dd3d0f1..3d8cdcab 100644 --- a/display/sun-sde-display-mtp-kiwi-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x20008 0>; }; diff --git a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts index c354a996..982183cb 100644 --- a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x50008 0>; }; diff --git a/display/sun-sde-display-mtp-nfc-overlay.dts b/display/sun-sde-display-mtp-nfc-overlay.dts index 544c30fe..8792479e 100644 --- a/display/sun-sde-display-mtp-nfc-overlay.dts +++ b/display/sun-sde-display-mtp-nfc-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x30008 0>; }; diff --git a/display/sun-sde-display-mtp-overlay.dts b/display/sun-sde-display-mtp-overlay.dts index ba89d90c..ea229825 100644 --- a/display/sun-sde-display-mtp-overlay.dts +++ b/display/sun-sde-display-mtp-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <8 0>; }; diff --git a/display/sun-sde-display-mtp-qmp1000-overlay.dts b/display/sun-sde-display-mtp-qmp1000-overlay.dts index 00e92d1b..da5a314a 100644 --- a/display/sun-sde-display-mtp-qmp1000-overlay.dts +++ b/display/sun-sde-display-mtp-qmp1000-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP QMP1000"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; - qcom,board-id = <0x10108 0>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x108 0>; }; diff --git a/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts index ce16eb03..52432f90 100644 --- a/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts +++ b/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x40108 0>; }; diff --git a/display/sun-sde-display-mtp-v8-overlay.dts b/display/sun-sde-display-mtp-v8-overlay.dts index 3cfae533..6efc5290 100644 --- a/display/sun-sde-display-mtp-v8-overlay.dts +++ b/display/sun-sde-display-mtp-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid"; compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x40008 0>; }; diff --git a/display/sun-sde-display-qrd-sku1-overlay.dts b/display/sun-sde-display-qrd-sku1-overlay.dts index 2479ab77..c82f0229 100644 --- a/display/sun-sde-display-qrd-sku1-overlay.dts +++ b/display/sun-sde-display-qrd-sku1-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", "qcom,qrd"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x1000B 0>; }; diff --git a/display/sun-sde-display-qrd-sku1-v8-overlay.dts b/display/sun-sde-display-qrd-sku1-v8-overlay.dts index 4780320d..5b98bf36 100644 --- a/display/sun-sde-display-qrd-sku1-v8-overlay.dts +++ b/display/sun-sde-display-qrd-sku1-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", "qcom,qrd"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x3000B 0>; }; diff --git a/display/sun-sde-display-qrd-sku2-v8-overlay.dts b/display/sun-sde-display-qrd-sku2-v8-overlay.dts index 0820a163..e38db838 100644 --- a/display/sun-sde-display-qrd-sku2-v8-overlay.dts +++ b/display/sun-sde-display-qrd-sku2-v8-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -12,6 +12,8 @@ model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid"; compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", "qcom,qrd"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x2000B 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts index 21abbbbf..1c8b7c19 100644 --- a/display/sun-sde-display-rcm-kiwi-overlay.dts +++ b/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; qcom,board-id = <0x40015 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts index 18bdb0e6..a331b956 100644 --- a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts +++ b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; qcom,board-id = <0x20015 0>; }; diff --git a/display/sun-sde-display-rcm-overlay.dts b/display/sun-sde-display-rcm-overlay.dts index 4236e89b..6a5c7e1d 100644 --- a/display/sun-sde-display-rcm-overlay.dts +++ b/display/sun-sde-display-rcm-overlay.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; qcom,board-id = <0x15 0>; }; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts index 1c7308f2..e69e5198 100644 --- a/display/sun-sde-display-rcm-v8-overlay.dts +++ b/display/sun-sde-display-rcm-v8-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; qcom,board-id = <0x30015 0>; }; From 2a10b6cef34774f90e086ad0de30fbff8fceb091 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Thu, 4 Apr 2024 12:18:07 -0700 Subject: [PATCH 090/242] ARM: dts: msm: move MDSS GDSC to genPD on sun target Move the MDSS GDSC from regulator to power-domain on sun target. This will align with upstream usage. Change-Id: I8e5e3330fa0d13d496336f82d3eaee44c921f903 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18a66616..d19c58d5 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -244,7 +244,7 @@ "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", "qcom,sde-data-bus-sw-0"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; }; }; From b9fe27e94b0a5345f02ca75e59de035f90580808 Mon Sep 17 00:00:00 2001 From: Anjaneya Prasad Musunuri Date: Tue, 2 Apr 2024 12:03:00 +0530 Subject: [PATCH 091/242] Revert "ARM: dts: msm: introduce disp cc memory region" This reverts commit 33797c66a4c1382550d47480cb1d04fe7b5effe7. Reason for revert: retention to be handled through clock api. Change-Id: Ib7e54924779e78f839a80e91342344c28b877b0c Signed-off-by: Anjaneya Prasad Musunuri --- display/sun-sde-common.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index aabd1a98..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -13,13 +13,11 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>, - <0x0af08000 0x24>; + <0x400000 0x2000>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg", - "disp_cc"; + "ipcc_reg"; /* interrupt config */ interrupts = ; From daf6614ab6be7dfeb48b497d44de89b6e0bed1d9 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Sat, 6 Apr 2024 22:24:12 +0800 Subject: [PATCH 092/242] ARM: dts: msm: add FHD+ mode for csot panel This change add a mode with FHD+ resolution for csot panel. Change-Id: I72c5efc4159fb0ed99fcaa5fd93069601993d598 Signed-off-by: Jinfeng Gu --- .../dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 552 ++++++++++++++++++ .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 107 +--- display/sun-sde-display-cdp.dtsi | 16 +- display/sun-sde-display-common.dtsi | 66 ++- display/sun-sde-display-mtp.dtsi | 13 +- display/sun-sde-display.dtsi | 36 +- 6 files changed, 673 insertions(+), 117 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 00000000..f93d1a07 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_fhd_plus_cmd: qcom,mdss_dsi_nt37801_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled fhd plus cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0 + 39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0 + 39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0 + 39 01 00 00 00 00 02 03 00 + 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 f2 + 00 02 52 03 71 00 07 03 14 02 8b 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 FB 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 32 d2 + 00 02 25 04 a7 00 07 02 20 02 09 10 + f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 32 d2 + 00 02 25 04 a7 00 07 02 20 02 09 10 + f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 32 d2 + 00 02 25 04 a7 00 07 02 20 02 09 10 + f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 753f24b1..185acbbf 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -130,93 +130,6 @@ timing@1 { cell-index = <1>; - qcom,mdss-dsi-panel-framerate = <120>; - qcom,mdss-dsi-panel-width = <1080>; - qcom,mdss-dsi-panel-height = <2400>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <20>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <18>; - qcom,mdss-dsi-v-front-porch = <20>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 05 2A 00 00 04 37 - 39 01 00 00 00 00 05 2B 00 00 09 5F - 39 01 00 00 00 00 02 8F 01 - 39 01 00 00 00 00 02 2f 00 - 39 01 00 00 00 00 02 26 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 06 c0 54 c0 00 21 43 - 39 01 00 00 00 00 06 f0 55 aa 52 08 02 - 39 01 00 00 00 00 02 cc 30 - 39 01 00 00 00 00 02 ce 01 - 39 01 00 00 20 00 02 cc 00 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 06 F0 55 AA 52 08 01 - 39 01 00 00 00 00 02 6F 01 - 39 01 00 00 00 00 04 C5 0B 0B 0B - 39 01 00 00 00 00 05 FF AA 55 A5 80 - 39 01 00 00 00 00 02 6F 02 - 39 01 00 00 00 00 02 F5 10 - 39 01 00 00 00 00 02 6F 1B - 39 01 00 00 00 00 02 F4 55 - 39 01 00 00 00 00 02 6F 18 - 39 01 00 00 00 00 02 F8 19 - 39 01 00 00 00 00 02 6F 0F - 39 01 00 00 00 00 02 FC 00 - 39 01 00 00 00 00 05 2A 00 00 04 37 - 39 01 00 00 00 00 05 2B 00 00 09 5F - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0 - 39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0 - 39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0 - 39 01 00 00 00 00 02 03 00 - 39 01 00 00 00 00 02 8F 01 - 39 01 00 00 00 00 02 6F 06 - 39 01 00 00 00 00 02 F3 DC - 39 01 00 00 00 00 02 26 00 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 3B 00 18 00 10 - 39 01 00 00 00 00 02 53 20 - 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF - 39 01 00 00 00 00 02 5A 01 - 39 01 00 00 00 00 02 5F 00 - 39 01 00 00 00 00 02 9C 01 - 05 01 00 00 00 00 01 2C - 39 01 00 00 00 00 02 2F 00 - - 05 01 00 00 78 00 01 11 - 05 01 00 00 14 00 01 29 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <540>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@2 { - cell-index = <2>; qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; @@ -310,8 +223,8 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@3 { - cell-index = <3>; + timing@2 { + cell-index = <2>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; @@ -417,8 +330,8 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@4 { - cell-index = <4>; + timing@3 { + cell-index = <3>; qcom,mdss-dsi-panel-framerate = <40>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; @@ -524,8 +437,8 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@5 { - cell-index = <5>; + timing@4 { + cell-index = <4>; qcom,mdss-dsi-panel-framerate = <30>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; @@ -631,8 +544,8 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@6 { - cell-index = <6>; + timing@5 { + cell-index = <5>; qcom,mdss-dsi-panel-framerate = <24>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; @@ -738,8 +651,8 @@ qcom,mdss-dsc-block-prediction-enable; }; - timing@7 { - cell-index = <7>; + timing@6 { + cell-index = <6>; qcom,mdss-dsi-panel-framerate = <20>; qcom,mdss-dsi-panel-width = <1440>; qcom,mdss-dsi-panel-height = <3200>; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 3004b6c7..7bd984d2 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -126,6 +126,19 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -239,7 +252,8 @@ &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd - &dsi_nt37801_amoled_qsync_video>; + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 7d774992..f37ea9a0 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -14,6 +14,7 @@ #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -373,48 +374,41 @@ }; timing@1 { - qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a - 0b 0a 02 04 00 21 0f]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 08 08 08 02 04 1a 0d]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - timing@3 { + timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06 06 06 06 02 04 13 0b]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - timing@4 { + timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04 04 04 03 02 04 0e 09]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - timing@5 { + timing@4 { qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 03 03 02 02 04 0c 08]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - timing@6 { + timing@5 { qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 03 03 02 02 04 0b 08]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; - timing@7 { + timing@6 { qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 02 02 02 02 04 0a 07]; qcom,display-topology = <2 2 1>; @@ -644,6 +638,54 @@ }; }; +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_ext_bridge_1080p { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 17cbb9cc..14343117 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -111,6 +111,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -223,7 +233,8 @@ &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd - &dsi_nt37801_amoled_qsync_video>; + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd>; }; }; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index ad74108e..5fcf1262 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -174,7 +174,7 @@ timing@1 { qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; timing@2 { @@ -201,11 +201,6 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; - - timing@7 { - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 720 40 1440 40>; - }; }; }; @@ -228,6 +223,35 @@ }; }; +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; }; From 06f2830f83dd30b8b7eb685c3530d8171938e7c5 Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Mon, 8 Apr 2024 17:23:27 +0800 Subject: [PATCH 093/242] ARM: dts: msm: add HDK touch support on sun target Add touch node for HDK on sun target. Change-Id: I005e861afaf866b57eef7de8fc640d255adc5ec9 Signed-off-by: Rui Chen --- display/sun-sde-display-hdk.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/display/sun-sde-display-hdk.dtsi b/display/sun-sde-display-hdk.dtsi index 030d0f7a..a5868788 100644 --- a/display/sun-sde-display-hdk.dtsi +++ b/display/sun-sde-display-hdk.dtsi @@ -279,3 +279,13 @@ &dsi_vtdr6130_amoled_120hz_cmd &dsi_vtdr6130_amoled_120hz_video>; }; + +&qupv3_se4_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_ext_bridge_1080p>; + }; +}; From 8e290407c530ff9231b0ec9cc598985336277741 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Tue, 2 Apr 2024 08:52:34 +0800 Subject: [PATCH 094/242] ARM: dts: msm: update pps for csot panel This change update pps from init code for csot panel. Change-Id: Ib1790e96dde6e72afaa060e8796337176dab6834 Signed-off-by: Jinfeng Gu --- .../dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 52 +++++++++---- ...-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 33 +++++--- .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 77 ++++++++++++++----- ...anel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 11 ++- ...dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 11 ++- ...-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 11 ++- ...panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 11 ++- ...t37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 11 ++- ...nel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 11 ++- 9 files changed, 165 insertions(+), 63 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index f93d1a07..b131fd51 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -88,8 +88,15 @@ 39 01 00 00 00 00 02 FC 00 39 01 00 00 00 00 05 2A 00 00 04 37 39 01 00 00 00 00 05 2B 00 00 09 5F - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 00 02 86 04 3A 00 0A 02 AB 01 E9 10 F0 + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0 39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0 39 01 00 00 00 00 02 03 00 @@ -178,13 +185,13 @@ 39 01 00 00 00 00 02 FC 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 5f - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 f2 - 00 02 52 03 71 00 07 03 14 02 8b 10 + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 f0 39 01 00 00 00 00 05 ff aa 55 a5 81 39 01 00 00 00 00 02 6f 23 - 39 01 00 00 00 00 15 FB 00 01 00 11 33 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 33 33 55 57 d0 00 00 44 56 77 78 9a bc dd f0 39 01 00 00 00 00 02 35 00 @@ -281,10 +288,15 @@ 39 01 00 00 00 00 02 FC 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 5f - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 32 d2 - 00 02 25 04 a7 00 07 02 20 02 09 10 + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -388,10 +400,15 @@ 39 01 00 00 00 00 02 FC 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 5f - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 32 d2 - 00 02 25 04 a7 00 07 02 20 02 09 10 + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -495,10 +512,15 @@ 39 01 00 00 00 00 02 FC 00 39 01 00 00 00 00 05 2a 00 00 04 37 39 01 00 00 00 00 05 2b 00 00 09 5f - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 32 d2 - 00 02 25 04 a7 00 07 02 20 02 09 10 + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 1a5f75cf..989253bd 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -85,9 +85,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -172,9 +177,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -274,9 +284,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 185acbbf..1b86e3d2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -89,9 +89,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -176,9 +181,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -278,9 +288,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -385,9 +400,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -492,9 +512,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -599,9 +624,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 @@ -706,9 +736,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index d9c48cd4..ed5a1961 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -75,9 +75,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 8a36fe29..483359ec 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -77,9 +77,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index be7213c7..979693ae 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -75,9 +75,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index acc300b4..841f1ee0 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -77,9 +77,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 7f33dd6f..af59a3fb 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -77,9 +77,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 7c3eadd2..7da07c60 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -79,9 +79,14 @@ 39 01 00 00 00 00 05 2A 00 00 05 9F 39 01 00 00 00 00 05 2B 00 00 0C 7F 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 D2 - 00 02 86 04 3A 00 0A 02 AB 01 E9 10 - F0 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 39 01 00 00 00 00 02 6F 06 39 01 00 00 00 00 02 F3 DC 39 01 00 00 00 00 02 26 00 From 6f466e30c0efbe689ba8d930b54bdcf0a28ec547 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 15 Apr 2024 11:41:18 -0700 Subject: [PATCH 095/242] Revert "ARM: dts: msm: move MDSS GDSC to genPD on sun target" This reverts commit 2a10b6cef34774f90e086ad0de30fbff8fceb091. Remove genPD changes part of cesta node. Change-Id: I66af06ccaec34319f4c6a7d888649c202e8fda28 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index d19c58d5..18a66616 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -244,7 +244,7 @@ "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", "qcom,sde-data-bus-sw-0"; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; }; }; From 60ea2afaaa84ee81f86091b6b44b10420e5a90cc Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Mon, 15 Apr 2024 11:41:36 -0700 Subject: [PATCH 096/242] Revert "ARM: dts: msm: enable display cesta on sun target" This reverts commit 5b87ecc6bdb521086ea800a484dece10e2173cd2. Disable display cesta until reboot recovery issue is fixed. Change-Id: Iedc5fc570f753532e5f936488d8bcc14a6889be7 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-display.dtsi | 3 +- display/sun-sde.dtsi | 64 ++++++++++------------------------ display/trustedvm-sun-sde.dtsi | 8 ----- 3 files changed, 19 insertions(+), 56 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 5fcf1262..57f6f526 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -132,8 +132,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 - &sde_dp &sde_cesta>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18a66616..61a0bb97 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -204,63 +204,26 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; - - sde_cesta: qcom,sde_cesta@0x0af30000 { - cell-index = <0>; - compatible = "qcom,sde-cesta"; - reg = <0xaf30000 0x60>, - <0xaf31000 0x30>, - <0xaf32000 0x30>, - <0xaf33000 0x30>, - <0xaf34000 0x30>, - <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; - - clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; - - clock-names = "branch_clk", "core_clk"; - clock-rate = <575000000 575000000>; - clock-max-rate = <575000000 575000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; - - interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, - <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, - <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, - <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, - <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, - <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 - &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, - <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 - &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; - interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", - "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", - "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", - "qcom,sde-data-bus-sw-0"; - - vdd-supply = <&disp_cc_mdss_core_gdsc>; - }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - - clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk"; - clock-rate = <0 0 19200000 575000000>; - clock-max-rate = <0 0 19200000 575000000>; + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 575000000 575000000 19200000 575000000>; + clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; + clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; qcom,hw-fence-sw-version = <0x1>; + vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ; @@ -299,6 +262,15 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; + + qcom,platform-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; }; }; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 93aa250c..22855dd8 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,14 +37,6 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0xaf30000 0x60>, - <0xaf31000 0x30>, - <0xaf32000 0x30>, - <0xaf33000 0x30>, - <0xaf34000 0x30>, - <0xaf35000 0x30>, - <0xaf36000 0x30>; - qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 667abb6151e112311e07fdb76b8e09dfb5d29d2a Mon Sep 17 00:00:00 2001 From: Manoj Kumar AVM Date: Mon, 15 Apr 2024 20:03:26 -0700 Subject: [PATCH 097/242] ARM: dts: msm: enable display cesta on sun target This reverts commit 60ea2afaaa84ee81f86091b6b44b10420e5a90cc. Change-Id: I89e385640913e1d05825e7f153ec77d9187b0be8 Signed-off-by: Manoj Kumar AVM --- display/sun-sde-display.dtsi | 3 +- display/sun-sde.dtsi | 64 ++++++++++++++++++++++++---------- display/trustedvm-sun-sde.dtsi | 8 +++++ 3 files changed, 56 insertions(+), 19 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 57f6f526..5fcf1262 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -132,7 +132,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_dp &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 61a0bb97..18a66616 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -204,26 +204,63 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <575000000 575000000>; + clock-max-rate = <575000000 575000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + vdd-supply = <&disp_cc_mdss_core_gdsc>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; - clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 575000000 575000000 19200000 575000000>; - clock-max-rate = <0 0 575000000 575000000 19200000 575000000>; - clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + + clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 575000000>; + clock-max-rate = <0 0 19200000 575000000>; qcom,hw-fence-sw-version = <0x1>; - vdd-supply = <&disp_cc_mdss_core_gdsc>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ; @@ -262,15 +299,6 @@ qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; - - qcom,platform-supply-entry@1 { - reg = <1>; - qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <0>; - qcom,supply-max-voltage = <0>; - qcom,supply-enable-load = <0>; - qcom,supply-disable-load = <0>; - }; }; }; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 22855dd8..93aa250c 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,6 +37,14 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,tvm-include-reg = <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 598a26d45087475d1701d708011dfd9ca3cb0c30 Mon Sep 17 00:00:00 2001 From: Manoj Kumar AVM Date: Mon, 15 Apr 2024 20:04:15 -0700 Subject: [PATCH 098/242] ARM: dts: msm: move MDSS GDSC to genPD on sun target This reverts commit 6f466e30c0efbe689ba8d930b54bdcf0a28ec547. Change-Id: I54c44106ccd36145f1b327d4777c5213a1a62fd3 Signed-off-by: Manoj Kumar AVM --- display/sun-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 18a66616..d19c58d5 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -244,7 +244,7 @@ "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", "qcom,sde-data-bus-sw-0"; - vdd-supply = <&disp_cc_mdss_core_gdsc>; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; }; }; From bcf7659cfa0319cf55b39f670dd5d20f8049fc50 Mon Sep 17 00:00:00 2001 From: Bruce Levy Date: Tue, 16 Apr 2024 15:51:13 -0700 Subject: [PATCH 099/242] Revert "ARM: dts: msm: add disp cc address in pakala tvm device tree" This reverts commit c136e385826a22185422dfae47238b65a5fdc285. Change-Id: I19875c8826173b70530afa0fc641b73f2c2d3f7d Signed-off-by: Bruce Levy --- display/trustedvm-sun-sde.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 6aaf4850..22855dd8 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -36,7 +36,6 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0x0af08000 0x24>; qcom,sde-hw-version =<0xC0000000>; From f955236d5d74d1fea1c18b6bade3b5b1e5e3fc18 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 17 Apr 2024 21:51:46 +0800 Subject: [PATCH 100/242] ARM: dts: msm: update clock rate for csot panel cphy cmd mode at 60Hz This change update clock rate for csot panel cphy cmd mode at 60Hz. Change-Id: Iee432582a29304799b9e6a93f3d8e7b8ff1fa2fe Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 +- display/sun-sde-display-common.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 989253bd..427764d1 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -249,7 +249,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <808730000>; + qcom,mdss-dsi-panel-clockrate = <707640000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index f37ea9a0..b5717d38 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -465,8 +465,8 @@ }; timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 1e 17 03 - 19 03 02 04 00 00 00]; + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; From d441bdbfff1e83351188e3c94d4b895c05b7ece0 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Wed, 24 Apr 2024 13:29:33 -0700 Subject: [PATCH 101/242] ARM: dts: msm: disable destination scaler feature on sun target Disable destination scaler feature temporarily to avoid DPU hang issue due to concurrency with other features. Change-Id: Ia63bb6da80465ba9b076a2e2844242bcb72f1319 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 7e0b89cc..c85d6519 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -176,7 +176,6 @@ qcom,sde-has-src-split; qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; - qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-bw-low-kbps = <18900000>; From 8e2c3e1a7e37e5ba7c9fac8c3112089a5363618f Mon Sep 17 00:00:00 2001 From: Jayasri Sampath Kumaran Date: Mon, 29 Apr 2024 10:04:40 -0400 Subject: [PATCH 102/242] ARM: dts: msm: update address ranges to avoid unsecure context bank for sun target Update unsecure context bank to exclude memory region allocated to display splash, ramdump and demura. Change-Id: I9a3d00c3943b2a5c94914856f498cb62a7fc4dfa Signed-off-by: Jayasri Sampath Kumaran --- display/sun-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index d19c58d5..3b69a237 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -184,6 +184,8 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, <&smmu_sde_unsec 0xd4e23000 0x002dd000>, + <&smmu_sde_unsec 0xd2880000 0x05780000>, + <&smmu_sde_unsec 0xa3500000 0x02c80000>, <&smmu_sde_unsec 0xfc800000 0x02b00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 49ae7eacf316012fb6ed5fba3d1a0035de097666 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Fri, 26 Apr 2024 14:22:23 +0800 Subject: [PATCH 103/242] ARM: dts: msm: add new msm-IDs support on sun HDK Add new msm-IDs support on sun HDK. Change-Id: I520eb6be7ece19ce521f5fd7580cc30c72ee87a1 Signed-off-by: Lei Chen --- display/sun-sde-display-hdk-overlay.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-hdk-overlay.dts b/display/sun-sde-display-hdk-overlay.dts index ae5e0e66..85200310 100644 --- a/display/sun-sde-display-hdk-overlay.dts +++ b/display/sun-sde-display-hdk-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. SunP QRD HDK"; compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk"; - qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>; + qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x1001f 0>; }; From 0233eb0290bb9a4dd42dc6e6a43572a250c19c5c Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Tue, 14 May 2024 01:41:24 -0700 Subject: [PATCH 104/242] Revert "ARM: dts: msm: disable destination scaler feature on sun target" This reverts commit d441bdbfff1e83351188e3c94d4b895c05b7ece0. Change-Id: I16168752b552fdee001e66ff13862f4ffd9d0c73 Signed-off-by: Linux Image Build Automation --- display/sun-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index c85d6519..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -176,6 +176,7 @@ qcom,sde-has-src-split; qcom,sde-pipe-order-version = <0x1>; qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; qcom,sde-max-trusted-vm-displays = <1>; qcom,sde-max-bw-low-kbps = <18900000>; From 121fe04261574f63234d354d2c032f943a343f39 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 30 Apr 2024 14:37:52 +0800 Subject: [PATCH 105/242] ARM: dts: msm: add secondary display support on NT37801 panel Add secondary display support on NT37801 panel for Sun QRD and MTP target. Change-Id: I2c8579f4343ae15109942e545e2f76e55aadf038 Signed-off-by: Lei Chen --- display/sun-sde-display-mtp.dtsi | 6 ++++++ display/sun-sde-display-qrd.dtsi | 12 ++++++++++++ 2 files changed, 18 insertions(+) diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 14343117..4641076d 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -43,22 +43,28 @@ &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_dsc_10b_cmd { diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index a7ae76f7..c1339749 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -43,42 +43,54 @@ &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_cmd_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_video_cphy { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; &dsi_nt37801_amoled_qsync_cmd_cphy { From 09992b738b4328c5ee9d17f7f7e515a5d343a73c Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 13 May 2024 17:24:10 +0800 Subject: [PATCH 106/242] ARM: dts: msm: update panel-roi-alignment for dsi_sim_cmd on sun target Update height alignments from 20 to 40 for HD 60FPS cmd mode to match DSC slice settings. The roi height and width alignment must be integral multiple of DSC slice height and width. Change-Id: I127af4c4e6a453757f60677bac787cd4bd4b6d07 Signed-off-by: Lei Chen --- display/sun-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 5fcf1262..4ca8588d 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -270,7 +270,7 @@ }; timing@3 { /* HD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <360 20 360 20 360 20>; + qcom,panel-roi-alignment = <360 40 360 40 360 40>; qcom,partial-update-enabled = "single_roi"; }; }; From fc3c848bb3fcf452dafbc4487b20ca6e7fd9ec75 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 22 May 2024 11:51:20 +0800 Subject: [PATCH 107/242] ARM: dts: msm: add scaling up code for FHD+ csot panel This change add scaling up code in on command for FHD+ csot panel. Change-Id: Idb98ba4080b7030c317b6530a06912baf432fc79 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index b131fd51..d6816370 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -203,6 +203,7 @@ 39 01 00 00 00 00 02 5F 00 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 39 01 00 00 00 00 02 2f 01 39 01 00 00 00 00 02 26 01 39 01 00 00 00 00 06 f0 55 aa 52 08 00 @@ -309,6 +310,7 @@ 39 01 00 00 00 00 02 5F 00 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 39 01 00 00 00 00 02 2f 00 39 01 00 00 00 00 02 26 01 39 01 00 00 00 00 02 5a 01 @@ -421,6 +423,7 @@ 39 01 00 00 00 00 02 5F 00 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 39 01 00 00 00 00 02 2f 00 39 01 00 00 00 00 02 26 01 39 01 00 00 00 00 02 5a 01 @@ -533,6 +536,7 @@ 39 01 00 00 00 00 02 5F 00 39 01 00 00 00 00 02 9C 01 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 39 01 00 00 00 00 02 2f 00 39 01 00 00 00 00 02 26 01 39 01 00 00 00 00 02 5a 01 From ffb6324600c4e8f04f1f8b8b841f5b502fcf1d2b Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 16 May 2024 09:15:03 +0800 Subject: [PATCH 108/242] ARM: dts: msm: update clock rate for csot panel cphy cmd mode This change increased clock rate with 3% config for cphy cmd mode. Change-Id: I3e89dd8596ac72712a4e4c38cb69249b6a815c47 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 427764d1..8030ebb2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -57,6 +57,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 @@ -149,6 +150,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <548200000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 01 @@ -249,7 +251,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <707640000>; + qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 From 2f83057496058650d5c55156d85bac495c7af861 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 16 May 2024 17:43:30 +0800 Subject: [PATCH 109/242] ARM: dts: msm: add NT37801 dphy mode with bypass DDIC SPR support This change add NT37801 dphy mode with bypass DDIC SPR support. Change-Id: Ie34c339d0406867ecc934e3ce55a19bb580d88ca Signed-off-by: Jinfeng Gu --- ...nel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 125 ++++++++++++++++++ ...l-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 124 +++++++++++++++++ display/sun-sde-display-cdp.dtsi | 30 ++++- display/sun-sde-display-common.dtsi | 42 ++++++ display/sun-sde-display-mtp.dtsi | 30 ++++- 5 files changed, 349 insertions(+), 2 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi new file mode 100644 index 00000000..260dc4a4 --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi new file mode 100644 index 00000000..212ad8ec --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_video_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 7bd984d2..638c2fcb 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -139,6 +139,32 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -253,7 +279,9 @@ &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video - &dsi_nt37801_amoled_fhd_plus_cmd>; + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index b5717d38..3af6915a 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -15,6 +15,8 @@ #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -686,6 +688,46 @@ }; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_ext_bridge_1080p { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,mdss-dsi-display-timings { diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 4641076d..a9814173 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -127,6 +127,32 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -240,7 +266,9 @@ &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video - &dsi_nt37801_amoled_fhd_plus_cmd>; + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; }; From 661ebda22d26a8435dee306e089a7ec30a0dcdb3 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 16 May 2024 09:15:03 +0800 Subject: [PATCH 110/242] ARM: dts: msm: update clock rate for cphy cmd mode at 120Hz & 90Hz This change updates clock rate for cphy cmd mode at 120Hz & 90Hz. Change-Id: I3e89dd8596ac72712a4e4c38cb69249b6a815c47 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 427764d1..ef282dd8 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -57,6 +57,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 @@ -149,6 +150,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <548200000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 01 From 2225cc899e3e7601c069b30b1ce965ce0f6b45f5 Mon Sep 17 00:00:00 2001 From: Yuchao Ma Date: Wed, 22 May 2024 13:48:24 +0800 Subject: [PATCH 111/242] ARM: dts: msm: Add pentile pack type for SPR on sun target This change adds pentile pack type for SPR on sun target. Change-Id: I9d1da6be1262d806e1e8f1820fd3b844d40cfbf3 Signed-off-by: Yuchao Ma --- .../dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 14 ++++++++++++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 14 ++++++++++++++ ...dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 14 ++++++++++++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 14 ++++++++++++++ 4 files changed, 56 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 427764d1..beef22f4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -38,6 +38,20 @@ qcom,mdss-dsi-te-using-te-pin; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 1b86e3d2..e2cd6e28 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -40,6 +40,20 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index ed5a1961..3015dcc5 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -28,6 +28,20 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 483359ec..27c0557b 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -33,6 +33,20 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "RG-BG Type A"; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From bfd823d9c5eec94083eeed4a31def80740bf3205 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 11 Mar 2024 17:01:48 -0700 Subject: [PATCH 112/242] ARM: dts: msm: add CSOT vid with SPR config Adds variant of CSOT panel with AP SPR in video mode. Change-Id: I01035e333822b37c4ebc5ab4cd1d728d0638e979 Signed-off-by: Kirill Shpin --- ...panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 134 ++++++++++++++++++ display/sun-sde-display-cdp.dtsi | 17 ++- display/sun-sde-display-common.dtsi | 21 +++ display/sun-sde-display-mtp.dtsi | 14 +- display/trustedvm-sun-sde-display-cdp.dtsi | 15 +- display/trustedvm-sun-sde-display-mtp.dtsi | 12 +- 6 files changed, 208 insertions(+), 5 deletions(-) create mode 100644 display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi new file mode 100644 index 00000000..f22f4d3a --- /dev/null +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_vid_spr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_spr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled vid mode dsi csot panel with DSC and AP SPR"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsc-version = <0x12>; + qcom,src-chroma-format = <1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 02 DE 00 + 39 01 00 00 00 00 02 6F 09 + 39 01 00 00 00 00 07 DE 10 34 25 30 14 25 + 39 01 00 00 00 00 05 FF AA 55 A5 81 + 39 01 00 00 00 00 02 6F 1D + 39 01 00 00 00 00 02 FB 6F + + 39 01 00 00 00 00 06 F0 55 AA 52 08 07 + 39 01 00 00 00 00 02 B0 24 + 39 01 00 00 00 00 02 03 10 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 7bd984d2..8b1db7f3 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -100,6 +100,19 @@ qcom,platform-sec-reset-gpio = <&tlmm 97 0>; }; +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + &dsi_nt37801_amoled_qsync_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -251,6 +264,7 @@ &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd>; @@ -264,6 +278,7 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index b5717d38..b9f0a674 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -10,6 +10,7 @@ #include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" #include "dsi-panel-nt37801-dsc-10bit-video.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" #include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" @@ -560,6 +561,26 @@ }; }; +&dsi_nt37801_amoled_vid_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_qsync_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index 4641076d..f5ca64b6 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -97,6 +97,16 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_qsync_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -238,6 +248,7 @@ &dsi_nt37801_amoled_dsc_10b_cmd &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr &dsi_nt37801_amoled_qsync_cmd &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd>; @@ -249,5 +260,6 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; }; diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 24679ff3..13d89f62 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -63,6 +63,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_vtdr6130_amoled_120hz_video { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -158,7 +167,8 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; }; }; @@ -169,6 +179,7 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; }; }; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index eda8e972..d762f789 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -32,6 +32,15 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -84,6 +93,7 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_dsc_10b_video - &dsi_nt37801_amoled_cmd_spr>; + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; }; }; From bdedd83bd977e020cda60f1cc913b9432829e335 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Thu, 4 Apr 2024 15:55:51 -0700 Subject: [PATCH 113/242] ARM: dts: msm: add esync pinctrl and clocks Adds pinctrl configuration to pass esync signal through from hw block to output pin. Also adds esync and oscillator clocks, and makes the DSI PLL clock available to parse for setting clock parent. Change-Id: I09ac2d1a334546452176285712d8c953f94aecf2 Signed-off-by: Kirill Shpin --- display/sun-sde-display-common.dtsi | 14 ++++---- display/sun-sde-display-pinctrl.dtsi | 54 ++++++++++++++++++++++++++++ display/sun-sde.dtsi | 14 ++++++-- 3 files changed, 74 insertions(+), 8 deletions(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index b5717d38..4ad8d613 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -128,9 +128,10 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi_active &sde_te_active>; - pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend>; + pinctrl-1 = <&sde_dsi_active &sde_te_active &sde_esync0_active>; + pinctrl-2 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend>; qcom,platform-te-gpio = <&tlmm 86 0>; qcom,panel-te-source = <0>; @@ -147,9 +148,10 @@ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; - pinctrl-names = "panel_active", "panel_suspend"; - pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; - pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active &sde_esync1_suspend>; + pinctrl-1 = <&sde_dsi1_active &sde_te1_active &sde_esync1_active>; + pinctrl-2 = <&sde_dsi1_suspend &sde_te1_suspend &sde_esync1_suspend>; qcom,platform-te-gpio = <&tlmm 87 0>; qcom,panel-te-source = <1>; diff --git a/display/sun-sde-display-pinctrl.dtsi b/display/sun-sde-display-pinctrl.dtsi index 7a7846df..8b9d0ff8 100644 --- a/display/sun-sde-display-pinctrl.dtsi +++ b/display/sun-sde-display-pinctrl.dtsi @@ -111,4 +111,58 @@ }; }; }; + + pmx_sde_esync: pmx_sde_esync { + sde_esync0_active: sde_esync0_active { + mux { + pins = "gpio88"; + function = "mdp_esync0_out"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync0_suspend: sde_esync0_suspend { + mux { + pins = "gpio88"; + function = "mdp_esync0_out"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync1_active: sde_esync1_active { + mux { + pins = "gpio100"; + function = "mdp_esync1_out"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync1_suspend: sde_esync1_suspend { + mux { + pins = "gpio100"; + function = "mdp_esync1_out"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 3b69a237..f5413498 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -312,10 +312,15 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&mdss_dsi_phy0 1>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK_SRC>, + <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi1 { @@ -326,10 +331,15 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&mdss_dsi_phy1 1>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK_SRC>, + <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi_phy0 { From d2aaaf9f4a60aade6db593a05a1207ccfc00f0f7 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Mon, 3 Jun 2024 16:27:20 -0700 Subject: [PATCH 114/242] Revert "ARM: dts: msm: update clock rate for cphy cmd mode at 120Hz & 90Hz" This reverts commit 661ebda22d26a8435dee306e089a7ec30a0dcdb3. Change-Id: I687b32224352e1561e1f4f022a903079701452f2 Signed-off-by: Linux Image Build Automation --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index ef282dd8..427764d1 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -57,7 +57,6 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 @@ -150,7 +149,6 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <548200000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 01 From a64265d79f9a9ec562afe841f4cff8616e9dd997 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 6 Jun 2024 14:55:56 +0800 Subject: [PATCH 115/242] ARM: dts: msm: enable partial update for spr cmd dphy mode This change enable partial update for spr cmd dphy mode. Change-Id: I4756cd2f2e64c69922018bae026a47ad00bc23f3 Signed-off-by: Jinfeng Gu --- display/sun-sde-display.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4ca8588d..4568ea85 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -252,6 +252,15 @@ }; }; +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + &dsi_sharp_4k_dsc_cmd { qcom,ulps-enabled; }; From dfe2218e1167f79309563a614bb0627b8a961afd Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Fri, 7 Jun 2024 16:58:37 +0800 Subject: [PATCH 116/242] bindings: Documentation: add flag for override rc_range_bpg_ofs Add "qcom,mdss-dsc-rc-override_v1" flag to enable override rc_range_bpg_ofs in sde_dsc_rc_range_bpg_override_v1. Change-Id: Ib889643b097dff81f2896afbde48e7273e46a097 Signed-off-by: Jinfeng Gu --- bindings/mdss-dsi-panel.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml index 54e88f3a..f085a963 100644 --- a/bindings/mdss-dsi-panel.yaml +++ b/bindings/mdss-dsi-panel.yaml @@ -1418,6 +1418,9 @@ properties: qcom,mdss-dsc-block-prediction-enable: description: A boolean value to enable/disable the block prediction at decoder. + qcom,mdss-dsc-rc-override_v1: + description: A boolean value to enable override rc_range_bpg_ofs in sde_dsc_rc_range_bpg_override_v1. + qcom,mdss-dsc-config-by-manufacture-cmd: description: > A boolean to indicates panel use manufacture command to setup pps @@ -1786,6 +1789,7 @@ examples: qcom,mdss-dsi-panel-prefill-lines = <0x10>; qcom,mdss-dsi-force-clock-lane-hs; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,adjust-timer-wakeup-ms = <1>; qcom,platform-reset-gpio = <&tlmm 0 0>; From b8a176c81de007f290fd065d6d424eee80ec2317 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 16 May 2024 09:15:03 +0800 Subject: [PATCH 117/242] ARM: dts: msm: update clock rate for csot panel cphy cmd mode This change increased clock rate with 3% config for cphy cmd mode. Change-Id: If8e7668a42e29f21a0f2cb2ef67fa60147c6786f Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 427764d1..8030ebb2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -57,6 +57,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 @@ -149,6 +150,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <548200000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 01 @@ -249,7 +251,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <707640000>; + qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 From fddd02548e7e893021b9b93a05bd6344a159ec63 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 5 Jun 2024 22:50:25 +0800 Subject: [PATCH 118/242] ARM: dts: msm: add the identification of rc_override_v1 This change adds the identification of rc_override_v1 and remove 24/20Hz for wqhd command dphy mode due to panel limitation. Change-Id: I6ec180fa5ffe25ca914ecd270bbe55c3a64e14d8 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 1 + .../dsi-panel-nt37801-dsc-10bit-video.dtsi | 1 + .../dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 + ...-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 3 + ...nel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 1 + ...i-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 1 + .../dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 229 +----------------- ...anel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 1 + ...l-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 1 + ...panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 1 + ...dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 1 + ...-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 1 + ...panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 1 + ...t37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 1 + ...nel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 1 + display/sun-sde-display-common.dtsi | 26 +- display/sun-sde-display.dtsi | 10 - 17 files changed, 31 insertions(+), 254 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index 499ea14e..aad5198e 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -109,6 +109,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index d7d968d6..79524689 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -106,6 +106,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index d6816370..e1c2f792 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -127,6 +127,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <540>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -227,6 +228,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <540>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -340,6 +342,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <540>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -453,6 +456,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <540>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -566,6 +570,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <540>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 8030ebb2..35f68861 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -125,6 +125,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -226,6 +227,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -338,6 +340,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index 260dc4a4..7b969aa8 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -113,6 +113,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 76401ecf..4ebc8416 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -120,6 +120,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 1b86e3d2..194b1126 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -125,6 +125,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -225,6 +226,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -337,6 +339,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -449,6 +452,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; @@ -561,230 +565,7 @@ "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@5 { - cell-index = <5>; - qcom,mdss-dsi-panel-framerate = <24>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <3200>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <20>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <18>; - qcom,mdss-dsi-v-front-porch = <20>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <1199900000>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 05 2a 00 00 05 9f - 39 01 00 00 00 00 05 2b 00 00 0c 7f - 39 01 00 00 00 00 02 8f 00 - 39 01 00 00 00 00 02 2f 00 - 39 01 00 00 00 00 02 26 01 - 39 01 00 00 00 00 02 5a 01 - 39 01 00 00 00 00 02 2f 30 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 02 6f 1c - 39 01 00 00 00 00 09 ba 91 04 04 00 01 - 04 04 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 06 c0 54 c0 00 21 43 - 39 01 00 00 00 00 06 f0 55 aa 52 08 02 - 39 01 00 00 00 00 02 cc 30 - 39 01 00 00 00 00 02 ce 01 - 39 01 00 00 20 00 02 cc 00 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 06 F0 55 AA 52 08 01 - 39 01 00 00 00 00 02 6F 01 - 39 01 00 00 00 00 04 C5 0B 0B 0B - 39 01 00 00 00 00 05 FF AA 55 A5 80 - 39 01 00 00 00 00 02 6F 02 - 39 01 00 00 00 00 02 F5 10 - 39 01 00 00 00 00 02 6F 1B - 39 01 00 00 00 00 02 F4 55 - 39 01 00 00 00 00 02 6F 18 - 39 01 00 00 00 00 02 F8 19 - 39 01 00 00 00 00 02 6F 0F - 39 01 00 00 00 00 02 FC 00 - 39 01 00 00 00 00 05 2A 00 00 05 9F - 39 01 00 00 00 00 05 2B 00 00 0C 7F - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 c2 - 00 02 68 04 6c 00 0a 02 77 01 e9 10 - f0 - 39 01 00 00 00 00 05 ff aa 55 a5 81 - 39 01 00 00 00 00 02 6f 23 - 39 01 00 00 00 00 15 fb 00 01 00 11 33 - 33 33 55 57 d0 00 00 44 56 77 78 9a - bc dd f0 - 39 01 00 00 00 00 02 6F 06 - 39 01 00 00 00 00 02 F3 DC - 39 01 00 00 00 00 02 26 00 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 3B 00 18 00 10 - 39 01 00 00 00 00 02 53 20 - 39 01 00 00 00 00 07 51 07 FF 07 FF 0F - FF - 39 01 00 00 00 00 02 5A 01 - 39 01 00 00 00 00 02 5F 00 - 39 01 00 00 00 00 02 9C 01 - 05 01 00 00 00 00 01 2C - 39 01 00 00 00 00 02 2f 00 - 39 01 00 00 00 00 02 26 01 - 39 01 00 00 00 00 02 5a 01 - 39 01 00 00 00 00 02 2f 30 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 02 6f 1c - 39 01 00 00 00 00 09 ba 91 04 04 00 01 - 04 04 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 06 c0 54 c0 00 21 43 - 39 01 00 00 00 00 06 f0 55 aa 52 08 02 - 39 01 00 00 00 00 02 cc 30 - 39 01 00 00 00 00 02 ce 01 - 39 01 00 00 20 00 02 cc 00 - 39 01 00 00 00 00 06 F0 55 AA 52 08 01 - 39 01 00 00 00 00 05 B2 55 01 FF 03 - 05 01 00 00 78 00 01 11 - 05 01 00 00 14 00 01 29 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <40>; - qcom,mdss-dsc-slice-width = <720>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; - }; - - timing@6 { - cell-index = <6>; - qcom,mdss-dsi-panel-framerate = <20>; - qcom,mdss-dsi-panel-width = <1440>; - qcom,mdss-dsi-panel-height = <3200>; - qcom,mdss-dsi-h-front-porch = <20>; - qcom,mdss-dsi-h-back-porch = <20>; - qcom,mdss-dsi-h-pulse-width = <4>; - qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <18>; - qcom,mdss-dsi-v-front-porch = <20>; - qcom,mdss-dsi-v-pulse-width = <2>; - qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-h-right-border = <0>; - qcom,mdss-dsi-v-top-border = <0>; - qcom,mdss-dsi-v-bottom-border = <0>; - qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <1199900000>; - - qcom,mdss-dsi-timing-switch-command = [ - 39 01 00 00 00 00 05 2a 00 00 05 9f - 39 01 00 00 00 00 05 2b 00 00 0c 7f - 39 01 00 00 00 00 02 8f 00 - 39 01 00 00 00 00 02 2f 00 - 39 01 00 00 00 00 02 26 01 - 39 01 00 00 00 00 02 5a 01 - 39 01 00 00 00 00 02 2f 30 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 02 6f 1c - 39 01 00 00 00 00 09 ba 91 05 05 00 01 - 05 05 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 06 c0 54 c0 00 21 43 - 39 01 00 00 00 00 06 f0 55 aa 52 08 02 - 39 01 00 00 00 00 02 cc 30 - 39 01 00 00 00 00 02 ce 01 - 39 01 00 00 20 00 02 cc 00 - ]; - - qcom,mdss-dsi-on-command = [ - 39 01 00 00 00 00 06 F0 55 AA 52 08 01 - 39 01 00 00 00 00 02 6F 01 - 39 01 00 00 00 00 04 C5 0B 0B 0B - 39 01 00 00 00 00 05 FF AA 55 A5 80 - 39 01 00 00 00 00 02 6F 02 - 39 01 00 00 00 00 02 F5 10 - 39 01 00 00 00 00 02 6F 1B - 39 01 00 00 00 00 02 F4 55 - 39 01 00 00 00 00 02 6F 18 - 39 01 00 00 00 00 02 F8 19 - 39 01 00 00 00 00 02 6F 0F - 39 01 00 00 00 00 02 FC 00 - 39 01 00 00 00 00 05 2A 00 00 05 9F - 39 01 00 00 00 00 05 2B 00 00 0C 7F - 39 01 00 00 00 00 03 90 03 03 - 39 01 00 00 00 00 13 91 89 28 00 28 c2 - 00 02 68 04 6c 00 0a 02 77 01 e9 10 - f0 - 39 01 00 00 00 00 05 ff aa 55 a5 81 - 39 01 00 00 00 00 02 6f 23 - 39 01 00 00 00 00 15 fb 00 01 00 11 33 - 33 33 55 57 d0 00 00 44 56 77 78 9a - bc dd f0 - 39 01 00 00 00 00 02 6F 06 - 39 01 00 00 00 00 02 F3 DC - 39 01 00 00 00 00 02 26 00 - 39 01 00 00 00 00 02 35 00 - 39 01 00 00 00 00 05 3B 00 18 00 10 - 39 01 00 00 00 00 02 53 20 - 39 01 00 00 00 00 07 51 07 FF 07 FF 0F - FF - 39 01 00 00 00 00 02 5A 01 - 39 01 00 00 00 00 02 5F 00 - 39 01 00 00 00 00 02 9C 01 - 05 01 00 00 00 00 01 2C - 39 01 00 00 00 00 02 2f 00 - 39 01 00 00 00 00 02 26 01 - 39 01 00 00 00 00 02 5a 01 - 39 01 00 00 00 00 02 2f 30 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 02 6f 1c - 39 01 00 00 00 00 09 ba 91 05 05 00 01 - 05 05 00 - 39 01 00 00 00 00 06 f0 55 aa 52 08 00 - 39 01 00 00 00 00 06 c0 54 c0 00 21 43 - 39 01 00 00 00 00 06 f0 55 aa 52 08 02 - 39 01 00 00 00 00 02 cc 30 - 39 01 00 00 00 00 02 ce 01 - 39 01 00 00 20 00 02 cc 00 - 39 01 00 00 00 00 06 F0 55 AA 52 08 01 - 39 01 00 00 00 00 05 B2 55 01 FF 03 - 05 01 00 00 78 00 01 11 - 05 01 00 00 14 00 01 29 - ]; - - qcom,mdss-dsi-off-command = [ - 05 01 00 00 14 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-timing-switch-command-state = - "dsi_lp_mode"; - qcom,mdss-dsi-h-sync-pulse = <0>; - qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index ed5a1961..6c83f483 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -111,6 +111,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index 212ad8ec..71f33306 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -112,6 +112,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index f22f4d3a..461591aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -122,6 +122,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 483359ec..22589d3e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -110,6 +110,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index 979693ae..b90133b6 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -131,6 +131,7 @@ "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index 841f1ee0..c665564d 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -130,6 +130,7 @@ "dsi_hs_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index af59a3fb..4992feb5 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -113,6 +113,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 7da07c60..061be26c 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -112,6 +112,7 @@ qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-h-sync-pulse = <0>; qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; qcom,mdss-dsc-slice-height = <40>; qcom,mdss-dsc-slice-width = <720>; qcom,mdss-dsc-slice-per-pkt = <1>; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index d60f583c..c8c82641 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -386,36 +386,22 @@ }; timing@2 { - qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 1f 06 - 06 06 06 02 04 13 0b]; + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@3 { - qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 12 1e 04 - 04 04 03 02 04 0e 09]; + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; timing@4 { - qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 - 03 03 02 02 04 0c 08]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@5 { - qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 - 03 03 02 02 04 0b 08]; - qcom,display-topology = <2 2 1>; - qcom,default-topology-index = <0>; - }; - - timing@6 { - qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 - 02 02 02 02 04 0a 07]; + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; }; diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4568ea85..eaa797b7 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -191,16 +191,6 @@ qcom,partial-update-enabled = "single_roi"; qcom,panel-roi-alignment = <720 40 720 40 1440 40>; }; - - timing@5 { - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 720 40 1440 40>; - }; - - timing@6 { - qcom,partial-update-enabled = "single_roi"; - qcom,panel-roi-alignment = <720 40 720 40 1440 40>; - }; }; }; From e6fa678d85ebb3149b3601e2f79a5826a01048a3 Mon Sep 17 00:00:00 2001 From: Xhoendi Collaku Date: Tue, 18 Jun 2024 21:59:13 -0700 Subject: [PATCH 119/242] Revert "ARM: dts: msm: update clock rate for csot panel cphy cmd mode" This reverts commit b8a176c81de007f290fd065d6d424eee80ec2317. Reason for revert: Release revert Change-Id: I7b9abd0923157850216955843265dce438b97adb --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 8030ebb2..427764d1 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -57,7 +57,6 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <728870000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 @@ -150,7 +149,6 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <548200000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 01 @@ -251,7 +249,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; - qcom,mdss-dsi-panel-clockrate = <728870000>; + qcom,mdss-dsi-panel-clockrate = <707640000>; qcom,mdss-dsi-timing-switch-command = [ 39 01 00 00 00 00 02 2f 00 From cdc4bd658812c03b1302d193799d609a6dab4426 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Thu, 20 Jun 2024 15:33:11 -0700 Subject: [PATCH 120/242] ARM: dts: msm: add sde_rscc register offset to cesta for sun target Add the sde_rscc register offset to help in accessing the cesta status registers. Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 5 +++-- display/trustedvm-sun-sde.dtsi | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5413498..72fe00dc 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -210,14 +210,15 @@ sde_cesta: qcom,sde_cesta@0x0af30000 { cell-index = <0>; compatible = "qcom,sde-cesta"; - reg = <0xaf30000 0x60>, + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, <0xaf36000 0x30>; - reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 93aa250c..fd827da3 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,7 +37,8 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0xaf30000 0x60>, + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, From dc3f289df8d8a53bad85cc92cdd2d6b71bc98046 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 20 Jun 2024 12:52:01 +0530 Subject: [PATCH 121/242] ARM: dts: msm: update panel-roi-alignment for dsi_sim_cmd on sun target Update in height alignments from 40 to 20 for FHD 60FPS cmd mode to match DSC slice settings. The values should be integral multiple of height defined for panel. Change-Id: I41e2e5b3ec0b75a6eb2f39879356c92239853f74 Signed-off-by: Abhinav Saurabh --- display/sun-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 4568ea85..42b30883 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -274,7 +274,7 @@ }; timing@2 { /* FHD 60FPS cmd mode*/ - qcom,panel-roi-alignment = <540 40 540 40 540 40>; + qcom,panel-roi-alignment = <540 20 540 20 540 20>; qcom,partial-update-enabled = "single_roi"; }; From d06aefb55dc6ded30fed3065f38965633e0a68fa Mon Sep 17 00:00:00 2001 From: Rui Chen Date: Wed, 19 Jun 2024 10:42:28 +0800 Subject: [PATCH 122/242] ARM: dts: msm: add pll_codes_region for secondary DSI PHY Add pll_codes_region propertity for secondary DSI PHY to support DSI dynamic clock switch feature. Change-Id: Iad0635b013094c833f9fb2304b5bbaf728f23360 Signed-off-by: Rui Chen --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5413498..0053de33 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -356,4 +356,5 @@ qcom,panel-allow-phy-poweroff; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; }; From ca2fc6dff779024032cfcaba18d85b4f87eb53d4 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Tue, 2 Jul 2024 17:09:50 -0700 Subject: [PATCH 123/242] ARM: dts: msm: add VHM properties to bindings Adds VHM related device tree properties to bindings and documents their meaning and usage. Change-Id: Idc43ba7bcfe1c8d9960aa00b3d807b74789d57f0 Signed-off-by: Kirill Shpin --- bindings/mdss-dsi-panel.yaml | 137 +++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml index f085a963..20ae28ff 100644 --- a/bindings/mdss-dsi-panel.yaml +++ b/bindings/mdss-dsi-panel.yaml @@ -660,6 +660,37 @@ properties: qcom,mdss-dsi-te-using-te-pin: description: Boolean to specify whether using hardware vsync. + qcom,mdss-esync: + description: > + Boolean entry to enable esync. "qcom,mdss-esync-hsync-milli-pulse-width" + property should be set along with this property. + + qcom,mdss-esync-milli-skew: + description: > + u32 entry to specify the skew between the esync signal and the timing + engine, in 1/1000ths of a pulse period. Example: + qcom,mdss-esync-milli-skew = <150>; + This would set the esync signal to precede the timing engine's output by + 0.15 of a pulse period. + default: 0 + + qcom,mdss-esync-hsync-milli-pulse-width: + description: > + u32 entry to specify the pulse width of the hsync portion of the esync + signal, in 1/1000ths of a pulse period. Example: + qcom,mdss-esync-hsync-milli-pulse-width = <750>; + This would set the esync line high for 0.75 of a pulse period, every hsync. + + qcom,mdss-esync-emsync-fps: + description: > + u32 entry to specify how frequently the esync signal should be modulated + with an EM pulse, in Hz. + + qcom,mdss-esync-emsync-milli-pulse-width: + description: > + u32 entry to specify the pulse width of the modulated esync signal, in + 1/1000ths of a pulse period. See "qcom,mdss-esync-hsync-milli-pulse-width". + qcom,qsync-enable: description: Boolean property to indicate if qsync is enabled/disabled. @@ -695,6 +726,79 @@ properties: default: dsi_lp_mode enum: [dsi_lp_mode, dsi_hs_mode] + qcom,mdss-dsi-esync-post-on-commands: + description: > + List of panel resume commands that need to be sent after the esync + generator has been enabled. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,mdss-dsi-sticky_still_en-command: + description: > + Command to enable panel GRAM and write to it in video mode. + + qcom,mdss-dsi-sticky_still_disable-command: + description: > + Command to disable panel GRAM in video mode. + + qcom,mdss-dsi-sticky_on_fly-command: + description: > + Command to enable panel GRAM and write to it for a self refresh for + exactly one frame. + + qcom,mdss-dsi-qsync-freq-step-sequence-interval: + description: > + Array of 3-value tuples that describe the value of the + "qcom,mdss-dsi-qsync-freq-step-sequence" property. + Within each tuple, first value corresponds to the type of frequency + stepping sequence (0 for normal usecase and 1 for video usecase), second + value corresponds to the starting framerate for the sequence (in mHz), + and third value corresponds to the number of steps in the sequence. + + qcom,mdss-dsi-qsync-freq-step-sequence: + description: > + Array of 2-value tuples that describe the framerate and duration of a step + in a sequence. + Within each tuple, first value corresponds to the framerate for this step + in the sequence, and second value corresponds to the duration in frames + of this step. + The tuples are arranged into groups defined by the + "qcom,mdss-dsi-qsync-freq-step-sequence-interval" property, which specifies + the length of a frequency stepping sequence in steps. + + qcom,mdss-dsi-freq-step-pattern1-command: + description: > + List of panel commands to indicate to the panel the beginning of the first + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern2-command: + description: > + List of panel commands to indicate to the panel the beginning of the second + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern3-command: + description: > + List of panel commands to indicate to the panel the beginning of the third + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern4-command: + description: > + List of panel commands to indicate to the panel the beginning of the fourth + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern5-command: + description: > + List of panel commands to indicate to the panel the beginning of the fifth + frequency stepping pattern, and information about that pattern. + + qcom,vrr-enable: + description: > + Boolean entry that restricts the inter-vsync frame latching to discrete + boundaries. + + qcom,video-psr-enable: + description: > + Boolean entry to specify that the panel supports GRAM usage in video mode. + qcom,mdss-dsi-te-pin-select: description: > Specifies TE operating mode. @@ -1765,6 +1869,16 @@ examples: mdss-dsi-tx-eot-append; qcom,ulps-enabled; qcom,suspend-ulps-enabled; + qcom,mdss-esync; + qcom,mdss-esync-milli-skew = <150>; + qcom,mdss-esync-hsync-milli-pulse-width = <750>; + qcom,mdss-esync-emsync-fps = <240>; + qcom,mdss-esync-emsync-milli-pulse-width = <300>; + qcom,qsync-enable; + qcom,vrr-enable; + qcom,video-psr-enable; + qcom,dsi-qsync-avr-step-fps = <240>; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; @@ -1827,6 +1941,29 @@ examples: qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 05 01 00 00 02 00 02 29 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-esync-post-on-commands = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_still_en-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_still_disable-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_on_fly-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-qsync-freq-step-sequence-interval = + <0 120000 2>, <0 10000 1>; + qcom,mdss-dsi-qsync-freq-step-sequence = + <60000 1>, <10000 1>, + <10000 2>; + qcom,mdss-dsi-freq-step-pattern1-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern2-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern3-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern4-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern5-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; qcom,mdss-dsi-timing-switch-command = [ 29 00 00 00 00 00 02 B0 04 29 00 00 00 00 00 02 F1 00]; From 4b3bee8622d5c011674e7569015c7579f0da7f93 Mon Sep 17 00:00:00 2001 From: Veera Sundaram Sankaran Date: Thu, 20 Jun 2024 15:33:11 -0700 Subject: [PATCH 124/242] ARM: dts: msm: add sde_rscc register offset to cesta for sun target Add the sde_rscc register offset to help in accessing the cesta status registers. Change-Id: I438002605a1bdf3ca06c92f4594a71bce70ef387 Signed-off-by: Veera Sundaram Sankaran --- display/sun-sde.dtsi | 5 +++-- display/trustedvm-sun-sde.dtsi | 3 ++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5413498..72fe00dc 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -210,14 +210,15 @@ sde_cesta: qcom,sde_cesta@0x0af30000 { cell-index = <0>; compatible = "qcom,sde-cesta"; - reg = <0xaf30000 0x60>, + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, <0xaf36000 0x30>; - reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index 93aa250c..fd827da3 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,7 +37,8 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0xaf30000 0x60>, + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, From cc7a2a70987776c79d8e2d8fe55219f32f2f55dd Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Mon, 8 Jul 2024 17:33:38 -0700 Subject: [PATCH 125/242] ARM: dts: msm: update pm qos for sun target Update sde-qos-cpu-mask value for sun target. Change-Id: I1e3a94b276d7ac31d693bdc73a46cc40189d5c43 Signed-off-by: Raviteja Tamatam --- display/sun-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 7e0b89cc..8a68f314 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,6 +259,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; + qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 7668b35d0247b5a6326e4db9c1989773df0cc0e0 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 17 Jul 2024 01:31:46 -0700 Subject: [PATCH 126/242] Revert "ARM: dts: msm: add sde_rscc register offset to cesta for sun target" This reverts commit 4b3bee8622d5c011674e7569015c7579f0da7f93. Change-Id: I56f2cbf8c58119733393bf12c63ed3d2127a91fc Signed-off-by: Linux Image Build Automation --- display/sun-sde.dtsi | 5 ++--- display/trustedvm-sun-sde.dtsi | 3 +-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 72fe00dc..f5413498 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -210,15 +210,14 @@ sde_cesta: qcom,sde_cesta@0x0af30000 { cell-index = <0>; compatible = "qcom,sde-cesta"; - reg = <0x0af20000 0x850>, - <0xaf30000 0x60>, + reg = <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + reg-names = "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; diff --git a/display/trustedvm-sun-sde.dtsi b/display/trustedvm-sun-sde.dtsi index fd827da3..93aa250c 100644 --- a/display/trustedvm-sun-sde.dtsi +++ b/display/trustedvm-sun-sde.dtsi @@ -37,8 +37,7 @@ qcom,sde-vm-exclude-reg-names = "sid_phys"; - qcom,tvm-include-reg = <0x0af20000 0x850>, - <0xaf30000 0x60>, + qcom,tvm-include-reg = <0xaf30000 0x60>, <0xaf31000 0x30>, <0xaf32000 0x30>, <0xaf33000 0x30>, From 22f51de9232416f67ab322ed80c464c41d37663e Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 22 Jul 2024 14:35:35 -0700 Subject: [PATCH 127/242] ARM: dts: msm: move esync RCG to SDE DSI node Driver needs to set esync clock's parent under a gating condition, which is not available at the point where the clocks under MDSS DSI node are parsed. Moves the esync RCG clock to SDE DSI instead. Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf Signed-off-by: Kirill Shpin --- display/sun-sde-display.dtsi | 22 ++++++++++++++++++---- display/sun-sde.dtsi | 12 ++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index c779d0fd..03774135 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,10 +92,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -121,10 +128,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f0d8064c..3c3f1462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,15 +313,13 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, - <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi1 { @@ -332,15 +330,13 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, - <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi_phy0 { From 6d718caa81ee3e38d9d48aa697ad7293e49e8570 Mon Sep 17 00:00:00 2001 From: Qing Huang Date: Wed, 3 Jul 2024 16:40:25 +0800 Subject: [PATCH 128/242] ARM: dts: msm: add HDR capability for panels on sun target Change adds HDR capability for panels on sun target Change-Id: I2e4dc6e037c3dc465103ee9c1c4465be7173c841 Signed-off-by: Qing Huang --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-10bit-video.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 5 +++++ .../dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 5 +++++ 15 files changed, 75 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index aad5198e..789ab9ac 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -38,6 +38,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index 79524689..010d6f73 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -31,6 +31,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index e1c2f792..84dfd229 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index fc12f0d7..45becd88 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -52,6 +52,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index 7b969aa8..a23f1478 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 4ebc8416..62b5e7fe 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 1d5cf4e7..0aadeb93 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -54,6 +54,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index dd6127df..fe91c356 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -42,6 +42,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index 71f33306..f94d9550 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 461591aa..0e1886aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index fe387ae4..38821fc6 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -47,6 +47,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index b90133b6..3384bf40 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -40,6 +40,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index c665564d..5a534706 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -42,6 +42,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 4992feb5..7840c1c2 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -28,6 +28,11 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 061be26c..93fd3234 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -35,6 +35,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 2d5488c29179392e5d0f28cc9d6c5e147326269e Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 22 Jul 2024 12:16:42 +0800 Subject: [PATCH 129/242] ARM: dts: msm: add battery_charger and qupv3_se15_i2c support This change adds battery_charger support for qrd/mtp and qupv3_se15_i2c support for cdp on sun target. Change-Id: I0fd532d386e8aff9212410e80e7183beeae7af3b Signed-off-by: Jinfeng Gu --- display/sun-sde-display-cdp.dtsi | 9 ++++++++- display/sun-sde-display-mtp.dtsi | 9 ++++++++- display/sun-sde-display-qrd.dtsi | 4 +++- 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index 2049962d..b2dd5503 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -307,6 +307,13 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr - &dsi_nt37801_amoled_vid_spr>; + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; }; diff --git a/display/sun-sde-display-mtp.dtsi b/display/sun-sde-display-mtp.dtsi index baa362b2..b62cf120 100644 --- a/display/sun-sde-display-mtp.dtsi +++ b/display/sun-sde-display-mtp.dtsi @@ -289,5 +289,12 @@ &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr - &dsi_nt37801_amoled_vid_spr>; + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; }; diff --git a/display/sun-sde-display-qrd.dtsi b/display/sun-sde-display-qrd.dtsi index c1339749..2e91032c 100644 --- a/display/sun-sde-display-qrd.dtsi +++ b/display/sun-sde-display-qrd.dtsi @@ -230,5 +230,7 @@ qcom,display-panels = <&dsi_nt37801_amoled_cmd &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video - &dsi_nt37801_amoled_video_cphy>; + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; }; From 34baca3d14ad3eb00a276206be444cf28f0da1e1 Mon Sep 17 00:00:00 2001 From: Yuchao Ma Date: Tue, 23 Jul 2024 17:40:25 +0800 Subject: [PATCH 130/242] ARM: dts: msm: Add spr pentile pack type for SPR panel This change adds pentile pack type for SPR panel. Also corrected the pack type to "BG-RG Type B" for sun target. Change-Id: I385a554b062b6d1fa86ff1ced8ead4fe791bcdd5 Signed-off-by: Yuchao Ma --- .../dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 +- .../dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 14 ++++++++++++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 2 +- ...dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 2 +- .../dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 14 ++++++++++++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 2 +- 6 files changed, 32 insertions(+), 4 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 45becd88..29afd64e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -51,7 +51,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 62b5e7fe..08e9b8b7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,6 +40,20 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 0aadeb93..5f34e53e 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -53,7 +53,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index fe91c356..26b49ed2 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -41,7 +41,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 0e1886aa..21e44730 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,6 +33,20 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 38821fc6..64d790cd 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -46,7 +46,7 @@ * # R B R B ... B R B R ... R B R B ... B R B R ... * ############################################################### */ - qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,spr-pentile-pack-type = "BG-RG Type B"; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; From edfe9f46a56ae830de9ce937621ed885a44ae204 Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Mon, 8 Jul 2024 17:33:38 -0700 Subject: [PATCH 131/242] ARM: dts: msm: update pm qos for sun target Update sde-qos-cpu-mask value for sun target. Change-Id: I1e3a94b276d7ac31d693bdc73a46cc40189d5c43 Signed-off-by: Raviteja Tamatam --- display/sun-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 7e0b89cc..8a68f314 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,6 +259,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; + qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 89f184dd38fdda2ac1c64633a2ff99710387732d Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 22 Jul 2024 14:35:35 -0700 Subject: [PATCH 132/242] ARM: dts: msm: move esync RCG to SDE DSI node Driver needs to set esync clock's parent under a gating condition, which is not available at the point where the clocks under MDSS DSI node are parsed. Moves the esync RCG clock to SDE DSI instead. Change-Id: I01e0fedbc7620425d237024663da944e2f7ae9cf Signed-off-by: Kirill Shpin --- display/sun-sde-display.dtsi | 22 ++++++++++++++++++---- display/sun-sde.dtsi | 12 ++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index c779d0fd..03774135 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,10 +92,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -121,10 +128,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f0d8064c..3c3f1462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,15 +313,13 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, - <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi1 { @@ -332,15 +330,13 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, - <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi_phy0 { From 0888108bdd1a4bfeb6fde9d32c0b591e7fd53941 Mon Sep 17 00:00:00 2001 From: Qing Huang Date: Wed, 3 Jul 2024 16:40:25 +0800 Subject: [PATCH 133/242] ARM: dts: msm: add HDR capability for panels on sun target Change adds HDR capability for panels on sun target Change-Id: I2e4dc6e037c3dc465103ee9c1c4465be7173c841 Signed-off-by: Qing Huang (cherry picked from commit 6d718caa81ee3e38d9d48aa697ad7293e49e8570) --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-10bit-video.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 5 +++++ .../dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 5 +++++ 15 files changed, 75 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index aad5198e..789ab9ac 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -38,6 +38,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index 79524689..010d6f73 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -31,6 +31,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index e1c2f792..84dfd229 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index fc12f0d7..45becd88 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -52,6 +52,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index 7b969aa8..a23f1478 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 4ebc8416..62b5e7fe 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 1d5cf4e7..0aadeb93 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -54,6 +54,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index dd6127df..fe91c356 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -42,6 +42,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index 71f33306..f94d9550 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 461591aa..0e1886aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index fe387ae4..38821fc6 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -47,6 +47,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index b90133b6..3384bf40 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -40,6 +40,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index c665564d..5a534706 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -42,6 +42,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 4992feb5..7840c1c2 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -28,6 +28,11 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 061be26c..93fd3234 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -35,6 +35,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 54ea574e80421afd95d1735ce41f8e6f4e10f5aa Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 31 Jul 2024 14:21:51 -0700 Subject: [PATCH 134/242] Revert "ARM: dts: msm: add HDR capability for panels on sun target" This reverts commit 0888108bdd1a4bfeb6fde9d32c0b591e7fd53941. Change-Id: Ibc4feea05e5be0ac6d4a49670c1d928475564676 Signed-off-by: Linux Image Build Automation --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-10bit-video.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 5 ----- .../dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 5 ----- 15 files changed, 75 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index 789ab9ac..aad5198e 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -38,11 +38,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index 010d6f73..79524689 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -31,11 +31,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index 84dfd229..e1c2f792 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 45becd88..fc12f0d7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -52,11 +52,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index a23f1478..7b969aa8 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 62b5e7fe..4ebc8416 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 0aadeb93..1d5cf4e7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -54,11 +54,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index fe91c356..dd6127df 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -42,11 +42,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index f94d9550..71f33306 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -33,11 +33,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 0e1886aa..461591aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,11 +33,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 38821fc6..fe387ae4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -47,11 +47,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index 3384bf40..b90133b6 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -40,11 +40,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index 5a534706..c665564d 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -42,11 +42,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 7840c1c2..4992feb5 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -28,11 +28,6 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 93fd3234..061be26c 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -35,11 +35,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <80>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 351096e02c86d301d367d16bd0a2bd6a26423199 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 31 Jul 2024 14:25:07 -0700 Subject: [PATCH 135/242] Revert "ARM: dts: msm: move esync RCG to SDE DSI node" This reverts commit 89f184dd38fdda2ac1c64633a2ff99710387732d. Change-Id: Ie469eea85132ee553518a3f3453c2a19c8ce0514 Signed-off-by: Linux Image Build Automation --- display/sun-sde-display.dtsi | 22 ++++------------------ display/sun-sde.dtsi | 12 ++++++++---- 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 03774135..c779d0fd 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,17 +92,10 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>, - /* - * The esync clk RCG is only necessary here to set its parent - * to the pll dsi clk, which also needs to be available at the - * point that its known whether the clock will be used. After - * updating the parent, this clock handle is no longer needed. - */ - <&dispcc DISP_CC_ESYNC0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk", "esync_clk_rcg"; + "mdp_core_clk"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -128,17 +121,10 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>, - /* - * The esync clk RCG is only necessary here to set its parent - * to the pll dsi clk, which also needs to be available at the - * point that its known whether the clock will be used. After - * updating the parent, this clock handle is no longer needed. - */ - <&dispcc DISP_CC_ESYNC1_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk", "esync_clk_rcg"; + "mdp_core_clk"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 3c3f1462..f0d8064c 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,13 +313,15 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", - "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi1 { @@ -330,13 +332,15 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", - "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi_phy0 { From c6e78953ec2a45e5a255b976ebb03b591223ca09 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Wed, 31 Jul 2024 14:25:18 -0700 Subject: [PATCH 136/242] Revert "ARM: dts: msm: update pm qos for sun target" This reverts commit edfe9f46a56ae830de9ce937621ed885a44ae204. Change-Id: I30632b67e4542f93e06d3258465a40d658fc29db Signed-off-by: Linux Image Build Automation --- display/sun-sde-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 8a68f314..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,7 +259,6 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; - qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 480057594641d2ae8964894488e41871c86e26a5 Mon Sep 17 00:00:00 2001 From: Raviteja Tamatam Date: Mon, 8 Jul 2024 17:33:38 -0700 Subject: [PATCH 137/242] ARM: dts: msm: update pm qos for sun target Update sde-qos-cpu-mask value for sun target. Change-Id: I9eeb298857d739bdf19620a9dde2c064dceea1ae Signed-off-by: Raviteja Tamatam --- display/sun-sde-common.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 7e0b89cc..8a68f314 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,6 +259,7 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; + qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 82fd582ac4c360950fe43ada3c40d564397cc165 Mon Sep 17 00:00:00 2001 From: Kirill Shpin Date: Mon, 22 Jul 2024 14:35:35 -0700 Subject: [PATCH 138/242] ARM: dts: msm: move esync RCG to SDE DSI node Driver needs to set esync clock's parent under a gating condition, which is not available at the point where the clocks under MDSS DSI node are parsed. Moves the esync RCG clock to SDE DSI instead. Change-Id: I0a94ecdf0dc3318baa0685eb78b14dbc9e052538 Signed-off-by: Kirill Shpin --- display/sun-sde-display.dtsi | 22 ++++++++++++++++++---- display/sun-sde.dtsi | 12 ++++-------- 2 files changed, 22 insertions(+), 12 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index c779d0fd..03774135 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,10 +92,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -121,10 +128,17 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>; + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk"; + "mdp_core_clk", "esync_clk_rcg"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f0d8064c..3c3f1462 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,15 +313,13 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, - <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, - <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi1 { @@ -332,15 +330,13 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, - <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, - <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", - "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; }; &mdss_dsi_phy0 { From 50d358d3ef9a567f4d64469a5975ffd36681ce06 Mon Sep 17 00:00:00 2001 From: Qing Huang Date: Wed, 3 Jul 2024 16:40:25 +0800 Subject: [PATCH 139/242] ARM: dts: msm: add HDR capability for panels on sun target Change adds HDR capability for panels on sun target Change-Id: Ibb106a5651579535a4ede964dc10fcd8b086a562 Signed-off-by: Qing Huang --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-10bit-video.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 5 +++++ display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 5 +++++ .../dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 5 +++++ display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 5 +++++ 15 files changed, 75 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index aad5198e..789ab9ac 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -38,6 +38,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index 79524689..010d6f73 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -31,6 +31,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index e1c2f792..84dfd229 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index fc12f0d7..45becd88 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -52,6 +52,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index 7b969aa8..a23f1478 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 4ebc8416..62b5e7fe 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,6 +40,11 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 1d5cf4e7..0aadeb93 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -54,6 +54,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index dd6127df..fe91c356 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -42,6 +42,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index 71f33306..f94d9550 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 461591aa..0e1886aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,6 +33,11 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index fe387ae4..38821fc6 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -47,6 +47,11 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index b90133b6..3384bf40 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -40,6 +40,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index c665564d..5a534706 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -42,6 +42,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 4992feb5..7840c1c2 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -28,6 +28,11 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 061be26c..93fd3234 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -35,6 +35,11 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 07d7e6353c8cee768a2c58edd78ea4381761ae8d Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Thu, 15 Aug 2024 19:35:06 -0700 Subject: [PATCH 140/242] Revert "ARM: dts: msm: add HDR capability for panels on sun target" This reverts commit 50d358d3ef9a567f4d64469a5975ffd36681ce06. Change-Id: I6d8e1df2a60cc029d4f52ca69e152a0160506c8c Signed-off-by: Linux Image Build Automation --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-10bit-video.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi | 5 ----- display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi | 5 ----- .../dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 5 ----- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 5 ----- 15 files changed, 75 deletions(-) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index 789ab9ac..aad5198e 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -38,11 +38,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi index 010d6f73..79524689 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -31,11 +31,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi index 84dfd229..e1c2f792 100644 --- a/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 45becd88..fc12f0d7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -52,11 +52,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi index a23f1478..7b969aa8 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi index 62b5e7fe..4ebc8416 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -40,11 +40,6 @@ qcom,mdss-dsi-te-check-enable; qcom,mdss-dsi-te-using-te-pin; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi index 0aadeb93..1d5cf4e7 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -54,11 +54,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index fe91c356..dd6127df 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -42,11 +42,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi index f94d9550..71f33306 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -33,11 +33,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi index 0e1886aa..461591aa 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -33,11 +33,6 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi index 38821fc6..fe387ae4 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -47,11 +47,6 @@ * ############################################################### */ qcom,spr-pentile-pack-type = "RG-BG Type A"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi index 3384bf40..b90133b6 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -40,11 +40,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi index 5a534706..c665564d 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -42,11 +42,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <60>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 7840c1c2..4992feb5 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -28,11 +28,6 @@ qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; qcom,spr-pack-type = "pentile"; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 93fd3234..061be26c 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -35,11 +35,6 @@ qcom,spr-pack-type = "pentile"; qcom,qsync-enable; qcom,mdss-dsi-qsync-min-refresh-rate = <80>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 - 15700 12250 35800 6750 2550>; - qcom,mdss-dsi-panel-peak-brightness = <13000000>; - qcom,mdss-dsi-panel-blackness-level = <10>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; From 4b579dbb1c1b4941769d875eb242c72d285f7f07 Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Thu, 15 Aug 2024 19:35:17 -0700 Subject: [PATCH 141/242] Revert "ARM: dts: msm: move esync RCG to SDE DSI node" This reverts commit 82fd582ac4c360950fe43ada3c40d564397cc165. Change-Id: Iebe62d036948a984e3d3f7c2d49c4cc4d64954ec Signed-off-by: Linux Image Build Automation --- display/sun-sde-display.dtsi | 22 ++++------------------ display/sun-sde.dtsi | 12 ++++++++---- 2 files changed, 12 insertions(+), 22 deletions(-) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 03774135..c779d0fd 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -92,17 +92,10 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>, - /* - * The esync clk RCG is only necessary here to set its parent - * to the pll dsi clk, which also needs to be available at the - * point that its known whether the clock will be used. After - * updating the parent, this clock handle is no longer needed. - */ - <&dispcc DISP_CC_ESYNC0_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk", "esync_clk_rcg"; + "mdp_core_clk"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; @@ -128,17 +121,10 @@ * MDP clock nodes, no actual vote shall be added and this * change is done just to satisfy sync state requirements. */ - <&dispcc DISP_CC_MDSS_MDP_CLK>, - /* - * The esync clk RCG is only necessary here to set its parent - * to the pll dsi clk, which also needs to be available at the - * point that its known whether the clock will be used. After - * updating the parent, this clock handle is no longer needed. - */ - <&dispcc DISP_CC_ESYNC1_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "pll_byte_clk0", "pll_dsi_clk0", "pll_byte_clk1", "pll_dsi_clk1", - "mdp_core_clk", "esync_clk_rcg"; + "mdp_core_clk"; vddio-supply = <&L12B>; vci-supply = <&L13B>; vdd-supply = <&L11B>; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 3c3f1462..f0d8064c 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -313,13 +313,15 @@ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&mdss_dsi_phy0 1>, <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_ESYNC0_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC0_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", - "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi1 { @@ -330,13 +332,15 @@ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&mdss_dsi_phy1 1>, <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_ESYNC1_CLK_SRC>, <&dispcc DISP_CC_OSC_CLK>, <&dispcc DISP_CC_MDSS_ESC1_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", - "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", - "esc_clk", "xo"; + "pixel_clk", "pixel_clk_rcg", "pll_dsi_clk", + "esync_clk", "esync_clk_rcg", "osc_clk", "esc_clk", "xo"; }; &mdss_dsi_phy0 { From 3806d55c2b8a205ee391805c7856954a93361b0c Mon Sep 17 00:00:00 2001 From: Linux Image Build Automation Date: Thu, 15 Aug 2024 19:35:29 -0700 Subject: [PATCH 142/242] Revert "ARM: dts: msm: update pm qos for sun target" This reverts commit 480057594641d2ae8964894488e41871c86e26a5. Change-Id: I7dbc07a2a9fed8f1ed42edb2c0f24772a484e633 Signed-off-by: Linux Image Build Automation --- display/sun-sde-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 8a68f314..7e0b89cc 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -259,7 +259,6 @@ qcom,sde-cdp-setting = <1 1>, <1 0>; - qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; qcom,sde-qos-cpu-irq-latency = <300>; From 60fb428708813f7313cde1fbc82d95aabb5d52ec Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Mon, 29 Jul 2024 20:55:23 +0800 Subject: [PATCH 143/242] ARM: dts: msm: add disp_cc vote for all components Sync state will remove the disp_cc device vote once the device driver probe is complete. It removes the DSI clock vote early for continuous splash usecase because DSI driver takes its vote in component binding instead of device driver probe. It is better to keep disp_cc vote for components till respective device probe complete and they register themselves to master component. This change adds disp_cc vote for smmu_sde_unsec, smmu_sde_sec, sde_wb1 and sde_wb2 devices to retain vote till bind_all API is called. Change-Id: Ie6e39cb53c4fdd93a1ce7d07a0fc99a250235902 Signed-off-by: Lei Chen --- display/sun-sde-display.dtsi | 4 ++++ display/sun-sde.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/display/sun-sde-display.dtsi b/display/sun-sde-display.dtsi index 03774135..a1a671ef 100644 --- a/display/sun-sde-display.dtsi +++ b/display/sun-sde-display.dtsi @@ -24,12 +24,16 @@ compatible = "qcom,wb-display"; cell-index = <0>; label = "wb_display1"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; sde_wb2: qcom,wb-display@2 { compatible = "qcom,wb-display"; cell-index = <1>; label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 3c3f1462..29503362 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -197,6 +197,8 @@ qcom,iommu-faults = "non-fatal"; qcom,iommu-earlymap; /* for cont-splash */ dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; smmu_sde_sec: qcom,smmu_sde_sec_cb { @@ -205,6 +207,8 @@ memory-region = <&smmu_sde_iommu_region_partition>; qcom,iommu-faults = "non-fatal"; qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; sde_cesta: qcom,sde_cesta@0x0af30000 { From 5560b268c7d954113f79e64b1926de60c65bfe22 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 7 Aug 2024 17:14:21 +0800 Subject: [PATCH 144/242] ARM: dts: msm: update clock rate for csot panel 10 bits cmd panel Increased clock rate with 2% config for 10 bits dphy cmd panel due to transfer time go beyond cause frame-drop with cesta enabled. Change-Id: I30fed53879bcf04ade37ff737b27c87f82740c67 Signed-off-by: Jinfeng Gu --- display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi index 789ab9ac..5d19e90e 100644 --- a/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi +++ b/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -61,6 +61,7 @@ qcom,mdss-dsi-v-top-border = <0>; qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1223800000>; qcom,mdss-dsi-on-command = [ 39 01 00 00 00 00 06 f0 55 aa 52 08 01 From a9c2cc7fc50f11a5b4291e74919f19fb766a19e5 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Tue, 6 Aug 2024 10:38:40 +0800 Subject: [PATCH 145/242] ARM: dts: msm: enable 4ppc mode for DP on sun platform Enable 4ppc mode for DP on sun platform to support higher resolution mode. Change-Id: I54208fd665710b5162bf20b1f676ed59c585226b Signed-off-by: Yahui Wang --- display/sun-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 29503362..2617a86c 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -95,6 +95,7 @@ qcom,max-pclk-frequency-khz = <675000>; qcom,widebus-enable; + qcom,4ppc-enable; qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; From 99dbb522fe10e17abdac88a6bd6510ac7d0e533f Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Tue, 13 Aug 2024 12:41:25 +0530 Subject: [PATCH 146/242] ARM: dts: qcom: Add APQ support for ATP platform This patch adds APQ support for ATP platform. Change-Id: I6b91f7151cc88834782fc6068d3adfc2f2024b84 Signed-off-by: Akash Gajjar --- display/sun-sde-display-atp-overlay.dts | 4 +++- display/sun-sde-display-rcm-kiwi-overlay.dts | 4 +++- display/sun-sde-display-rcm-kiwi-v8-overlay.dts | 4 +++- display/sun-sde-display-rcm-overlay.dts | 4 +++- display/sun-sde-display-rcm-v8-overlay.dts | 4 +++- display/sun-sde.dts | 4 +++- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/display/sun-sde-display-atp-overlay.dts b/display/sun-sde-display-atp-overlay.dts index 7f336bb0..374a8b41 100644 --- a/display/sun-sde-display-atp-overlay.dts +++ b/display/sun-sde-display-atp-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun ATP"; compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x10021 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-overlay.dts b/display/sun-sde-display-rcm-kiwi-overlay.dts index 1c8b7c19..28228c2e 100644 --- a/display/sun-sde-display-rcm-kiwi-overlay.dts +++ b/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x40015 0>; }; diff --git a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts index a331b956..3e7c2ff6 100644 --- a/display/sun-sde-display-rcm-kiwi-v8-overlay.dts +++ b/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x20015 0>; }; diff --git a/display/sun-sde-display-rcm-overlay.dts b/display/sun-sde-display-rcm-overlay.dts index 6a5c7e1d..c0c75af3 100644 --- a/display/sun-sde-display-rcm-overlay.dts +++ b/display/sun-sde-display-rcm-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x15 0>; }; diff --git a/display/sun-sde-display-rcm-v8-overlay.dts b/display/sun-sde-display-rcm-v8-overlay.dts index e69e5198..86e99543 100644 --- a/display/sun-sde-display-rcm-v8-overlay.dts +++ b/display/sun-sde-display-rcm-v8-overlay.dts @@ -11,6 +11,8 @@ / { model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; - qcom,msm-id = <618 0x10000>, <618 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <0x30015 0>; }; diff --git a/display/sun-sde.dts b/display/sun-sde.dts index 4b3a3f74..36b0c926 100644 --- a/display/sun-sde.dts +++ b/display/sun-sde.dts @@ -9,6 +9,8 @@ #include "sun-sde.dtsi" / { - qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; qcom,board-id = <15 0>; }; From bd65aed9a36c4d68cb0d769770163814d77ee046 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Mon, 15 Jul 2024 19:25:40 +0530 Subject: [PATCH 147/242] ARM: dts: msm: add board id for sun MTP with 3.5mm Kiwi WLAN V8 Power Grid Add board id for Sun MTP with 3.5mm Kiwi WLAN V8 Power Grid. Change-Id: I9bd6275a37275e4f10f8c4efe3bf7bf95f581776 Signed-off-by: Akash Gajjar --- display/sun-sde-display-mtp-kiwi-v8-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts index 982183cb..102879d4 100644 --- a/display/sun-sde-display-mtp-kiwi-v8-overlay.dts +++ b/display/sun-sde-display-mtp-kiwi-v8-overlay.dts @@ -15,5 +15,5 @@ qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, <0x100026a 0x10000>, <0x100026a 0x20000>, <0x100027f 0x10000>, <0x100027f 0x20000>; - qcom,board-id = <0x50008 0>; + qcom,board-id = <0x50008 0>, <0x60108 0>; }; From d334f234de483b06d30100a3c71455833b14130e Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:55:39 +0530 Subject: [PATCH 148/242] ARM: dts: msm: add DDIC SPR cmd/video mode on sun trustedvm platform Add DDIC SPR cmd/video mode on sun trustedvm platform. Change-Id: Ieae00136db2e76c1119ec42eac89a4c2df51a074 Signed-off-by: Ayushi Makhija --- display/trustedvm-sun-sde-display-cdp.dtsi | 22 ++++++++++++++++++++++ display/trustedvm-sun-sde-display-mtp.dtsi | 20 ++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/display/trustedvm-sun-sde-display-cdp.dtsi b/display/trustedvm-sun-sde-display-cdp.dtsi index 13d89f62..cc339fca 100644 --- a/display/trustedvm-sun-sde-display-cdp.dtsi +++ b/display/trustedvm-sun-sde-display-cdp.dtsi @@ -54,6 +54,24 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_nt37801_amoled_cmd_spr { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -166,6 +184,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_video_cphy &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; @@ -179,6 +199,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; }; diff --git a/display/trustedvm-sun-sde-display-mtp.dtsi b/display/trustedvm-sun-sde-display-mtp.dtsi index d762f789..ea7d79ce 100644 --- a/display/trustedvm-sun-sde-display-mtp.dtsi +++ b/display/trustedvm-sun-sde-display-mtp.dtsi @@ -41,6 +41,24 @@ qcom,platform-reset-gpio = <&tlmm 98 0>; }; +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + &dsi_sim_panel_au { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; @@ -92,6 +110,8 @@ &dsi_nt37801_amoled_cmd_cphy &dsi_nt37801_amoled_video &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr &dsi_nt37801_amoled_dsc_10b_video &dsi_nt37801_amoled_cmd_spr &dsi_nt37801_amoled_vid_spr>; From 5f9b22a66d8e592a860ed6e7a69884a7177275c2 Mon Sep 17 00:00:00 2001 From: Ping Li Date: Thu, 5 Sep 2024 13:18:08 -0700 Subject: [PATCH 149/242] ARM: dts: msm: add support for sw fuse for Sun target Add sw fuse range to dts file for Sun target. The swfuse_phys is only needed in primary VM. Change-Id: I8a7446c2f6cbf183a7bff6af463ff7f427467628 Signed-off-by: Ping Li --- display/sun-sde-common.dtsi | 6 ++++-- display/sun-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 8a68f314..12270f64 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x128>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index 2617a86c..f5dda611 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -275,7 +275,7 @@ qcom,sde-soccp-controller = <&soccp_pas>; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From c6d3648a833818f334d8902baa90cf52fc5b0872 Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Tue, 30 Apr 2024 14:54:42 -0700 Subject: [PATCH 150/242] ARM: dts: qcom: update display panel for battery_charger on Sun HDK Update the list of display panels under battery_charger device to support enable/disable notifications from the charger firmware at runtime based on panel event notifications on Sun HDK. Change-Id: I2d025b23915c0ebce4ebb8caafcdec672fed9b2c Signed-off-by: Subbaraman Narayanamurthy --- display/sun-sde-display-hdk.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-hdk.dtsi b/display/sun-sde-display-hdk.dtsi index a5868788..fd5bca06 100644 --- a/display/sun-sde-display-hdk.dtsi +++ b/display/sun-sde-display-hdk.dtsi @@ -277,7 +277,8 @@ qcom,display-panels = <&dsi_vtdr6130_amoled_cmd &dsi_vtdr6130_amoled_video &dsi_vtdr6130_amoled_120hz_cmd - &dsi_vtdr6130_amoled_120hz_video>; + &dsi_vtdr6130_amoled_120hz_video + &dsi_ext_bridge_1080p>; }; &qupv3_se4_spi { From f67e4c69c1b191a36bd8bccfef5514745e071b6a Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Sat, 7 Sep 2024 03:46:16 +0530 Subject: [PATCH 151/242] ARM: dts: msm: add initial dsi display nodes for Tuna Add initial dsi display nodes for Tuna. Change-Id: Iadcf785e9ecdaa8baabe94ce0921190d141170d2 Signed-off-by: Abhinav Saurabh --- display/tuna-sde-common.dtsi | 149 +++++++++++++++++++++++++++++++++++ display/tuna-sde.dts | 14 ++++ display/tuna-sde.dtsi | 57 ++++++++++++++ 3 files changed, 220 insertions(+) create mode 100644 display/tuna-sde-common.dtsi create mode 100644 display/tuna-sde.dts create mode 100644 display/tuna-sde.dtsi diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi new file mode 100644 index 00000000..a9d1afed --- /dev/null +++ b/display/tuna-sde-common.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <925000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/tuna-sde.dts b/display/tuna-sde.dts new file mode 100644 index 00000000..b9a80b12 --- /dev/null +++ b/display/tuna-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde.dtsi" + +/ { + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi new file mode 100644 index 00000000..04165109 --- /dev/null +++ b/display/tuna-sde.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; From 722ce2c3d0dedad9138ae054575762c12765d3bb Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Wed, 25 Sep 2024 15:07:27 +0530 Subject: [PATCH 152/242] ARM: dts: msm: add initial dp display nodes for Tuna target Add initial dp display nodes for Tuna target. Change-Id: I1ae45cea93d708b0eb76e59a43dd849de536f22c Signed-off-by: Mani Chandana Ballary Kuntumalla --- display/tuna-sde.dtsi | 169 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 04165109..4c964d5b 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -2,11 +2,180 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include +#include #include "tuna-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "disabled"; + + //usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L3B>; + vdda_usb-0p9-supply = <&L3B>; + //vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1300000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; }; &mdss_mdp { From a0472afd5fb7f622edcead5517e2a8dfd18ff242 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 17 Sep 2024 10:28:08 +0530 Subject: [PATCH 153/242] ARM: dts: msm: enable display on tuna platforms Enable display on tuna platforms. Change-Id: I039ff6c32febd7b2afebfaa24a921186b5a46f2c Signed-off-by: Abhinav Saurabh --- Kbuild | 11 + display/tuna-sde-display-atp-overlay.dts | 17 + display/tuna-sde-display-cdp-overlay.dts | 17 + display/tuna-sde-display-cdp.dtsi | 192 +++ display/tuna-sde-display-common.dtsi | 1043 +++++++++++++++++ display/tuna-sde-display-mtp-kiwi-overlay.dts | 17 + display/tuna-sde-display-mtp-kiwi.dtsi | 6 + display/tuna-sde-display-mtp-overlay.dts | 17 + display/tuna-sde-display-mtp.dtsi | 186 +++ display/tuna-sde-display-pinctrl.dtsi | 114 ++ display/tuna-sde-display-qrd-overlay.dts | 17 + display/tuna-sde-display-qrd.dtsi | 126 ++ display/tuna-sde-display-rcm-overlay.dts | 17 + display/tuna-sde-display-rumi-overlay.dts | 16 + display/tuna-sde-display-rumi.dtsi | 11 + display/tuna-sde-display.dtsi | 204 ++++ 16 files changed, 2011 insertions(+) create mode 100644 display/tuna-sde-display-atp-overlay.dts create mode 100644 display/tuna-sde-display-cdp-overlay.dts create mode 100644 display/tuna-sde-display-cdp.dtsi create mode 100644 display/tuna-sde-display-common.dtsi create mode 100644 display/tuna-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/tuna-sde-display-mtp-kiwi.dtsi create mode 100644 display/tuna-sde-display-mtp-overlay.dts create mode 100644 display/tuna-sde-display-mtp.dtsi create mode 100644 display/tuna-sde-display-pinctrl.dtsi create mode 100644 display/tuna-sde-display-qrd-overlay.dts create mode 100644 display/tuna-sde-display-qrd.dtsi create mode 100644 display/tuna-sde-display-rcm-overlay.dts create mode 100644 display/tuna-sde-display-rumi-overlay.dts create mode 100644 display/tuna-sde-display-rumi.dtsi create mode 100644 display/tuna-sde-display.dtsi diff --git a/Kbuild b/Kbuild index 1e85878a..dfa6c483 100644 --- a/Kbuild +++ b/Kbuild @@ -30,6 +30,17 @@ dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ display/trustedvm-sun-sde-display-qrd-overlay.dtbo endif +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ + display/tuna-sde-display-atp-overlay.dtbo \ + display/tuna-sde-display-cdp-overlay.dtbo \ + display/tuna-sde-display-mtp-overlay.dtbo \ + display/tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/tuna-sde-display-qrd-overlay.dtbo \ + display/tuna-sde-display-rumi-overlay.dtbo \ + display/tuna-sde-display-rcm-overlay.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/display/tuna-sde-display-atp-overlay.dts b/display/tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..87105863 --- /dev/null +++ b/display/tuna-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/tuna-sde-display-cdp-overlay.dts b/display/tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..ac83131c --- /dev/null +++ b/display/tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..3a36881e --- /dev/null +++ b/display/tuna-sde-display-cdp.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi new file mode 100644 index 00000000..11e68080 --- /dev/null +++ b/display/tuna-sde-display-common.dtsi @@ -0,0 +1,1043 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +#include "tuna-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1950000>; + qcom,supply-enable-load = <154000>; + qcom,supply-disable-load = <45000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1000000>; + qcom,supply-max-voltage = <1100000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <471>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3540000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 77 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 78 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YYG with reduced margins */ + +&dsi_nt37801_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 1a 0c 00]; + qcom,display-topology = <1 0 1>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/tuna-sde-display-mtp-kiwi-overlay.dts b/display/tuna-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..e826d973 --- /dev/null +++ b/display/tuna-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/display/tuna-sde-display-mtp-kiwi.dtsi b/display/tuna-sde-display-mtp-kiwi.dtsi new file mode 100644 index 00000000..ddf34dc6 --- /dev/null +++ b/display/tuna-sde-display-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include "tuna-sde-display-mtp.dtsi" diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..277cc2e7 --- /dev/null +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>, <8 1>; +}; diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..cf76078e --- /dev/null +++ b/display/tuna-sde-display-mtp.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/tuna-sde-display-pinctrl.dtsi b/display/tuna-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..dafc8eb9 --- /dev/null +++ b/display/tuna-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/display/tuna-sde-display-qrd-overlay.dts b/display/tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..b422a057 --- /dev/null +++ b/display/tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..5a3f6295 --- /dev/null +++ b/display/tuna-sde-display-qrd.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/display/tuna-sde-display-rcm-overlay.dts b/display/tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..3adf6685 --- /dev/null +++ b/display/tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/display/tuna-sde-display-rumi-overlay.dts b/display/tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..d7f33da6 --- /dev/null +++ b/display/tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/tuna-sde-display-rumi.dtsi b/display/tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..9f4795a1 --- /dev/null +++ b/display/tuna-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi new file mode 100644 index 00000000..12934721 --- /dev/null +++ b/display/tuna-sde-display.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "tuna-sde-display-common.dtsi" + +&soc { +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; From d61e445679c3752a96ad46e50d98d149b0da9ba7 Mon Sep 17 00:00:00 2001 From: Jyothi bommidi Date: Wed, 25 Sep 2024 12:08:44 +0530 Subject: [PATCH 154/242] ARM: dts: msm: enable touch support for tuna display Enable touch support for tuna on CDP, MTP and QRD platforms. Change-Id: I976de6d01cc99bf6698128a121cc43041071461a Signed-off-by: Jyothi bommidi --- display/tuna-sde-display-cdp.dtsi | 15 +++++++++++++++ display/tuna-sde-display-mtp.dtsi | 16 ++++++++++++++++ display/tuna-sde-display-qrd.dtsi | 11 +++++++++++ 3 files changed, 42 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 3a36881e..c275438b 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -190,3 +190,18 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi index cf76078e..e330558d 100644 --- a/display/tuna-sde-display-mtp.dtsi +++ b/display/tuna-sde-display-mtp.dtsi @@ -184,3 +184,19 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 5a3f6295..13de5d6f 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -124,3 +124,14 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; + }; +}; From e1e3bcbddebda5112036ee0004f7a6276c9235a2 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Tue, 24 Sep 2024 13:04:15 +0530 Subject: [PATCH 155/242] ARM: dts: msm: add display dt node for Tuna target This patch adds display device tree support for Tuna target. Change-Id: Ife1ab80dcb78fc7654805ab5bedec76bdd33039d Signed-off-by: Akash Gajjar --- display/trustedvm-tuna-sde.dtsi | 81 ++++++++ display/tuna-sde-common.dtsi | 320 ++++++++++++++++++++++++++++++++ display/tuna-sde.dtsi | 81 ++++++++ 3 files changed, 482 insertions(+) create mode 100644 display/trustedvm-tuna-sde.dtsi diff --git a/display/trustedvm-tuna-sde.dtsi b/display/trustedvm-tuna-sde.dtsi new file mode 100644 index 00000000..79d85eab --- /dev/null +++ b/display/trustedvm-tuna-sde.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version =<0xC0000000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index a9d1afed..be5b2380 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -7,6 +7,326 @@ &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x65000 0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0xa 6>; + qcom,sde-wb-id = <1 2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000 0x2d000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13 14>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <6 7 1 2 3 4 5>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>, + <0x2c330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>, + <0x2c334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x3>; + qcom,sde-ubwc-version = <0x50000001>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <23600000>; + qcom,sde-max-bw-high-kbps = <27800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <4>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 4c964d5b..79fb22e3 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -5,8 +5,10 @@ #include #include #include +#include #include #include +#include #include "tuna-sde-common.dtsi" &soc { @@ -175,10 +177,89 @@ qcom,supply-disable-load = <0>; }; }; + + }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; }; }; &mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + + qcom,hw-fence-sw-version = <0x1>; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + mmcx-supply = <&VDD_MMCX_LEVEL>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; }; &mdss_dsi0 { From bfd09f6c6de1bb51669f7263068da1c254a194d7 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 10 Oct 2024 11:33:04 +0530 Subject: [PATCH 156/242] ARM: dts: msm: update dsi supply voltage for tuna Update DSI and panel supply voltage configuration as per the recent change in the supplier regulators. Change-Id: I68f81440637a673810773c5c8790da7bf7db38ba Signed-off-by: Abhinav Saurabh --- display/tuna-sde-common.dtsi | 8 ++++---- display/tuna-sde-display-common.dtsi | 6 +++--- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index be5b2380..e2a5d2f5 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -349,7 +349,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -375,7 +375,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -412,7 +412,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; + qcom,supply-max-voltage = <950000>; qcom,supply-enable-load = <98000>; qcom,supply-disable-load = <96>; }; @@ -448,7 +448,7 @@ reg = <0>; qcom,supply-name = "vdda-0p9"; qcom,supply-min-voltage = <880000>; - qcom,supply-max-voltage = <925000>; + qcom,supply-max-voltage = <950000>; qcom,supply-enable-load = <98000>; qcom,supply-disable-load = <96>; }; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 11e68080..21e45a58 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -55,7 +55,7 @@ reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1950000>; + qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <154000>; qcom,supply-disable-load = <45000>; qcom,supply-post-on-sleep = <20>; @@ -64,7 +64,7 @@ qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "vdd"; - qcom,supply-min-voltage = <1000000>; + qcom,supply-min-voltage = <1030000>; qcom,supply-max-voltage = <1100000>; qcom,supply-enable-load = <220000>; qcom,supply-disable-load = <471>; @@ -75,7 +75,7 @@ reg = <2>; qcom,supply-name = "vci"; qcom,supply-min-voltage = <3000000>; - qcom,supply-max-voltage = <3540000>; + qcom,supply-max-voltage = <3544000>; qcom,supply-enable-load = <10000>; qcom,supply-disable-load = <300>; qcom,supply-post-on-sleep = <0>; From b37f9177371868805978c0a38747b7e6be6260e3 Mon Sep 17 00:00:00 2001 From: Akash Gajjar Date: Thu, 3 Oct 2024 10:51:13 +0530 Subject: [PATCH 157/242] ARM: dts: msm: enable display connectors on tuna target Add smmu secure, unsecure, wb1, wb2 DT node on tuna target. Change-Id: Iae9cfd130a704773f63e3fbb1ab2f1b20a09681d Signed-off-by: Akash Gajjar --- display/tuna-sde-display.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index 12934721..cbcbda6f 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -7,6 +7,21 @@ #include "tuna-sde-display-common.dtsi" &soc { + sde_wb1: qcom,wb-display@1 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display1"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <1>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &sde_dsi { @@ -68,7 +83,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; }; &dsi_nt37801_amoled_cmd { From 14871db80d3cf61d59d4b5401cff84bd2db7143f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 1 Oct 2024 19:24:50 +0530 Subject: [PATCH 158/242] ARM: dts: msm: enable display on tuna trustedvm platforms Enable display on tuna trustedvm platforms. Change-Id: I0135626484601f55438135f4beeb6d114d50a559 Signed-off-by: Abhinav Saurabh --- ...trustedvm-tuna-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-tuna-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-cdp.dtsi | 161 ++++++++++++++++++ ...edvm-tuna-sde-display-mtp-kiwi-overlay.dts | 18 ++ .../trustedvm-tuna-sde-display-mtp-kiwi.dtsi | 6 + ...trustedvm-tuna-sde-display-mtp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-mtp.dtsi | 156 +++++++++++++++++ ...trustedvm-tuna-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-qrd.dtsi | 106 ++++++++++++ ...trustedvm-tuna-sde-display-rcm-overlay.dts | 18 ++ ...rustedvm-tuna-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-tuna-sde-display-rumi.dtsi | 10 ++ display/trustedvm-tuna-sde-display.dtsi | 28 +++ 13 files changed, 592 insertions(+) create mode 100644 display/trustedvm-tuna-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-qrd.dtsi create mode 100644 display/trustedvm-tuna-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi.dtsi create mode 100644 display/trustedvm-tuna-sde-display.dtsi diff --git a/display/trustedvm-tuna-sde-display-atp-overlay.dts b/display/trustedvm-tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..92d161b3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/display/trustedvm-tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..823d8b0c --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..bd14043b --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..b552bb5d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi new file mode 100644 index 00000000..e9428826 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display-mtp.dtsi" diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..4bd8c860 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>, <8 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp.dtsi b/display/trustedvm-tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..4738255d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/display/trustedvm-tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..5192b5e3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd.dtsi b/display/trustedvm-tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..f456854a --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/display/trustedvm-tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..2f339264 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/display/trustedvm-tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..665cb540 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi.dtsi b/display/trustedvm-tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..e9c1e520 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-tuna-sde-display.dtsi b/display/trustedvm-tuna-sde-display.dtsi new file mode 100644 index 00000000..22b2e5b0 --- /dev/null +++ b/display/trustedvm-tuna-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; From 259a4eb1c2f999cff963a0a33a32f5592f8445e6 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Wed, 23 Oct 2024 10:59:37 +0530 Subject: [PATCH 159/242] ARM: dts: msm: enable display support for vtdr panel on tuna CDP Enable display support for vtdr6130 panel on tuna CDP platform. Change-Id: I38016bc3ab0aaf82c27ae96ba01bd914022d07f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-cdp.dtsi | 62 +++++++ display/tuna-sde-display-cdp.dtsi | 70 ++++++++ display/tuna-sde-display-common.dtsi | 189 ++++++++++++++++++++ display/tuna-sde-display.dtsi | 29 +++ 4 files changed, 350 insertions(+) diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi index bd14043b..06e55839 100644 --- a/display/trustedvm-tuna-sde-display-cdp.dtsi +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -5,6 +5,38 @@ #include "trustedvm-tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -124,6 +156,36 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; }; diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index c275438b..cbc2df0f 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,43 @@ #include "tuna-sde-display.dtsi" +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -146,6 +183,39 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 21e45a58..beb59396 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -27,6 +27,12 @@ #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" #include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" #include "dsi-panel-ext-bridge-1080p.dtsi" #include "tuna-sde-display-pinctrl.dtsi" @@ -121,6 +127,189 @@ /* PHY TIMINGS REVISION YYG with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index cbcbda6f..a3568aac 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -86,6 +86,35 @@ connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; }; +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + &dsi_nt37801_amoled_cmd { qcom,mdss-dsi-display-timings { timing@0 { From a33ce0f8f4d840e5a5667be57cc67486a4441654 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 11 Oct 2024 16:48:54 +0530 Subject: [PATCH 160/242] ARM: dts: msm: enable compilation for tuna trustedvm platforms Enable compilation for tuna trustedvm platforms. Change-Id: I5cf57ec9141fbf614c6ea99affe289d33db0cf68 Signed-off-by: Abhinav Saurabh --- Kbuild | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Kbuild b/Kbuild index dfa6c483..a9b829d6 100644 --- a/Kbuild +++ b/Kbuild @@ -39,6 +39,14 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ display/tuna-sde-display-qrd-overlay.dtbo \ display/tuna-sde-display-rumi-overlay.dtbo \ display/tuna-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rcm-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) From 7e1a9f881b43ee37c1e7950d8bfca74443c3cb2a Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 22 Oct 2024 13:05:22 +0530 Subject: [PATCH 161/242] ARM: dts: msm: add display support for Tuna MTP platforms Add display device tree support for MTP harmonium and MTP NFC platforms for Tuna. Change-Id: I7f7f935295081aabc227cfafba5ab1e0e87a3508 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 4 ++-- ...ustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} | 6 +++--- ...i => trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi} | 0 display/trustedvm-tuna-sde-display-mtp-overlay.dts | 2 +- ....dts => tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} | 6 +++--- ...p-kiwi.dtsi => tuna-sde-display-mtp-kiwi-harmonium.dtsi} | 2 +- display/tuna-sde-display-mtp-overlay.dts | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) rename display/{trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts => trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} (66%) rename display/{trustedvm-tuna-sde-display-mtp-kiwi.dtsi => trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi} (100%) rename display/{tuna-sde-display-mtp-kiwi-overlay.dts => tuna-sde-display-mtp-kiwi-harmonium-overlay.dts} (66%) rename display/{tuna-sde-display-mtp-kiwi.dtsi => tuna-sde-display-mtp-kiwi-harmonium.dtsi} (76%) diff --git a/Kbuild b/Kbuild index a9b829d6..7d9c2e52 100644 --- a/Kbuild +++ b/Kbuild @@ -35,7 +35,7 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ display/tuna-sde-display-atp-overlay.dtbo \ display/tuna-sde-display-cdp-overlay.dtbo \ display/tuna-sde-display-mtp-overlay.dtbo \ - display/tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ display/tuna-sde-display-qrd-overlay.dtbo \ display/tuna-sde-display-rumi-overlay.dtbo \ display/tuna-sde-display-rcm-overlay.dtbo @@ -43,7 +43,7 @@ else dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \ display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \ display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \ - display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \ display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \ display/trustedvm-tuna-sde-display-rcm-overlay.dtbo diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts similarity index 66% rename from display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts rename to display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index b552bb5d..f5aaca03 100644 --- a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -7,12 +7,12 @@ /plugin/; #include "trustedvm-tuna-sde.dtsi" -#include "trustedvm-tuna-sde-display-mtp-kiwi.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi" / { - model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 2>; + qcom,board-id = <8 3>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi similarity index 100% rename from display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi rename to display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts index 4bd8c860..1aa64b70 100644 --- a/display/trustedvm-tuna-sde-display-mtp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -14,5 +14,5 @@ compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 0>, <8 1>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/tuna-sde-display-mtp-kiwi-overlay.dts b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts similarity index 66% rename from display/tuna-sde-display-mtp-kiwi-overlay.dts rename to display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index e826d973..e06a77e4 100644 --- a/display/tuna-sde-display-mtp-kiwi-overlay.dts +++ b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -6,12 +6,12 @@ /dts-v1/; /plugin/; -#include "tuna-sde-display-mtp-kiwi.dtsi" +#include "tuna-sde-display-mtp-kiwi-harmonium.dtsi" / { - model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN"; + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 2>; + qcom,board-id = <8 3>; }; diff --git a/display/tuna-sde-display-mtp-kiwi.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi similarity index 76% rename from display/tuna-sde-display-mtp-kiwi.dtsi rename to display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index ddf34dc6..a4b9235b 100644 --- a/display/tuna-sde-display-mtp-kiwi.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -3,4 +3,4 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ - #include "tuna-sde-display-mtp.dtsi" +#include "tuna-sde-display-mtp.dtsi" diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts index 277cc2e7..49eee65c 100644 --- a/display/tuna-sde-display-mtp-overlay.dts +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -13,5 +13,5 @@ compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; qcom,msm-id = <681 0x10000>, <655 0x10000>; - qcom,board-id = <8 0>, <8 1>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; From b721cc974358dedc5079de4d45aa3272fa503c5b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 28 Oct 2024 13:11:42 +0530 Subject: [PATCH 162/242] ARM: dts: msm: add display support for SM8735P variant in tuna Add display support for SM8735P variant, SOC-ID: 694. Change-Id: I8c7a668727b52e67dabf7f0f4a7464f5ec880a84 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-atp-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-cdp-overlay.dts | 2 +- .../trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-mtp-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-qrd-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-rcm-overlay.dts | 2 +- display/trustedvm-tuna-sde-display-rumi-overlay.dts | 2 +- display/tuna-sde-display-atp-overlay.dts | 2 +- display/tuna-sde-display-cdp-overlay.dts | 2 +- display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts | 2 +- display/tuna-sde-display-mtp-overlay.dts | 2 +- display/tuna-sde-display-qrd-overlay.dts | 2 +- display/tuna-sde-display-rcm-overlay.dts | 2 +- display/tuna-sde-display-rumi-overlay.dts | 2 +- display/tuna-sde.dts | 2 +- 15 files changed, 15 insertions(+), 15 deletions(-) diff --git a/display/trustedvm-tuna-sde-display-atp-overlay.dts b/display/trustedvm-tuna-sde-display-atp-overlay.dts index 92d161b3..0768b294 100644 --- a/display/trustedvm-tuna-sde-display-atp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", "qcom,atp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <33 0>; }; diff --git a/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/display/trustedvm-tuna-sde-display-cdp-overlay.dts index 823d8b0c..191aa7e0 100644 --- a/display/trustedvm-tuna-sde-display-cdp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", "qcom,cdp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <1 0>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index f5aaca03..9b5b7dab 100644 --- a/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 3>; }; diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts index 1aa64b70..f1dfe65f 100644 --- a/display/trustedvm-tuna-sde-display-mtp-overlay.dts +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/display/trustedvm-tuna-sde-display-qrd-overlay.dts index 5192b5e3..40d830d8 100644 --- a/display/trustedvm-tuna-sde-display-qrd-overlay.dts +++ b/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", "qcom,qrd"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <11 0>; }; diff --git a/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/display/trustedvm-tuna-sde-display-rcm-overlay.dts index 2f339264..c357378d 100644 --- a/display/trustedvm-tuna-sde-display-rcm-overlay.dts +++ b/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -13,6 +13,6 @@ model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 0>, <21 1>; }; diff --git a/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/display/trustedvm-tuna-sde-display-rumi-overlay.dts index 665cb540..80b32374 100644 --- a/display/trustedvm-tuna-sde-display-rumi-overlay.dts +++ b/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <655 0x10000>, <694 0x10000>; qcom,board-id = <15 0>; }; diff --git a/display/tuna-sde-display-atp-overlay.dts b/display/tuna-sde-display-atp-overlay.dts index 87105863..99135b48 100644 --- a/display/tuna-sde-display-atp-overlay.dts +++ b/display/tuna-sde-display-atp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna ATP"; compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", "qcom,atp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <33 0>; }; diff --git a/display/tuna-sde-display-cdp-overlay.dts b/display/tuna-sde-display-cdp-overlay.dts index ac83131c..03f5795b 100644 --- a/display/tuna-sde-display-cdp-overlay.dts +++ b/display/tuna-sde-display-cdp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna CDP"; compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", "qcom,cdp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <1 0>; }; diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts index e06a77e4..d33cda40 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts +++ b/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 3>; }; diff --git a/display/tuna-sde-display-mtp-overlay.dts b/display/tuna-sde-display-mtp-overlay.dts index 49eee65c..46106183 100644 --- a/display/tuna-sde-display-mtp-overlay.dts +++ b/display/tuna-sde-display-mtp-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna MTP"; compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", "qcom,mtp"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; }; diff --git a/display/tuna-sde-display-qrd-overlay.dts b/display/tuna-sde-display-qrd-overlay.dts index b422a057..c650759d 100644 --- a/display/tuna-sde-display-qrd-overlay.dts +++ b/display/tuna-sde-display-qrd-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna QRD"; compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", "qcom,qrd"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <11 0>; }; diff --git a/display/tuna-sde-display-rcm-overlay.dts b/display/tuna-sde-display-rcm-overlay.dts index 3adf6685..a3d546fe 100644 --- a/display/tuna-sde-display-rcm-overlay.dts +++ b/display/tuna-sde-display-rcm-overlay.dts @@ -12,6 +12,6 @@ model = "Qualcomm Technologies, Inc. Tuna RCM"; compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", "qcom,rcm"; - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <21 0>, <21 1>; }; diff --git a/display/tuna-sde-display-rumi-overlay.dts b/display/tuna-sde-display-rumi-overlay.dts index d7f33da6..d01e5b1d 100644 --- a/display/tuna-sde-display-rumi-overlay.dts +++ b/display/tuna-sde-display-rumi-overlay.dts @@ -11,6 +11,6 @@ / { model = "Qualcomm Technologies, Inc. Tuna RUMI"; compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; - qcom,msm-id = <655 0x10000>; + qcom,msm-id = <655 0x10000>, <694 0x10000>; qcom,board-id = <15 0>; }; diff --git a/display/tuna-sde.dts b/display/tuna-sde.dts index b9a80b12..e45c8b27 100644 --- a/display/tuna-sde.dts +++ b/display/tuna-sde.dts @@ -9,6 +9,6 @@ #include "tuna-sde.dtsi" / { - qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; qcom,board-id = <0 0>; }; From 459ad4fd04044cb8af16f20c7bfd7ce53719db3a Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Mon, 14 Oct 2024 09:39:36 +0530 Subject: [PATCH 163/242] ARM: dts: msm: update dither count as per hw capability This change updates number of pingpong dither supported for sun target. Change-Id: Ie4685d349e8a56b6fb1017409168347b48145992 Signed-off-by: Mahadevan Signed-off-by: lnxdisplay --- display/sun-sde-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/sun-sde-common.dtsi b/display/sun-sde-common.dtsi index 12270f64..0b0c405c 100644 --- a/display/sun-sde-common.dtsi +++ b/display/sun-sde-common.dtsi @@ -110,7 +110,7 @@ qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>; qcom,sde-dither-off = <0xe0 0xe0 0xe0 - 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; qcom,sde-dither-version = <0x00020000>; qcom,sde-dither-size = <0x20>; From 4f215a58daeeebe59759d19948782fb1fe336090 Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:46:23 +0530 Subject: [PATCH 164/242] ARM: dts: msm: add qcom,dsi-select-sec-sync-clocks property Currently, we are using the qcom,dsi-select-sec-clocks property to select the clock source for secondary display when sync mode is enabled. In the use case, when DPU0 is faulty and DPU1 is working, the clock source of the secondary display needs to be changed from _mclk to _clk2. Add a new property called qcom,dsi-select-sec-sync-clocks to specify the clock source of the secondary display when running in sync mode with dual DPU. This way, existing "qcom,dsi-select- sec-clocks" property can be used as clock source for the secondary display when DPU0 is faulty/disabled. Change-Id: I3ced083b6700921549e7036722a73d7a4f1f41e5 Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- bindings/sde-dsi.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml index 6e85620c..ebf4c9b8 100644 --- a/bindings/sde-dsi.yaml +++ b/bindings/sde-dsi.yaml @@ -263,6 +263,10 @@ properties: qcom,dsi-select-sec-clocks: description: Specifies the required clocks to use for secondary panel + qcom,dsi-select-sec-sync-clocks: + description: Specifies the required clocks to use for secondary + panel when sync mode is enabled. + qcom,dsi-display-list: description: Specifies the list of supported displays. $ref: /schemas/types.yaml#/definitions/string-array From 4a86f982acd4fad1673f67aa1809bab7db31ea85 Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Thu, 26 Sep 2024 18:38:31 +0530 Subject: [PATCH 165/242] ARM: dts: msm: update documentation for qcom,mdp Use "qcom,mdp" to specify the list of phandles for all the DPU instances. This will enable a DSI display driver to know all the DPUs present in the system. This can also be used to differentiate single DPU and dual DPU usecases based on number of MDPs enabled. Change-Id: I668c971b4e227d4a0c8fa321ed624bc45a43b163 Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- bindings/sde-dsi.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bindings/sde-dsi.yaml b/bindings/sde-dsi.yaml index ebf4c9b8..9ff4625e 100644 --- a/bindings/sde-dsi.yaml +++ b/bindings/sde-dsi.yaml @@ -192,7 +192,7 @@ properties: description: Specifies the default panel. qcom,mdp: - description: Specifies the mdp node which can find panel node from this. + description: Specifies the list of phandles to all sde kms device nodes. qcom,demura-panel-id: description: | From 984fda4d7d77fc3b6225cfee7fd06fd0cbda79ea Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 25 Oct 2024 13:35:06 +0530 Subject: [PATCH 166/242] ARM: dts: msm: add initial dsi display nodes for Kera Add initial dsi display nodes for Kera. Change-Id: I09194c34f8ac1ec6d606879267b1732a72c0cd4e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 149 ++++++++++++++++++++++++++++++++++ display/kera-sde-display.dtsi | 147 +++++++++++++++++++++++++++++++++ display/kera-sde.dts | 14 ++++ display/kera-sde.dtsi | 58 +++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 display/kera-sde-common.dtsi create mode 100644 display/kera-sde-display.dtsi create mode 100644 display/kera-sde.dts create mode 100644 display/kera-sde.dtsi diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi new file mode 100644 index 00000000..4f0e2247 --- /dev/null +++ b/display/kera-sde-common.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi new file mode 100644 index 00000000..2159dfde --- /dev/null +++ b/display/kera-sde-display.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "kera-sde-display-common.dtsi" + +&soc { +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 2>, + <&mdss_dsi_phy1 3>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/display/kera-sde.dts b/display/kera-sde.dts new file mode 100644 index 00000000..f6c6ae21 --- /dev/null +++ b/display/kera-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde.dtsi" + +/ { + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi new file mode 100644 index 00000000..38714fa9 --- /dev/null +++ b/display/kera-sde.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; From 4eced6e8c62d19d61ad393199f8b2e8ed221031e Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Mon, 28 Oct 2024 14:07:38 +0530 Subject: [PATCH 167/242] ARM: dts: msm: add initial dp display nodes for Kera target Add initial dp display nodes for Kera target. Change-Id: Ic1b7abe71ae58b414c5d51a10d4b99a3c1e862cb Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: lnxdisplay --- display/kera-sde.dtsi | 169 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 38714fa9..83cf63be 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -3,11 +3,180 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include #include +#include #include +#include #include "kera-sde-common.dtsi" &soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "disabled"; + + //usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L7K>; + vdda_usb-0p9-supply = <&L7K>; + //vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; }; &mdss_mdp { From 9739f4c25ed29a6c9a22b86f77508a8c8d8a3672 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 23 Sep 2024 17:38:41 +0800 Subject: [PATCH 168/242] ARM: dts: msm: enable 4-3-2 topology for sharp 4k Enable 4-3-2 topology for both cmd and video mode on sharp 4k panel for sun target. Change-Id: I76dca958eea693d495c17320c56922f9a9ffa74b Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-common.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index c8c82641..cb197717 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -763,7 +763,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 05 06 02 04 00 12 0a]; - qcom,display-topology = <2 2 2>; + qcom,display-topology = <2 2 2>, + <4 3 2>; qcom,default-topology-index = <0>; }; }; @@ -784,7 +785,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 06 07 02 04 00 15 0b]; - qcom,display-topology = <2 2 2>; + qcom,display-topology = <2 2 2>, + <4 3 2>; qcom,default-topology-index = <0>; }; }; From d83ba874286f3531d5bad1da2d20a964d8d4a4b7 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Thu, 24 Oct 2024 18:21:09 +0800 Subject: [PATCH 169/242] ARM: dts: msm: add sharp QHD plus cmd/video mode panel support This change added sharp QHD plus cmd/video mode panel support. Change-Id: Id0420be23cbc583500fe280d410e1a568e03f9a1 Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi | 211 ++++++++++++++++++ .../dsi-panel-sharp-dsc-qhd-plus-video.dtsi | 204 +++++++++++++++++ 2 files changed, 415 insertions(+) create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi create mode 100644 display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi new file mode 100644 index 00000000..ff0dfc0f --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_cmd: qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp qhd cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-mdp-transfer-time-us = <7933>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 44 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi new file mode 100644 index 00000000..00a7ea92 --- /dev/null +++ b/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_video: qcom,mdss_dsi_sharp_qhd_plus_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; From d0f765f345060fc244944b1150f1a2f940a93d1e Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Wed, 25 Sep 2024 17:02:58 +0800 Subject: [PATCH 170/242] ARM: dts: msm: enable 4-4-2 topology for sharp QHD plus panel This change enabled 4LM and 4DSC topology for sharp QHD plus panel. Change-Id: I3f6c348c6235575c2b14ac73d5ac50c19b1acc1c Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-cdp.dtsi | 26 ++++++++++++++++++++++++-- display/sun-sde-display-common.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/display/sun-sde-display-cdp.dtsi b/display/sun-sde-display-cdp.dtsi index b2dd5503..9ec15fff 100644 --- a/display/sun-sde-display-cdp.dtsi +++ b/display/sun-sde-display-cdp.dtsi @@ -236,6 +236,24 @@ qcom,platform-bklight-en-gpio = <&tlmm 100 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -295,7 +313,9 @@ &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd &dsi_nt37801_amoled_cmd_ddicspr - &dsi_nt37801_amoled_video_ddicspr>; + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; @@ -314,6 +334,8 @@ &dsi_nt37801_amoled_qsync_video &dsi_nt37801_amoled_fhd_plus_cmd &dsi_nt37801_amoled_cmd_ddicspr - &dsi_nt37801_amoled_video_ddicspr>; + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; }; }; diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index cb197717..98eaab75 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -20,6 +20,8 @@ #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" #include "dsi-panel-sharp-dsc-4k-cmd.dtsi" #include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-dsc-10bit-cmd.dtsi" @@ -792,6 +794,30 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,poms-align-panel-vsync; From 7d2f2106a6cd58308b19c35eea2227ad0b3d4198 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 11 Nov 2024 11:58:50 +0530 Subject: [PATCH 171/242] ARM: dts: msm: add display DT node for Kera target This change adds display DT node for Kera target. Change-Id: I19694c8cd0fc9c684fe21edcd21cd7b5035f502e Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 317 ++++++++++++++++++++++++++++++++++ display/kera-sde-display.dtsi | 9 +- display/kera-sde.dtsi | 64 +++++++ 3 files changed, 389 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index 4f0e2247..b3621384 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -7,6 +7,323 @@ &soc { mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x2>; + qcom,sde-ubwc-version = <0x40000000>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <6800000>; + qcom,sde-max-bw-high-kbps = <14200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-num-ddr-channels = <2>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x7>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 2159dfde..cbb5d7de 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -7,6 +7,13 @@ #include "kera-sde-display-common.dtsi" &soc { + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &sde_dsi { @@ -68,7 +75,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 83cf63be..f9a5b91c 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -9,6 +9,8 @@ #include #include #include "kera-sde-common.dtsi" +#include +#include &soc { ext_disp: qcom,msm-ext-disp { @@ -177,9 +179,71 @@ }; }; }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; }; &mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "branch_clk", "core_clk", "vsync_clk", + "lut_clk"; + clock-rate = <0 0 660000000 660000000 19200000 660000000>; + clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + + qcom,hw-fence-sw-version = <0x1>; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 1600000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; }; &mdss_dsi0 { From 91808d9891afdd2cb946203ca8bb88af87280d27 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 5 Nov 2024 07:41:22 +0530 Subject: [PATCH 172/242] ARM: dts: msm: enable display on kera trustedvm platforms Enable display on kera trustedvm platforms. Change-Id: I76a769baa8726f24a391b612b6558d8322e96527 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- ...trustedvm-kera-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-kera-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-cdp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-mtp-overlay.dts | 19 +++ display/trustedvm-kera-sde-display-mtp.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-kera-sde-display-qrd.dtsi | 156 ++++++++++++++++++ ...trustedvm-kera-sde-display-rcm-overlay.dts | 19 +++ ...rustedvm-kera-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-kera-sde-display-rumi.dtsi | 10 ++ display/trustedvm-kera-sde-display.dtsi | 28 ++++ display/trustedvm-kera-sde.dtsi | 44 +++++ 12 files changed, 659 insertions(+) create mode 100644 display/trustedvm-kera-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-cdp.dtsi create mode 100644 display/trustedvm-kera-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-mtp.dtsi create mode 100644 display/trustedvm-kera-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-qrd.dtsi create mode 100644 display/trustedvm-kera-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-kera-sde-display-rumi.dtsi create mode 100644 display/trustedvm-kera-sde-display.dtsi create mode 100644 display/trustedvm-kera-sde.dtsi diff --git a/display/trustedvm-kera-sde-display-atp-overlay.dts b/display/trustedvm-kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..362e7d57 --- /dev/null +++ b/display/trustedvm-kera-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp-overlay.dts b/display/trustedvm-kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..07e44da0 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp-overlay.dts b/display/trustedvm-kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..073f3342 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/display/trustedvm-kera-sde-display-mtp.dtsi b/display/trustedvm-kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd-overlay.dts b/display/trustedvm-kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..e2f6b39c --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/trustedvm-kera-sde-display-qrd.dtsi b/display/trustedvm-kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..77b43890 --- /dev/null +++ b/display/trustedvm-kera-sde-display-qrd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/trustedvm-kera-sde-display-rcm-overlay.dts b/display/trustedvm-kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..20c01be8 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi-overlay.dts b/display/trustedvm-kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..0374cc20 --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-kera-sde-display-rumi.dtsi b/display/trustedvm-kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..6bf94fae --- /dev/null +++ b/display/trustedvm-kera-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi new file mode 100644 index 00000000..e6420a52 --- /dev/null +++ b/display/trustedvm-kera-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +}; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi new file mode 100644 index 00000000..9b88fd38 --- /dev/null +++ b/display/trustedvm-kera-sde.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { +}; + +&mdss_mdp { +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; From 738b90d9fe7b934d8910f9a5ba773b22637cf124 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 1 Nov 2024 16:05:56 +0530 Subject: [PATCH 173/242] ARM: dts: msm: enable display on kera platforms Enable display on kera platforms. Change-Id: I40b6a9f002a72a527e2cbe61f0f59f059ad5716e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 10 + ...-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi | 156 +++ ...anel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi | 134 +++ ...-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi | 262 +++++ ...anel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi | 134 +++ display/kera-sde-display-atp-overlay.dts | 17 + display/kera-sde-display-cdp-overlay.dts | 17 + display/kera-sde-display-cdp.dtsi | 185 ++++ display/kera-sde-display-common.dtsi | 942 ++++++++++++++++++ display/kera-sde-display-mtp-overlay.dts | 18 + display/kera-sde-display-mtp.dtsi | 185 ++++ display/kera-sde-display-pinctrl.dtsi | 114 +++ display/kera-sde-display-qrd-overlay.dts | 17 + display/kera-sde-display-qrd.dtsi | 185 ++++ display/kera-sde-display-rcm-overlay.dts | 18 + display/kera-sde-display-rumi-overlay.dts | 16 + display/kera-sde-display-rumi.dtsi | 11 + display/kera-sde-display.dtsi | 8 +- display/kera-sde.dtsi | 2 - 19 files changed, 2425 insertions(+), 6 deletions(-) create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi create mode 100644 display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi create mode 100644 display/kera-sde-display-atp-overlay.dts create mode 100644 display/kera-sde-display-cdp-overlay.dts create mode 100644 display/kera-sde-display-cdp.dtsi create mode 100644 display/kera-sde-display-common.dtsi create mode 100644 display/kera-sde-display-mtp-overlay.dts create mode 100644 display/kera-sde-display-mtp.dtsi create mode 100644 display/kera-sde-display-pinctrl.dtsi create mode 100644 display/kera-sde-display-qrd-overlay.dts create mode 100644 display/kera-sde-display-qrd.dtsi create mode 100644 display/kera-sde-display-rcm-overlay.dts create mode 100644 display/kera-sde-display-rumi-overlay.dts create mode 100644 display/kera-sde-display-rumi.dtsi diff --git a/Kbuild b/Kbuild index 7d9c2e52..3c212c66 100644 --- a/Kbuild +++ b/Kbuild @@ -49,6 +49,16 @@ dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo display/trustedvm-tuna-sde-display-rcm-overlay.dtbo endif +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ + display/kera-sde-display-atp-overlay.dtbo \ + display/kera-sde-display-cdp-overlay.dtbo \ + display/kera-sde-display-mtp-overlay.dtbo \ + display/kera-sde-display-qrd-overlay.dtbo \ + display/kera-sde-display-rumi-overlay.dtbo \ + display/kera-sde-display-rcm-overlay.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi new file mode 100644 index 00000000..17c9b05f --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <353116800>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 00000000..806b30eb --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 00000000..d465d706 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 00000000..286080d3 --- /dev/null +++ b/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/display/kera-sde-display-atp-overlay.dts b/display/kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..055789c5 --- /dev/null +++ b/display/kera-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/kera-sde-display-cdp-overlay.dts b/display/kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..52f5b3d9 --- /dev/null +++ b/display/kera-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-cdp.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi new file mode 100644 index 00000000..f6710815 --- /dev/null +++ b/display/kera-sde-display-common.dtsi @@ -0,0 +1,942 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" + +#include "kera-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <2000000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3544000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <1>; + qcom,supply-post-off-sleep = <2>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + qcom,supply-enable-load = <200000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-post-off-sleep = <2>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 17 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 121 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ + +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/display/kera-sde-display-mtp-overlay.dts b/display/kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..1eb193fa --- /dev/null +++ b/display/kera-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-mtp.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-pinctrl.dtsi b/display/kera-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..0a7180d8 --- /dev/null +++ b/display/kera-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/display/kera-sde-display-qrd-overlay.dts b/display/kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..04a7ea38 --- /dev/null +++ b/display/kera-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..e4091be5 --- /dev/null +++ b/display/kera-sde-display-qrd.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; diff --git a/display/kera-sde-display-rcm-overlay.dts b/display/kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..24277d00 --- /dev/null +++ b/display/kera-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/display/kera-sde-display-rumi-overlay.dts b/display/kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..8c8643b2 --- /dev/null +++ b/display/kera-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/kera-sde-display-rumi.dtsi b/display/kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..177e852b --- /dev/null +++ b/display/kera-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index cbb5d7de..f2942b9c 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -19,8 +19,8 @@ &sde_dsi { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe @@ -48,8 +48,8 @@ &sde_dsi1 { clocks = <&mdss_dsi_phy0 0>, <&mdss_dsi_phy0 1>, - <&mdss_dsi_phy1 2>, - <&mdss_dsi_phy1 3>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, /* * Currently the dsi clock handles are under the dsi * controller DT node. As soon as the controller probe diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index f9a5b91c..b18d8140 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -248,7 +248,6 @@ &mdss_dsi0 { vdda-1p2-supply = <&L4B>; - qcom,split-link-supported; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -262,7 +261,6 @@ &mdss_dsi1 { vdda-1p2-supply = <&L4B>; - qcom,split-link-supported; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, From 51764b0a87edb2e413503fe81633fb38d649b1dd Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Sun, 17 Nov 2024 15:00:36 +0530 Subject: [PATCH 174/242] ARM: dts: msm: add smmu_sde_unsec to connector list This change adds smmu_sde_unsec to connector list for trustedvm platform in tuna target. Change-Id: I86cba1f15319a502450f8b89b9bb96409869a821 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/display/trustedvm-tuna-sde-display.dtsi b/display/trustedvm-tuna-sde-display.dtsi index 22b2e5b0..56e90443 100644 --- a/display/trustedvm-tuna-sde-display.dtsi +++ b/display/trustedvm-tuna-sde-display.dtsi @@ -24,5 +24,5 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; }; From 4d9b336136db4c40ebf3688dcc41e9ba39aa4f44 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Fri, 15 Nov 2024 10:53:05 +0530 Subject: [PATCH 175/242] ARM: dts: msm: enable touch support for Kera display Enable touch support for Kera on CDP, MTP and QRD platforms. Change-Id: Ica6505a62ca407001b6cbaaac8d5b738acd92fc7 Signed-off-by: Anand Tarakh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 15 +++++++++++++++ display/kera-sde-display-mtp.dtsi | 15 +++++++++++++++ display/kera-sde-display-qrd.dtsi | 15 +++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-mtp.dtsi +++ b/display/kera-sde-display-mtp.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi index e4091be5..efb7d0d3 100644 --- a/display/kera-sde-display-qrd.dtsi +++ b/display/kera-sde-display-qrd.dtsi @@ -183,3 +183,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; From 1fbdd896c40bf1f1c6ec5e014b1e9557c7ea35c7 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 24 Oct 2024 11:09:38 +0530 Subject: [PATCH 176/242] ARM: dts: msm: Enable DP for Tuna CDP, QRD, and MTP platforms Enable DP support for MTP Harmonium, QRD, and CDP platforms for Tuna. Change-Id: I1cf8ff5a64f2d71df8e3247679ed03625aedee44 Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: Ritesh Kumar Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 8 ++++++++ display/tuna-sde-display-mtp-kiwi-harmonium.dtsi | 8 ++++++++ display/tuna-sde-display-qrd.dtsi | 8 ++++++++ display/tuna-sde.dtsi | 7 ++++--- 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index cbc2df0f..e18d17f2 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -260,6 +260,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_i2c { st_fts@49 { panel = <&dsi_nt37801_amoled_cmd diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index a4b9235b..afb97cbc 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -4,3 +4,11 @@ */ #include "tuna-sde-display-mtp.dtsi" + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 13de5d6f..0598d2ac 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -125,6 +125,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_spi { st_fts@0 { panel = <&dsi_nt37801_amoled_cmd_cphy diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 79fb22e3..2387ccee 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -34,10 +34,11 @@ compatible = "qcom,dp-display"; status = "disabled"; - //usb-phy = <&usb_qmp_dp_phy>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -104,7 +105,7 @@ vdda-1p2-supply = <&L4B>; vdda-0p9-supply = <&L3B>; vdda_usb-0p9-supply = <&L3B>; - //vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, @@ -133,7 +134,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <30000>; qcom,supply-disable-load = <0>; }; From 93cee5f4cbc95d0c7626127af8ac89a651be750b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 25 Nov 2024 11:55:48 +0530 Subject: [PATCH 177/242] ARM: dts: msm: update dsi supply voltage for kera Update DSI and panel supply voltage configuration as per the recent change in the supplier regulators for Kera. Change-Id: I512d381d4bf7e0a6b0d171736af872c7f45eeb74 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 4 ++-- display/kera-sde-display-common.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index b3621384..53bd54c2 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -346,7 +346,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -372,7 +372,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index f6710815..8fec279c 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -48,7 +48,7 @@ reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <2000000>; + qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <220000>; qcom,supply-disable-load = <8000>; qcom,supply-post-on-sleep = <20>; From 2c8658563ea6ca61d95cdafcd24a362845da2490 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 11 Nov 2024 12:04:28 +0530 Subject: [PATCH 178/242] ARM: dts: msm: add display node in trustedvm platform This change adds display node in trustedvm platform on Kera target. Change-Id: Ibe2c60bcb34bdedee75f7b8fa163a8aacb204562 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-kera-sde-display.dtsi | 2 +- display/trustedvm-kera-sde.dtsi | 37 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi index e6420a52..8ec7d0f1 100644 --- a/display/trustedvm-kera-sde-display.dtsi +++ b/display/trustedvm-kera-sde-display.dtsi @@ -24,5 +24,5 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; }; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 9b88fd38..3740746b 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -8,9 +8,46 @@ #include "kera-sde-common.dtsi" &soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; }; &mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0xC0040000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From ef1f3c4062fcf51f3afc371b9ac6d876b4968f4f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Sat, 23 Nov 2024 18:50:16 +0530 Subject: [PATCH 179/242] ARM: dts: msm: enable compilation for kera trustedvm platforms Enable compilation for kera trustedvm platforms. Change-Id: I7f05e7e7d6f245707db30e6315ff5cb46e1438f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Kbuild b/Kbuild index 3c212c66..31654078 100644 --- a/Kbuild +++ b/Kbuild @@ -57,6 +57,13 @@ dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ display/kera-sde-display-qrd-overlay.dtbo \ display/kera-sde-display-rumi-overlay.dtbo \ display/kera-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-kera-sde-display-atp-overlay.dtbo \ + display/trustedvm-kera-sde-display-cdp-overlay.dtbo \ + display/trustedvm-kera-sde-display-mtp-overlay.dtbo \ + display/trustedvm-kera-sde-display-qrd-overlay.dtbo \ + display/trustedvm-kera-sde-display-rumi-overlay.dtbo \ + display/trustedvm-kera-sde-display-rcm-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) From c56ffa64e79e8270a0ea56f9fb40c602555676cb Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 2 Dec 2024 17:22:01 +0530 Subject: [PATCH 180/242] ARM: dts: msm: update UBWC HBB configuration for kera This change updates UBWC highest bank bit configuration for kera target. Change-Id: Ie0ef2bea85d9e2ce542cef4fa3de97ccf93596a0 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index 53bd54c2..c54b3b69 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -150,7 +150,8 @@ qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-wb-linewidth-linear = <8192>; qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x8 0x2>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; qcom,sde-ubwc-version = <0x40000000>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; From 78a57f6b4d5eb2f884c5e8a000b4a6162781c74d Mon Sep 17 00:00:00 2001 From: Srihitha Tangudu Date: Mon, 25 Nov 2024 11:53:03 +0530 Subject: [PATCH 181/242] ARM: dts: msm: dynamic clock switch with specific HFP/VFP adjustment Add new dynamic clock types "adjust-hfp" and "adjust-vfp" to facilitate specific hfp/vfp adjustment as per "qcom,dsi-dyn-hfp-list" and "qcom,dsi-dyn-vfp-list" respectively corresponding to bit clock rates of "qcom,dsi-dyn-clk-list". FPS might not be maintained in these cases. Change-Id: Ic225624fb5e0bee0d8b099f2e955f65768371d4b Signed-off-by: Srihitha Tangudu Signed-off-by: lnxdisplay --- bindings/mdss-dsi-panel.yaml | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/bindings/mdss-dsi-panel.yaml b/bindings/mdss-dsi-panel.yaml index 20ae28ff..accf1822 100644 --- a/bindings/mdss-dsi-panel.yaml +++ b/bindings/mdss-dsi-panel.yaml @@ -543,6 +543,12 @@ properties: "constant-fps-adjust-vfp" = FPS is maintained even after dynamic clock switch by changing panel vertical front porch values. + "adjust-hfp" = Dynamic clock switch is achieved by adjusting the + horizontal front porch value according to the qcom,dsi-dyn-hfp-list. + FPS may not be maintained after the switch. + "adjust-vfp" = Dynamic clock switch is achieved by adjusting the + vertical front porch value according to the qcom,dsi-dyn-vfp-list. + FPS may not be maintatined after the switch. This dyn-clk-type entry is an optional binding which is contingent on the enabling of dynamic clock switch. $ref: /schemas/types.yaml#/definitions/string-array @@ -1713,6 +1719,24 @@ properties: order of preference. $ref: /schemas/types.yaml#/definitions/uint32-array + qcom,dsi-dyn-clk-hfp-list: + description: > + An u32 array of horizontal front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-hfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-dyn-clk-vfp-list: + description: > + An u32 array of vertical front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-vfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + qcom,disable-rsc-solver: description: > Timing node property to dynamically disable RSC solver for @@ -1908,7 +1932,7 @@ examples: qcom,platform-reset-gpio = <&tlmm 0 0>; qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + qcom,dsi-dyn-clk-type = "adjust-hfp"; qcom,mdss-dsi-display-timings { wqhd { @@ -1988,6 +2012,7 @@ examples: qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + qcom,dsi-dyn-clk-hfp-list = <52 64 96>; qcom,vert-padding-value = <2940>; qcom,mdss-dsc-slice-height = <16>; From ce0c7bb029e58e081495392bd318ddc6d13032d0 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Wed, 4 Dec 2024 15:43:19 +0530 Subject: [PATCH 182/242] ARM: dts: msm: add support for sw fuse for Kera target Add sw fuse range to dts file for Kera target. The swfuse_phys is only needed in primary VM. Change-Id: If8e58f86f15960633c2e058342d15c307dcc738c Signed-off-by: Sanskar Omar Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 6 ++++-- display/kera-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index c54b3b69..a2822e3e 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x140>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index b18d8140..22362ce2 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -228,7 +228,7 @@ qti,smmu-proxy-cb-id = ; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From 165cb0eb23cd111b66c09db1662708fd0a09a894 Mon Sep 17 00:00:00 2001 From: Sanskar Omar Date: Wed, 4 Dec 2024 15:29:42 +0530 Subject: [PATCH 183/242] ARM: dts: msm: add support for sw fuse for Tuna target Add sw fuse range to dts file for Tuna target. The swfuse_phys is only needed in primary VM. Change-Id: Ida97d23c3f0634864829ea8f7ea91e388062eb4c Signed-off-by: Sanskar Omar Signed-off-by: lnxdisplay --- display/tuna-sde-common.dtsi | 6 ++++-- display/tuna-sde.dtsi | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index e2a5d2f5..e3098929 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -13,11 +13,13 @@ reg = <0x0ae00000 0x93800>, <0x0aeb0000 0x2008>, <0x0af80000 0x7000>, - <0x400000 0x2000>; + <0x400000 0x2000>, + <0x0af50000 0x140>; reg-names = "mdp_phys", "vbif_phys", "regdma_phys", - "ipcc_reg"; + "ipcc_reg", + "swfuse_phys"; /* interrupt config */ interrupts = ; diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 2387ccee..6567fb17 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -231,7 +231,7 @@ qti,smmu-proxy-cb-id = ; - qcom,sde-vm-exclude-reg-names = "ipcc_reg"; + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; /* data and reg bus scale settings */ interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, From 33b1c55941c4e1b31d2a2db6e35abec50827b6f0 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Tue, 19 Nov 2024 19:53:06 +0530 Subject: [PATCH 184/242] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: Ia50ffd92a35f13219877a73698ca6defa28dd2de Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/tuna-sde-display.dtsi | 12 ++++++++++++ display/tuna-sde.dtsi | 1 + 2 files changed, 13 insertions(+) diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index a3568aac..ce534cc8 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -22,6 +22,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 6567fb17..f9db998d 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From e30c954b9f32935ceeb128e7bf1a6e97ba7c1283 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Thu, 24 Oct 2024 11:09:38 +0530 Subject: [PATCH 185/242] ARM: dts: msm: Enable DP for Tuna CDP, QRD, and MTP platforms Enable DP support for MTP Harmonium, QRD, and CDP platforms for Tuna. Change-Id: I1cf8ff5a64f2d71df8e3247679ed03625aedee44 Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: Ritesh Kumar --- display/tuna-sde-display-cdp.dtsi | 8 ++++++++ display/tuna-sde-display-mtp-kiwi-harmonium.dtsi | 8 ++++++++ display/tuna-sde-display-qrd.dtsi | 8 ++++++++ display/tuna-sde.dtsi | 7 ++++--- 4 files changed, 28 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index cbc2df0f..e18d17f2 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -260,6 +260,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_i2c { st_fts@49 { panel = <&dsi_nt37801_amoled_cmd diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index a4b9235b..afb97cbc 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -4,3 +4,11 @@ */ #include "tuna-sde-display-mtp.dtsi" + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 13de5d6f..0598d2ac 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -125,6 +125,14 @@ qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; }; +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; +}; + &qupv3_se4_spi { st_fts@0 { panel = <&dsi_nt37801_amoled_cmd_cphy diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 79fb22e3..2387ccee 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -34,10 +34,11 @@ compatible = "qcom,dp-display"; status = "disabled"; - //usb-phy = <&usb_qmp_dp_phy>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -104,7 +105,7 @@ vdda-1p2-supply = <&L4B>; vdda-0p9-supply = <&L3B>; vdda_usb-0p9-supply = <&L3B>; - //vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, @@ -133,7 +134,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1300000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <30000>; qcom,supply-disable-load = <0>; }; From b2575f1a14052270aa68d4fe4d849462391f4b61 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Tue, 19 Nov 2024 19:53:06 +0530 Subject: [PATCH 186/242] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: Ia50ffd92a35f13219877a73698ca6defa28dd2de Signed-off-by: Sampurna Bolloju --- display/tuna-sde-display.dtsi | 12 ++++++++++++ display/tuna-sde.dtsi | 1 + 2 files changed, 13 insertions(+) diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index a3568aac..ce534cc8 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -22,6 +22,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 2387ccee..4881ebc2 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 3d64224baa2b16deace5fc00d3e84b16a60635d1 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Thu, 21 Nov 2024 10:01:50 +0530 Subject: [PATCH 187/242] ARM: dts: msm: enable display cesta on tuna target Add display cesta related DT node on tuna target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: Ifa9f0b4500c5e6b453395bcf1de492e332d63306 Signed-off-by: Sampurna Bolloju --- display/trustedvm-tuna-sde.dtsi | 9 ++++++ display/tuna-sde-display.dtsi | 3 +- display/tuna-sde.dtsi | 54 ++++++++++++++++++++++++++++----- 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/display/trustedvm-tuna-sde.dtsi b/display/trustedvm-tuna-sde.dtsi index 79d85eab..e07423fe 100644 --- a/display/trustedvm-tuna-sde.dtsi +++ b/display/trustedvm-tuna-sde.dtsi @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index ce534cc8..b905f813 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -95,7 +95,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 4881ebc2..a900029f 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ; From 4ac686f6377d2d8e76b0a1758bcaa970d89a59b1 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 2 Dec 2024 17:22:01 +0530 Subject: [PATCH 188/242] ARM: dts: msm: update UBWC HBB configuration for kera This change updates UBWC highest bank bit configuration for kera target. Change-Id: Ie0ef2bea85d9e2ce542cef4fa3de97ccf93596a0 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index b3621384..863f3f57 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -150,7 +150,8 @@ qcom,sde-max-dest-scaler-output-linewidth = <2560>; qcom,sde-wb-linewidth-linear = <8192>; qcom,sde-mixer-blendstages = <0xb>; - qcom,sde-highest-bank-bit = <0x8 0x2>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; qcom,sde-ubwc-version = <0x40000000>; qcom,sde-ubwc-swizzle = <0x6>; qcom,sde-ubwc-bw-calc-version = <0x1>; From e33e96c9ffbecbb4d48a0f5b67aff4d68dcf7f61 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 25 Nov 2024 11:55:48 +0530 Subject: [PATCH 189/242] ARM: dts: msm: update dsi supply voltage for kera Update DSI and panel supply voltage configuration as per the recent change in the supplier regulators for Kera. Change-Id: I512d381d4bf7e0a6b0d171736af872c7f45eeb74 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-common.dtsi | 4 ++-- display/kera-sde-display-common.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index 863f3f57..c54b3b69 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -347,7 +347,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; @@ -373,7 +373,7 @@ reg = <0>; qcom,supply-name = "vdda-1p2"; qcom,supply-min-voltage = <1200000>; - qcom,supply-max-voltage = <1320000>; + qcom,supply-max-voltage = <1200000>; qcom,supply-enable-load = <16600>; qcom,supply-disable-load = <0>; }; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index f6710815..8fec279c 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -48,7 +48,7 @@ reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <2000000>; + qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <220000>; qcom,supply-disable-load = <8000>; qcom,supply-post-on-sleep = <20>; From 8faa1b933e23e08f839fbd3ebc9b93a7dd6dd32c Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Sat, 23 Nov 2024 18:50:16 +0530 Subject: [PATCH 190/242] ARM: dts: msm: enable compilation for kera trustedvm platforms Enable compilation for kera trustedvm platforms. Change-Id: I7f05e7e7d6f245707db30e6315ff5cb46e1438f7 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- Kbuild | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Kbuild b/Kbuild index 3c212c66..31654078 100644 --- a/Kbuild +++ b/Kbuild @@ -57,6 +57,13 @@ dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ display/kera-sde-display-qrd-overlay.dtbo \ display/kera-sde-display-rumi-overlay.dtbo \ display/kera-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-kera-sde-display-atp-overlay.dtbo \ + display/trustedvm-kera-sde-display-cdp-overlay.dtbo \ + display/trustedvm-kera-sde-display-mtp-overlay.dtbo \ + display/trustedvm-kera-sde-display-qrd-overlay.dtbo \ + display/trustedvm-kera-sde-display-rumi-overlay.dtbo \ + display/trustedvm-kera-sde-display-rcm-overlay.dtbo endif always-y := $(dtb-y) $(dtbo-y) From b9098e6ae4f8601bfa4c5da8945c5bd7f2ec6dd7 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 11 Nov 2024 12:04:28 +0530 Subject: [PATCH 191/242] ARM: dts: msm: add display node in trustedvm platform This change adds display node in trustedvm platform on Kera target. Change-Id: Ibe2c60bcb34bdedee75f7b8fa163a8aacb204562 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-kera-sde-display.dtsi | 2 +- display/trustedvm-kera-sde.dtsi | 37 +++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/display/trustedvm-kera-sde-display.dtsi b/display/trustedvm-kera-sde-display.dtsi index e6420a52..8ec7d0f1 100644 --- a/display/trustedvm-kera-sde-display.dtsi +++ b/display/trustedvm-kera-sde-display.dtsi @@ -24,5 +24,5 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; }; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 9b88fd38..3740746b 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -8,9 +8,46 @@ #include "kera-sde-common.dtsi" &soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; }; &mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + qcom,sde-hw-version = <0xC0040000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; }; &mdss_dsi0 { From 817e9062974d35c8283c997a476cbce9483407fd Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 2 Dec 2024 13:51:33 +0530 Subject: [PATCH 192/242] ARM: dts: msm: Add display support for Sharp qhd+ panel on Tuna CDP Add display support for Sharp qhd+ panel on Tuna CDP platform. Change-Id: I58a4bccc33cba4a2e471a24c3dfc25c6608a010c Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 62 ++++++++++++++++++++++++++++ display/tuna-sde-display-common.dtsi | 52 +++++++++++++++++++++++ 2 files changed, 114 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index e18d17f2..2827224b 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,49 @@ #include "tuna-sde-display.dtsi" +&pm8550vs_g_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio4"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550vs_f_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio8"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550vs_f_gpios 8 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -216,6 +259,24 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; @@ -257,6 +318,7 @@ }; &sde_dsi { + avdd-supply = <&display_panel_avdd>; qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index beb59396..168db297 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -18,6 +18,8 @@ #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" #include "dsi-panel-sim-cmd.dtsi" #include "dsi-panel-sim-dsc-10bit-cmd.dtsi" @@ -88,6 +90,30 @@ }; }; + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; @@ -713,6 +739,32 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; From acb2ed7db6dbc9e6902059ad4ea40e692723b201 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Wed, 27 Nov 2024 11:26:19 +0530 Subject: [PATCH 193/242] [DNM] ARM: dts: msm: disable all the features for kera SOD Disable all the features of default panels for Kera SOD. Change-Id: I6fc4aa4b5571e1145c46d9eb9ea129fa4c923b47 Signed-off-by: Abhinav Saurabh --- display/kera-sde-display-cdp.dtsi | 2 +- display/kera-sde-display-common.dtsi | 24 ------------------------ display/kera-sde-display-mtp.dtsi | 2 +- display/kera-sde-display-qrd.dtsi | 2 +- 4 files changed, 3 insertions(+), 27 deletions(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index efb7d0d3..9c114ee1 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; }; &qupv3_se8_spi { diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 8fec279c..4ac0e743 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -170,29 +170,18 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; - qcom,dsi-supported-dfps-list = <144 120 90 60>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - - qcom,dsi-dyn-clk-enable; - qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; - - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; - qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; }; }; @@ -238,19 +227,12 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; - qcom,dsi-supported-dfps-list = <120 90 60>; - qcom,mdss-dsi-pan-enable-dynamic-fps; - qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; - - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 @@ -345,15 +327,12 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 @@ -390,15 +369,12 @@ &dsi_vtdr6130_amoled_qsync_144hz_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; - qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-panel-hdr-enabled; - qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi index efb7d0d3..9c114ee1 100644 --- a/display/kera-sde-display-mtp.dtsi +++ b/display/kera-sde-display-mtp.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; }; &qupv3_se8_spi { diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi index efb7d0d3..9c114ee1 100644 --- a/display/kera-sde-display-qrd.dtsi +++ b/display/kera-sde-display-qrd.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; }; &qupv3_se8_spi { From 47ed6ef3f94cfc68c66b41aa98b47864bf85a96e Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Sat, 4 Jan 2025 00:52:48 -0800 Subject: [PATCH 194/242] Revert "[DNM] ARM: dts: msm: disable all the features for kera SOD" This reverts commit acb2ed7db6dbc9e6902059ad4ea40e692723b201. Change-Id: I05f21efb89ccaf128dfa1fe969efa1c2d07b9220 --- display/kera-sde-display-cdp.dtsi | 2 +- display/kera-sde-display-common.dtsi | 24 ++++++++++++++++++++++++ display/kera-sde-display-mtp.dtsi | 2 +- display/kera-sde-display-qrd.dtsi | 2 +- 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 9c114ee1..efb7d0d3 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; &qupv3_se8_spi { diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 4ac0e743..8fec279c 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -170,18 +170,29 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; qcom,display-topology = <2 2 1>; qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; }; }; @@ -227,12 +238,19 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 @@ -327,12 +345,15 @@ qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 @@ -369,12 +390,15 @@ &dsi_vtdr6130_amoled_qsync_144hz_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 diff --git a/display/kera-sde-display-mtp.dtsi b/display/kera-sde-display-mtp.dtsi index 9c114ee1..efb7d0d3 100644 --- a/display/kera-sde-display-mtp.dtsi +++ b/display/kera-sde-display-mtp.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; &qupv3_se8_spi { diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi index 9c114ee1..efb7d0d3 100644 --- a/display/kera-sde-display-qrd.dtsi +++ b/display/kera-sde-display-qrd.dtsi @@ -181,7 +181,7 @@ }; &sde_dsi { - qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_60hz_video>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; &qupv3_se8_spi { From 6d29e3552a54178a5d794038188d6dff08d6e5de Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 9 Dec 2024 11:33:05 +0530 Subject: [PATCH 195/242] ARM: dts: msm: add cesta to connector list on MTP, QRD and CDP platforms This change adds cesta to connectors list on MTP Harmonium, CDP and QRD platforms. Change-Id: I5a4bc421daf5a70ec0b67661d826c6adf5c31a80 Signed-off-by: Sampurna Bolloju --- display/tuna-sde-display-cdp.dtsi | 3 ++- display/tuna-sde-display-mtp-kiwi-harmonium.dtsi | 3 ++- display/tuna-sde-display-qrd.dtsi | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 2827224b..3d5e34aa 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -327,7 +327,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; }; &qupv3_se4_i2c { diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index afb97cbc..17dad919 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -10,5 +10,6 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; }; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 0598d2ac..1ffc9332 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -130,7 +130,9 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; + }; &qupv3_se4_spi { From fd6c3b8d142f1bb64096e9cf09af97834b7d2c63 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Sat, 28 Dec 2024 18:02:08 +0530 Subject: [PATCH 196/242] ARM: dts: msm: Enable DP for Kera CDP, QRD, and MTP platforms Enable DP support for MTP, QRD, and CDP platforms for Kera. Change-Id: I78e1c0ffd842a4ebf0d73f9076c059591036dbaf Signed-off-by: Mani Chandana Ballary Kuntumalla --- display/kera-sde-display.dtsi | 2 +- display/kera-sde.dtsi | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index f2942b9c..9404dfd8 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -75,7 +75,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 22362ce2..0b5dc6c9 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -33,12 +33,13 @@ sde_dp: qcom,dp_display@af54000 { cell-index = <0>; compatible = "qcom,dp-display"; - status = "disabled"; + status = "ok"; - //usb-phy = <&usb_qmp_dp_phy>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -105,7 +106,7 @@ vdda-1p2-supply = <&L4B>; vdda-0p9-supply = <&L7K>; vdda_usb-0p9-supply = <&L7K>; - //vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, From 6fac09aa9f5891a2672742ce73108542b5fa53d0 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Fri, 3 Jan 2025 12:24:22 +0530 Subject: [PATCH 197/242] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326 Signed-off-by: Sailesh Reddy Male --- display/kera-sde-display.dtsi | 14 +++++++++++++- display/kera-sde.dtsi | 3 ++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index f2942b9c..165863d3 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -14,6 +14,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 22362ce2..1146b8d4 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -182,6 +182,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From 2ccf7a76c31e485bfd26da48d21b627a1df2e3b7 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 3 Jan 2025 15:30:22 +0530 Subject: [PATCH 198/242] ARM: dts: msm: update in sharp qhd+ panel GPIO name in tuna Update in Sharp qhd+ panel GPIO name as per recent change from supplier in tuna. Change-Id: I64422b2242d78b73a39ba30a4d5377cd442d20c9 Signed-off-by: Abhinav Saurabh --- display/tuna-sde-display-cdp.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 2827224b..7d8b8db9 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tuna-sde-display.dtsi" -&pm8550vs_g_gpios { +&pm8550vs_d_gpios { lcd_backlight_ctrl { lcd_backlight_en_default: lcd_backlight_en_default { pins = "gpio4"; @@ -19,7 +19,7 @@ }; }; -&pm8550vs_f_gpios { +&pm8550ve_f_gpios { display_panel_avdd_default: display_panel_avdd_default { pins = "gpio8"; function = "normal"; @@ -38,7 +38,7 @@ regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; regulator-enable-ramp-delay = <233>; - gpio = <&pm8550vs_f_gpios 8 0>; + gpio = <&pm8550ve_f_gpios 8 0>; enable-active-high; regulator-boot-on; proxy-supply = <&display_panel_avdd>; @@ -265,7 +265,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 14 0>; - qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; }; &dsi_sharp_qhd_plus_dsc_video { @@ -274,7 +274,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 14 0>; - qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; }; &dsi_sim_cmd { From 01332fcb66640e9b9e2d8933446ea2c0312d46eb Mon Sep 17 00:00:00 2001 From: Spurthy Mutturaj Date: Thu, 29 Aug 2024 10:38:33 -0700 Subject: [PATCH 199/242] ARM: dts: msm: add xo clock to sde_cesta node in sun target Add XO clock to sde_cesta node. This will help to vote XO freq for cesta idle vote for mdp-clk. Change-Id: I33b309ed9ac2d9013fee8f071c5f07938e651e5f Signed-off-by: Spurthy Mutturaj Signed-off-by: Sampurna Bolloju --- display/sun-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5dda611..f1e10426 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -226,12 +226,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <575000000 575000000>; - clock-max-rate = <575000000 575000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk","xo"; + clock-rate = <575000000 575000000 19200000>; + clock-max-rate = <575000000 575000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From fc4b7903f4876423d5f41cf2123ed1af0ffd6b2b Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Thu, 21 Nov 2024 10:01:50 +0530 Subject: [PATCH 200/242] ARM: dts: msm: enable display cesta on tuna target Add display cesta related DT node on tuna target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: Ifa9f0b4500c5e6b453395bcf1de492e332d63306 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde.dtsi | 9 ++++++ display/tuna-sde-display.dtsi | 3 +- display/tuna-sde.dtsi | 54 ++++++++++++++++++++++++++++----- 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/display/trustedvm-tuna-sde.dtsi b/display/trustedvm-tuna-sde.dtsi index 79d85eab..e07423fe 100644 --- a/display/trustedvm-tuna-sde.dtsi +++ b/display/trustedvm-tuna-sde.dtsi @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version =<0xC0000000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index ce534cc8..b905f813 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -95,7 +95,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index f9db998d..a1de8490 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-mmrm = <0 0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; mmcx-supply = <&VDD_MMCX_LEVEL>; qti,smmu-proxy-cb-id = ; From be33284342dd8287c40e79cead7c710f156c5c92 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Mon, 9 Dec 2024 11:33:05 +0530 Subject: [PATCH 201/242] ARM: dts: msm: add cesta to connector list on MTP, QRD and CDP platforms This change adds cesta to connectors list on MTP Harmonium, CDP and QRD platforms. Change-Id: I5a4bc421daf5a70ec0b67661d826c6adf5c31a80 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 3 ++- display/tuna-sde-display-mtp-kiwi-harmonium.dtsi | 3 ++- display/tuna-sde-display-qrd.dtsi | 4 +++- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 2827224b..3d5e34aa 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -327,7 +327,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; }; &qupv3_se4_i2c { diff --git a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi index afb97cbc..17dad919 100644 --- a/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi +++ b/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -10,5 +10,6 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; }; diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 0598d2ac..1ffc9332 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -130,7 +130,9 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; + }; &qupv3_se4_spi { From be951b936323279c58eaa56f95775c11bf2e44cf Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Fri, 10 Jan 2025 14:35:41 +0530 Subject: [PATCH 202/242] ARM: dts: msm: add xo clock in sde_cesta for tuna target Add xo clock in sde_cesta for tuna target. This will help to vote for xo frequency during cesta idle time. Change-Id: I7cbf64c3121044d8976272bd690a718fda18a443 Signed-off-by: Sampurna Bolloju --- display/tuna-sde.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index a1de8490..672b44cc 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 46b41adcfe9dd0a7476ad0b1659258dffa7ca9f6 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Mon, 6 Jan 2025 17:48:32 +0530 Subject: [PATCH 203/242] ARM: dts: msm: add 111 topology support for VTDR6130 panel on Tuna Add 111 topology support for VTDR6130 panel on Tuna target. Change-Id: Ie9e294652476b12aaa467cf8f754f9325576bf47 Signed-off-by: Anand Tarakh --- display/tuna-sde-display-common.dtsi | 29 ++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 168db297..4598c0e4 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" @@ -172,7 +172,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -180,7 +181,8 @@ timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -188,7 +190,8 @@ timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -196,7 +199,8 @@ timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -226,7 +230,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -249,21 +254,24 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -288,7 +296,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; From 95aa5d8b14bcc73a97dce20538c905431ca8404a Mon Sep 17 00:00:00 2001 From: Spurthy Mutturaj Date: Thu, 29 Aug 2024 10:38:33 -0700 Subject: [PATCH 204/242] ARM: dts: msm: add xo clock to sde_cesta node in sun target Add XO clock to sde_cesta node. This will help to vote XO freq for cesta idle vote for mdp-clk. Change-Id: I33b309ed9ac2d9013fee8f071c5f07938e651e5f Signed-off-by: Spurthy Mutturaj Signed-off-by: Sampurna Bolloju --- display/sun-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f5dda611..f1e10426 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -226,12 +226,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <575000000 575000000>; - clock-max-rate = <575000000 575000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk","xo"; + clock-rate = <575000000 575000000 19200000>; + clock-max-rate = <575000000 575000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 189842f911ff5463673e6c7ffd7c6839fd555bc2 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 13 Jan 2025 15:07:32 +0530 Subject: [PATCH 205/242] ARM: dts: msm: add 111 topology support for VTDR6130 panel on Kera Add 111 topology support for VTDR6130 panel on Kera target. Change-Id: I4daae3b5f1db36eec8b256a1c8e53540f39c8e1b Signed-off-by: Abhinav Saurabh --- display/kera-sde-display-common.dtsi | 35 ++++++++++++++++++---------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 8fec279c..cee0fa2e 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-sim-cmd.dtsi" @@ -135,7 +135,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -143,7 +144,8 @@ timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -151,7 +153,8 @@ timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -159,7 +162,8 @@ timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -190,7 +194,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -214,21 +219,24 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -255,7 +263,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -381,7 +390,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -403,7 +413,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; From 0b926c64065c1ace3775baf61fc3636388f977ce Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 13 Jan 2025 16:38:12 +0530 Subject: [PATCH 206/242] ARM: dts: msm: add support for sharp qhd+ sim panel on Kera Add display support for sharp qhd+ sim panel on Kera. Change-Id: I60283a25c36f9566d7273150551a7eb212cbe001 Signed-off-by: Abhinav Saurabh --- display/kera-sde-display-cdp.dtsi | 18 +++++++++++++++++- display/kera-sde-display-common.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index efb7d0d3..48dcca62 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "kera-sde-display.dtsi" @@ -135,6 +135,22 @@ qcom,platform-sec-reset-gpio = <&tlmm 127 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index cee0fa2e..1392a0c2 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -11,6 +11,8 @@ #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" @@ -420,6 +422,32 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; From 58e6536df088b2ae17df0719b49607516f89b7f5 Mon Sep 17 00:00:00 2001 From: Mani Chandana Ballary Kuntumalla Date: Sat, 28 Dec 2024 18:02:08 +0530 Subject: [PATCH 207/242] ARM: dts: msm: Enable DP for Kera CDP, QRD, and MTP platforms Enable DP support for MTP, QRD, and CDP platforms for Kera. Change-Id: I78e1c0ffd842a4ebf0d73f9076c059591036dbaf Signed-off-by: Mani Chandana Ballary Kuntumalla Signed-off-by: lnxdisplay --- display/kera-sde-display.dtsi | 2 +- display/kera-sde.dtsi | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index f2942b9c..9404dfd8 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -75,7 +75,7 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 22362ce2..0b5dc6c9 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -33,12 +33,13 @@ sde_dp: qcom,dp_display@af54000 { cell-index = <0>; compatible = "qcom,dp-display"; - status = "disabled"; + status = "ok"; - //usb-phy = <&usb_qmp_dp_phy>; + usb-phy = <&usb_qmp_dp_phy>; qcom,ext-disp = <&ext_disp>; usb-controller = <&usb0>; qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; reg = <0xaf54000 0x104>, <0xaf54200 0x0c0>, @@ -105,7 +106,7 @@ vdda-1p2-supply = <&L4B>; vdda-0p9-supply = <&L7K>; vdda_usb-0p9-supply = <&L7K>; - //vdd_mx-supply = <&VDD_MXA_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, From b0bdc77fda92821476ffdbaa9b333af7a2cbe11a Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Fri, 10 Jan 2025 14:35:41 +0530 Subject: [PATCH 208/242] ARM: dts: msm: add xo clock in sde_cesta for tuna target Add xo clock in sde_cesta for tuna target. This will help to vote for xo frequency during cesta idle time. Change-Id: I7cbf64c3121044d8976272bd690a718fda18a443 Signed-off-by: Sampurna Bolloju Signed-off-by: lnxdisplay --- display/tuna-sde.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index a1de8490..672b44cc 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 10c7d405417db4a1702afdc02de88a49bec85448 Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Mon, 6 Jan 2025 17:48:32 +0530 Subject: [PATCH 209/242] ARM: dts: msm: add 111 topology support for VTDR6130 panel on Tuna Add 111 topology support for VTDR6130 panel on Tuna target. Change-Id: Ie9e294652476b12aaa467cf8f754f9325576bf47 Signed-off-by: Anand Tarakh Signed-off-by: lnxdisplay --- display/tuna-sde-display-common.dtsi | 29 ++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 168db297..4598c0e4 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" @@ -172,7 +172,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -180,7 +181,8 @@ timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -188,7 +190,8 @@ timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -196,7 +199,8 @@ timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -226,7 +230,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -249,21 +254,24 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -288,7 +296,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; From 53d4aef4041ed7bc5b568387d1f80c8af8dd2f77 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 13 Jan 2025 16:38:12 +0530 Subject: [PATCH 210/242] ARM: dts: msm: add support for sharp qhd+ sim panel on Kera Add display support for sharp qhd+ sim panel on Kera. Change-Id: I60283a25c36f9566d7273150551a7eb212cbe001 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 18 +++++++++++++++++- display/kera-sde-display-common.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index efb7d0d3..48dcca62 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "kera-sde-display.dtsi" @@ -135,6 +135,22 @@ qcom,platform-sec-reset-gpio = <&tlmm 127 0>; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; +}; + &dsi_sim_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 8fec279c..31e0fb61 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -11,6 +11,8 @@ #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" #include "dsi-panel-sim-dualmipi-video.dtsi" #include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" @@ -409,6 +411,32 @@ }; }; +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sim_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; From 7364fffb72b177b4d5993d751efc52a4ceefbe43 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 13 Jan 2025 15:07:32 +0530 Subject: [PATCH 211/242] ARM: dts: msm: add 111 topology support for VTDR6130 panel on Kera Add 111 topology support for VTDR6130 panel on Kera target. Change-Id: I4daae3b5f1db36eec8b256a1c8e53540f39c8e1b Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-common.dtsi | 35 ++++++++++++++++++---------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 31e0fb61..1392a0c2 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-sim-cmd.dtsi" @@ -137,7 +137,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -145,7 +146,8 @@ timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -153,7 +155,8 @@ timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -161,7 +164,8 @@ timing@3 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; }; @@ -192,7 +196,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; }; @@ -216,21 +221,24 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@1 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; timing@2 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -257,7 +265,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 06 07 02 04 00 16 0b]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -383,7 +392,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; @@ -405,7 +415,8 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 07 08 02 04 00 19 0c]; - qcom,display-topology = <2 2 1>; + qcom,display-topology = <2 2 1>, + <1 1 1>; qcom,default-topology-index = <0>; }; }; From a9d0d303a539121d6014d6e924e620f66dc65abd Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Tue, 7 Jan 2025 14:52:06 +0530 Subject: [PATCH 212/242] ARM: dts: msm: add TUI touch support on vm display panel on tuna Add TUI touch support on vm display panel on Tuna target. Change-Id: I52c09fb96a54fe950c96761f96e2dfb274261021 Signed-off-by: Anand Tarakh Signed-off-by: lnxdisplay --- display/trustedvm-tuna-sde-display-cdp.dtsi | 18 +++++++++++++++++- display/trustedvm-tuna-sde-display-mtp.dtsi | 18 +++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi index 06e55839..13c0c9d9 100644 --- a/display/trustedvm-tuna-sde-display-cdp.dtsi +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "trustedvm-tuna-sde-display.dtsi" @@ -221,3 +221,19 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp.dtsi b/display/trustedvm-tuna-sde-display-mtp.dtsi index 4738255d..86d21c3f 100644 --- a/display/trustedvm-tuna-sde-display-mtp.dtsi +++ b/display/trustedvm-tuna-sde-display-mtp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "trustedvm-tuna-sde-display.dtsi" @@ -154,3 +154,19 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; }; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; From fd34b32bd6b14d4691e153cfd9a266d23188ceee Mon Sep 17 00:00:00 2001 From: Anand Tarakh Date: Thu, 9 Jan 2025 17:29:52 +0530 Subject: [PATCH 213/242] ARM: dts: msm: add TUI touch support on vm display panel on kera Add TUI touch support on vm display panel on kera target. Change-Id: I5e9e22d1476e1545ccdef69ff14248f2f019e336 Signed-off-by: Anand Tarakh Signed-off-by: lnxdisplay --- display/trustedvm-kera-sde-display-cdp.dtsi | 17 ++++++++++++++++- display/trustedvm-kera-sde-display-mtp.dtsi | 17 ++++++++++++++++- display/trustedvm-kera-sde-display-qrd.dtsi | 17 ++++++++++++++++- 3 files changed, 48 insertions(+), 3 deletions(-) diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi index 77b43890..c42cf3a7 100644 --- a/display/trustedvm-kera-sde-display-cdp.dtsi +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "trustedvm-kera-sde-display.dtsi" @@ -154,3 +154,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/trustedvm-kera-sde-display-mtp.dtsi b/display/trustedvm-kera-sde-display-mtp.dtsi index 77b43890..c42cf3a7 100644 --- a/display/trustedvm-kera-sde-display-mtp.dtsi +++ b/display/trustedvm-kera-sde-display-mtp.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "trustedvm-kera-sde-display.dtsi" @@ -154,3 +154,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/display/trustedvm-kera-sde-display-qrd.dtsi b/display/trustedvm-kera-sde-display-qrd.dtsi index 77b43890..c42cf3a7 100644 --- a/display/trustedvm-kera-sde-display-qrd.dtsi +++ b/display/trustedvm-kera-sde-display-qrd.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "trustedvm-kera-sde-display.dtsi" @@ -154,3 +154,18 @@ &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; From 7716134fc5f840a9ebf0d2b0e4457b556601ef1f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Fri, 3 Jan 2025 15:30:22 +0530 Subject: [PATCH 214/242] ARM: dts: msm: update in sharp qhd+ panel GPIO name in tuna Update in Sharp qhd+ panel GPIO name as per recent change from supplier in tuna. Change-Id: I64422b2242d78b73a39ba30a4d5377cd442d20c9 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 3d5e34aa..59f78a28 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tuna-sde-display.dtsi" -&pm8550vs_g_gpios { +&pm8550vs_d_gpios { lcd_backlight_ctrl { lcd_backlight_en_default: lcd_backlight_en_default { pins = "gpio4"; @@ -19,7 +19,7 @@ }; }; -&pm8550vs_f_gpios { +&pm8550ve_f_gpios { display_panel_avdd_default: display_panel_avdd_default { pins = "gpio8"; function = "normal"; @@ -38,7 +38,7 @@ regulator-min-microvolt = <5500000>; regulator-max-microvolt = <5500000>; regulator-enable-ramp-delay = <233>; - gpio = <&pm8550vs_f_gpios 8 0>; + gpio = <&pm8550ve_f_gpios 8 0>; enable-active-high; regulator-boot-on; proxy-supply = <&display_panel_avdd>; @@ -265,7 +265,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 14 0>; - qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; }; &dsi_sharp_qhd_plus_dsc_video { @@ -274,7 +274,7 @@ qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 14 0>; - qcom,platform-bklight-en-gpio = <&pm8550vs_g_gpios 4 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; }; &dsi_sim_cmd { From a8dacd89026e7852925eaae6d222addd29ab06ea Mon Sep 17 00:00:00 2001 From: Yadong Wang Date: Fri, 27 Dec 2024 11:04:25 +0800 Subject: [PATCH 215/242] ARM: dts: msm: add physical width/height config for NT37801 panel This change adds physical width/height configurations for NT37801 panel Change-Id: Ifa4b1c719e7046aa1d4a00156fb9e97f2027f64c Signed-off-by: Yadong Wang Signed-off-by: lnxdisplay --- display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi | 2 ++ display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi index 29afd64e..f7807289 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -29,6 +29,8 @@ qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <161>; qcom,mdss-dsi-te-pin-select = <1>; qcom,mdss-dsi-wr-mem-start = <0x2c>; diff --git a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi index 26b49ed2..fd8f2e99 100644 --- a/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -24,6 +24,8 @@ qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <161>; qcom,mdss-dsi-tx-eot-append; qcom,adjust-timer-wakeup-ms = <1>; qcom,panel-cphy-mode; From 88e82855ef7606e0034e84f189963e9ed5981a49 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 20 Jan 2025 15:24:10 +0800 Subject: [PATCH 216/242] ARM: dts: msm: update qsync min fps support for nt37801 vid mode panel This change updates qsync min refresh rate support from 80Hz to 90Hz for nt37801 video mode panel. Change-Id: Id3db122e121b59163e16e7413cc7be1256c3f397 Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi | 4 ++-- display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi index 7840c1c2..f1fd60ce 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &mdss_mdp { @@ -37,7 +37,7 @@ qcom,mdss-dsi-wr-mem-start = <0x2c>; qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,qsync-enable; - qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-qsync-min-refresh-rate = <90>; qcom,mdss-dsi-display-timings { timing@0 { cell-index = <0>; diff --git a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi index 93fd3234..9b8dfcd4 100644 --- a/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi +++ b/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ &mdss_mdp { @@ -34,7 +34,7 @@ qcom,mdss-dsi-wr-mem-continue = <0x3c>; qcom,spr-pack-type = "pentile"; qcom,qsync-enable; - qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-qsync-min-refresh-rate = <90>; qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 15700 12250 35800 6750 2550>; From 820ccdbe30d53ab346f673ac366b7fc494606b0f Mon Sep 17 00:00:00 2001 From: Huayang Zhong Date: Fri, 3 Jan 2025 12:56:36 +0800 Subject: [PATCH 217/242] ARM: dts: msm: enable dfps for sharp quadpipe panel This change enables dfps for sharp video mode panel on sun target. Change-Id: I710fc6dd6d4f910f44db32e1e9ee3dbafa688dea Signed-off-by: Huayang Zhong Signed-off-by: lnxdisplay --- display/sun-sde-display-common.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index 98eaab75..a6b1b5b2 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" @@ -808,6 +808,10 @@ &dsi_sharp_qhd_plus_dsc_video { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 From df60c4102a40693b3796df04187996f2b929e138 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 9 Jan 2025 15:17:40 +0530 Subject: [PATCH 218/242] ARM: dts: msm: update dvdd initial voltage for tuna MTP & CDP Increase DVDD initial voltage from 1.06V to 1.09V. Also increase the min voltage voting to 1.09V for CDP and MTP platforms of Tuna. This is to avoid any voltage drop issue on the DVDD rail similar to Tuna QRD platform. Change-Id: I77eabf294777130059bac6f748cc5c0f4a7d0002 Signed-off-by: Abhinav Saurabh --- display/tuna-sde-display-cdp.dtsi | 11 +++++++++++ display/tuna-sde-display-mtp.dtsi | 13 ++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 59f78a28..22b70ad5 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,17 @@ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &pm8550vs_d_gpios { lcd_backlight_ctrl { lcd_backlight_en_default: lcd_backlight_en_default { diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi index e330558d..237c7780 100644 --- a/display/tuna-sde-display-mtp.dtsi +++ b/display/tuna-sde-display-mtp.dtsi @@ -1,10 +1,21 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; From 3cb51a69e7c1211e380c8cfcbf0558905351e3d3 Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 10 Dec 2024 14:52:46 +0800 Subject: [PATCH 219/242] ARM: dts: msm: update dvdd initial voltage for tuna QRD Increase dvdd initial voltage from 1.06v to 1.09v to avoid voltage drop issue caused by IR on tuna QRD target. Change-Id: I23bc8d44ec13260b9281e3c08968daa5e97fafb6 Signed-off-by: Lei Chen --- display/tuna-sde-display-qrd.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 1ffc9332..312952ed 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -5,6 +5,17 @@ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; From 97a28e65f92b168cea39b9b18efb3ac4f715cae4 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Thu, 16 Jan 2025 11:43:28 +0530 Subject: [PATCH 220/242] ARM: dts: msm: enable display cesta on kera target Add display cesta related DT node on kera target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d Signed-off-by: Sailesh Reddy Male --- display/kera-sde-display.dtsi | 3 +- display/kera-sde.dtsi | 54 ++++++++++++++++++++++++++++----- display/trustedvm-kera-sde.dtsi | 11 ++++++- 3 files changed, 58 insertions(+), 10 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index ee0d4543..5b448fb8 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -87,7 +87,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index bb73d70f..8c06d42e 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - qti,smmu-proxy-cb-id = ; qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 3740746b..05d3d958 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version = <0xC0040000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 01b4df928e22a26f0ab689daa650625ca7a8b525 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Mon, 20 Jan 2025 15:07:40 +0530 Subject: [PATCH 221/242] ARM: dts: msm: add xo clock in sde_cesta for kera target Add xo clock in sde_cesta for kera target. This will help to vote for xo frequency during cesta idle time. Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968 Signed-off-by: Sailesh Reddy Male --- display/kera-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 8c06d42e..1148e017 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 833aabb4db040bd50138d676db5789a66360b2ff Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Fri, 31 Jan 2025 18:28:30 +0530 Subject: [PATCH 222/242] ARM: dts: msm: remove hard coded panel clk rate for kera RCM Remove hard coded panel clk rate Kera RCM platform. Change-Id: I1c3c77eed76665e87e9ec0ed0dfc2ba80e97e08e Signed-off-by: Ayushi Makhija --- display/kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ display/trustedvm-kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 48dcca62..5c971225 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -16,6 +16,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -42,6 +60,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -68,6 +100,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi index 77b43890..4b000697 100644 --- a/display/trustedvm-kera-sde-display-cdp.dtsi +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -14,6 +14,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -36,6 +54,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -58,6 +90,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { From 4dbf74429549c78d489a5b2c106ca99af985a02a Mon Sep 17 00:00:00 2001 From: Ayushi Makhija Date: Fri, 31 Jan 2025 18:28:30 +0530 Subject: [PATCH 223/242] ARM: dts: msm: remove hard coded panel clk rate for kera RCM Remove hard coded panel clk rate Kera RCM platform. Change-Id: I1c3c77eed76665e87e9ec0ed0dfc2ba80e97e08e Signed-off-by: Ayushi Makhija Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ display/trustedvm-kera-sde-display-cdp.dtsi | 42 +++++++++++++++++++++ 2 files changed, 84 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 48dcca62..5c971225 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -16,6 +16,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -42,6 +60,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -68,6 +100,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { diff --git a/display/trustedvm-kera-sde-display-cdp.dtsi b/display/trustedvm-kera-sde-display-cdp.dtsi index c42cf3a7..fc746e20 100644 --- a/display/trustedvm-kera-sde-display-cdp.dtsi +++ b/display/trustedvm-kera-sde-display-cdp.dtsi @@ -14,6 +14,24 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_video { @@ -36,6 +54,20 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_120hz_video { @@ -58,6 +90,16 @@ qcom,mdss-dsi-bl-inverted-dbv; qcom,platform-reset-gpio = <&tlmm 12 0>; qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; }; &dsi_vtdr6130_amoled_90hz_video { From e8ba29204b695894d17c7711f357f1696415a899 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Mon, 20 Jan 2025 10:50:02 +0530 Subject: [PATCH 224/242] ARM: dts: msm: support 4k sharp panel on Tuna CDP Support 4k sharp panel on Tuna CDP. Change-Id: Ifdc1fa4edfe7ac752e1e4d8ab56d4735427d633b Signed-off-by: Rajeev Nandan Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 18 ++++++++++++ display/tuna-sde-display-common.dtsi | 44 ++++++++++++++++++++++++++++ display/tuna-sde-display.dtsi | 6 +++- 3 files changed, 67 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 59f78a28..b7f06fd9 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -259,6 +259,24 @@ qcom,platform-sec-reset-gpio = <&tlmm 126 0>; }; +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index 4598c0e4..f47125d1 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -18,6 +18,8 @@ #include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" #include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" #include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" #include "dsi-panel-sim-cmd-au.dtsi" @@ -748,6 +750,48 @@ }; }; +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; diff --git a/display/tuna-sde-display.dtsi b/display/tuna-sde-display.dtsi index b905f813..402b3d07 100644 --- a/display/tuna-sde-display.dtsi +++ b/display/tuna-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -214,6 +214,10 @@ }; }; +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; +}; + &dsi_sim_cmd { qcom,ulps-enabled; qcom,mdss-dsi-display-timings { From 3253c6e1eae380da6751a76381b1da61ae7c718e Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Fri, 3 Jan 2025 12:24:22 +0530 Subject: [PATCH 225/242] ARM: dts: msm: reserve memory region for splash and ramdump Reserves memory region to enable continuous splash and ramdump on tuna target. Change-Id: I0c2da9b0093923b83344e0bf3927022eceb30326 Signed-off-by: Sailesh Reddy Male Signed-off-by: lnxdisplay --- display/kera-sde-display.dtsi | 14 +++++++++++++- display/kera-sde.dtsi | 3 ++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 9404dfd8..ee0d4543 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -14,6 +14,18 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; }; &sde_dsi { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 0b5dc6c9..bb73d70f 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -183,6 +183,7 @@ smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, <&smmu_sde_sec 0x0 0x00020000>; }; From f78eece0c398d6a207f87d838074e200a645ce7b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 20 Jan 2025 14:07:10 +0530 Subject: [PATCH 226/242] ARM: dts: msm: enable touch support for vtdr panel on tuna Enable touch support for vtdr panel on tuna CDP. Change-Id: I9bec9f15829c789a9f5230cd59811465f87e895e Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index b7f06fd9..88bd993c 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -363,4 +363,15 @@ &dsi_nt37801_amoled_cmd_ddicspr &dsi_nt37801_amoled_video_ddicspr>; }; + + goodix-berlin@5d { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video>; + }; }; From 41793be5f5e7a8501520e99fc19e7eed0f8dce13 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 28 Jan 2025 16:06:54 +0530 Subject: [PATCH 227/242] ARM: dts: msm: update in sharp qhd+ panel GPIO name in Kera Update in Sharp qhd+ panel GPIO name as per recent change from supplier and enablement of its physical panel in Kera. Change-Id: I15115714f5e719eed63e741bc7aef8b2fb608c0d Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 50 ++++++++++++++++++++++++++-- display/kera-sde-display-common.dtsi | 24 +++++++++++++ 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 5c971225..0dca9ffd 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -5,6 +5,49 @@ #include "kera-sde-display.dtsi" +&pmxr2230_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio2"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550vs_g_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio5"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550vs_g_gpios 5 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + &dsi_vtdr6130_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; @@ -178,19 +221,21 @@ }; &dsi_sharp_qhd_plus_dsc_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; }; &dsi_sharp_qhd_plus_dsc_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; }; &dsi_sim_cmd { @@ -239,6 +284,7 @@ }; &sde_dsi { + avdd-supply = <&display_panel_avdd>; qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; diff --git a/display/kera-sde-display-common.dtsi b/display/kera-sde-display-common.dtsi index 1392a0c2..bd95e2e8 100644 --- a/display/kera-sde-display-common.dtsi +++ b/display/kera-sde-display-common.dtsi @@ -79,6 +79,30 @@ }; }; + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + sde_dsi: qcom,dsi-display-primary { compatible = "qcom,dsi-display"; label = "primary"; From 8aebb5a4919e6613ae0195c0e4383c873cfb734e Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Mon, 20 Jan 2025 12:14:52 +0530 Subject: [PATCH 228/242] ARM: dts: msm: add 60hz and 90hz support for VTDR6130 panel on tuna Add 60hz and 90hz support for VTDR6130 panel on tuna target. Change-Id: Iad6d7514f241be42bf2cd8addaefa2d3fb1e89a8 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 56 ++++++++++++++ display/tuna-sde-display-common.dtsi | 108 +++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index 88bd993c..e306ac89 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -76,7 +76,9 @@ &dsi_vtdr6130_amoled_120hz_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; @@ -228,7 +230,61 @@ &dsi_vtdr6130_amoled_120hz_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; qcom,mdss-dsi-bl-min-level = <10>; qcom,mdss-dsi-bl-max-level = <4095>; qcom,mdss-brightness-max-level = <8191>; diff --git a/display/tuna-sde-display-common.dtsi b/display/tuna-sde-display-common.dtsi index f47125d1..093f5ca4 100644 --- a/display/tuna-sde-display-common.dtsi +++ b/display/tuna-sde-display-common.dtsi @@ -33,6 +33,10 @@ #include "dsi-panel-sim-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" #include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" @@ -305,6 +309,110 @@ }; }; +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; qcom,esd-check-enabled; From d56825f5c411151d1516280c5e30d7797665bde5 Mon Sep 17 00:00:00 2001 From: Jayaprakash Madisetty Date: Fri, 10 Jan 2025 16:35:04 +0530 Subject: [PATCH 229/242] ARM: dts: msm: add disp_cc io to sde cesta To enable and disable mdp clock gating functionality with cesta immediate vote approach, add disp_cc_io memory to sde cesta. Change-Id: I2bd6d80269a69d870f2c8b4ff0b1bf8b1270aa6f Signed-off-by: Jayaprakash Madisetty Signed-off-by: lnxdisplay --- display/sun-sde.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/display/sun-sde.dtsi b/display/sun-sde.dtsi index f1e10426..ebb9dbbd 100644 --- a/display/sun-sde.dtsi +++ b/display/sun-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -222,8 +222,9 @@ <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", "disp_cc"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, From 54b12f3ac164b3f82c9666978629249341ee9249 Mon Sep 17 00:00:00 2001 From: Sampurna Bolloju Date: Tue, 11 Feb 2025 14:51:22 +0530 Subject: [PATCH 230/242] ARM: dts: msm: add disp_cc io and ctl hyp DT property To enable and disable mdp clock gating functionality with cesta immediate vote approach, add disp_cc_io memory to sde cesta. Add ctl hyp DT property for reserve reservation on a datapath used in VM. Change-Id: I4c1b900dfb5e1a7d725aea80b4519bc1f9472e03 Signed-off-by: Sampurna Bolloju --- display/tuna-sde-common.dtsi | 5 ++++- display/tuna-sde.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/display/tuna-sde-common.dtsi b/display/tuna-sde-common.dtsi index e3098929..e3030150 100644 --- a/display/tuna-sde-common.dtsi +++ b/display/tuna-sde-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -31,6 +31,9 @@ qcom,sde-off = <0x1000>; qcom,sde-len = <0x488>; + qcom,sde-ctl-hyp-off = <0x15000>; + qcom,sde-ctl-hyp-size = <0xc00>; + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; qcom,sde-ctl-size = <0x1000>; qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; diff --git a/display/tuna-sde.dtsi b/display/tuna-sde.dtsi index 672b44cc..8dfa80e1 100644 --- a/display/tuna-sde.dtsi +++ b/display/tuna-sde.dtsi @@ -218,8 +218,10 @@ <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", + "disp_cc"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, From 03f3cfccb929895772920f28ab7eeef11757a226 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Thu, 16 Jan 2025 11:43:28 +0530 Subject: [PATCH 231/242] ARM: dts: msm: enable display cesta on kera target Add display cesta related DT node on kera target. Move the GDSC & MDP core clock from MDP to cesta node, as it will be controlled through cesta. Add the cesta related register offsets in trusted-vm DT. Change-Id: I1f777f3402d8a4d7d57ca889206a4095447abb7d Signed-off-by: Sailesh Reddy Male --- display/kera-sde-display.dtsi | 3 +- display/kera-sde.dtsi | 54 ++++++++++++++++++++++++++++----- display/trustedvm-kera-sde.dtsi | 11 ++++++- 3 files changed, 58 insertions(+), 10 deletions(-) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index ee0d4543..5b448fb8 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -87,7 +87,8 @@ }; &mdss_mdp { - connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp>; + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp + &sde_cesta>; }; &dsi_vtdr6130_amoled_cmd { diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index bb73d70f..8c06d42e 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -207,27 +207,65 @@ clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; clock-names = "mdp_core_clk"; }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + + clock-names = "branch_clk", "core_clk"; + clock-rate = <660000000 660000000>; + clock-max-rate = <660000000 660000000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; }; &mdss_mdp { clocks = <&gcc GCC_DISP_HF_AXI_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; clock-names = "gcc_bus", - "iface_clk", "branch_clk", "core_clk", "vsync_clk", - "lut_clk"; - clock-rate = <0 0 660000000 660000000 19200000 660000000>; - clock-max-rate = <0 0 660000000 660000000 19200000 660000000>; + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; qcom,hw-fence-sw-version = <0x1>; - power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; - qti,smmu-proxy-cb-id = ; qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; diff --git a/display/trustedvm-kera-sde.dtsi b/display/trustedvm-kera-sde.dtsi index 3740746b..05d3d958 100644 --- a/display/trustedvm-kera-sde.dtsi +++ b/display/trustedvm-kera-sde.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -36,6 +36,15 @@ "sid_phys"; qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; qcom,sde-hw-version = <0xC0040000>; clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, From 709107dd1c60bdfce13389caf134fb4f4af43148 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Mon, 20 Jan 2025 15:07:40 +0530 Subject: [PATCH 232/242] ARM: dts: msm: add xo clock in sde_cesta for kera target Add xo clock in sde_cesta for kera target. This will help to vote for xo frequency during cesta idle time. Change-Id: Ic4370c8a49ffbec2743c022e438280d371a5a968 Signed-off-by: Sailesh Reddy Male --- display/kera-sde.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 8c06d42e..1148e017 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -222,12 +222,13 @@ reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>; + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; - clock-names = "branch_clk", "core_clk"; - clock-rate = <660000000 660000000>; - clock-max-rate = <660000000 660000000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC>; + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From 4648e8647fbbd3d2adb983711a54a1c67b7e2bd0 Mon Sep 17 00:00:00 2001 From: Sailesh Reddy Male Date: Tue, 11 Feb 2025 15:22:29 +0530 Subject: [PATCH 233/242] ARM: dts: msm: add disp_cc io to cesta and ctl hyp to mdss_mdp device To enable and disable mdp clock gating functionality with cesta immediate vote approach, add disp_cc_io memory to sde cesta. Add changes to enable ctl hyp property for reserve reservation on datapath used in a VM. Change-Id: Id10875ecb90acb8a922ef4e4788da13a764ea102 Signed-off-by: Sailesh Reddy Male --- display/kera-sde-common.dtsi | 5 ++++- display/kera-sde.dtsi | 6 ++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/display/kera-sde-common.dtsi b/display/kera-sde-common.dtsi index a2822e3e..94e9cdb8 100644 --- a/display/kera-sde-common.dtsi +++ b/display/kera-sde-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -31,6 +31,9 @@ qcom,sde-off = <0x1000>; qcom,sde-len = <0x488>; + qcom,sde-ctl-hyp-off = <0x15000>; + qcom,sde-ctl-hyp-size = <0xc00>; + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; qcom,sde-ctl-size = <0x1000>; qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index 1148e017..f2714059 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -218,8 +218,10 @@ <0xaf33000 0x30>, <0xaf34000 0x30>, <0xaf35000 0x30>, - <0xaf36000 0x30>; - reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5"; + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", + "disp_cc"; clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, From 003732b83e15db7721c50df5df93f216fef2aedd Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 13 Feb 2025 11:13:37 +0530 Subject: [PATCH 234/242] ARM: dts: msm: add ulps & roi support for 120hz VTDR6130 panel on Kera Add ulps and roi support for 120hz, 90hz & 60hz VTDR6130 panel on Kera target. Change-Id: I21bf599aadc6d4f10d25c3f1d232c1ba37a0d8b1 Signed-off-by: Abhinav Saurabh --- display/kera-sde-display.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 5b448fb8..5bf58b4f 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -116,6 +116,34 @@ }; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,ulps-enabled; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,ulps-enabled; }; From 814a9fa2bedcac2facb510cc133be8c5812a44db Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Fri, 14 Feb 2025 18:47:18 +0800 Subject: [PATCH 235/242] ARM: dts: msm: set aux switch as fsa4480 for kera qrd platform This change sets aux switch as fsa4480 for kera qrd platform. Change-Id: Ie6b3311879dcc84284c32a4801a98b50fbe6c07b Signed-off-by: Yahui Wang --- display/kera-sde-display-qrd.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/display/kera-sde-display-qrd.dtsi b/display/kera-sde-display-qrd.dtsi index efb7d0d3..4d959c52 100644 --- a/display/kera-sde-display-qrd.dtsi +++ b/display/kera-sde-display-qrd.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "kera-sde-display.dtsi" @@ -180,6 +180,10 @@ qcom,mdss-dsi-bl-max-level = <1023>; }; +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + &sde_dsi { qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; }; From 2b84779e5519d6769e922dbba2cbc13c3946e137 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 25 Feb 2025 17:23:17 +0530 Subject: [PATCH 236/242] ARM: dts: msm: Update PHY timings for CMD VTDR panels on Kera CDP/RCM This update adjusts the PHY timings for the VTDR command mode panel on Kera RCM/CDP platforms based on the required FPS, following the removal of the qcom,mdss-dsi-panel-clockrate hardcoding. Previously, the hardcoding resulted in uniform panel PHY timings across all FPS. Some Kera RCMs have exhibited screen freeze issues when switching from 120 FPS to 60 FPS in command mode after the removal of the hardcoded clock rate. Interestingly, this issue has not been observed on Kera CDPs and other platforms, suggesting potential underlying hardware differences between CDPs and RCMs that necessitate proper tuning of panel PHY timings. Update the panel PHY timings to fix this. Fixes: I1c3c77eed76 ("ARM: dts: msm: remove hard coded panel clk rate for kera RCM"). Change-Id: Iffd1d5da485d6961baa49ff96a65882c491a8ff6 Signed-off-by: Abhinav Saurabh --- display/kera-sde-display-cdp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 0dca9ffd..faa2551e 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -67,14 +67,20 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@3 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -111,10 +117,14 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -151,6 +161,8 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; From b32b6000f9a03e8de1d92b242263670c02b2614d Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 9 Jan 2025 15:17:40 +0530 Subject: [PATCH 237/242] ARM: dts: msm: update dvdd initial voltage for tuna MTP & CDP Increase DVDD initial voltage from 1.06V to 1.09V. Also increase the min voltage voting to 1.09V for CDP and MTP platforms of Tuna. This is to avoid any voltage drop issue on the DVDD rail similar to Tuna QRD platform. Change-Id: I77eabf294777130059bac6f748cc5c0f4a7d0002 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/tuna-sde-display-cdp.dtsi | 11 +++++++++++ display/tuna-sde-display-mtp.dtsi | 13 ++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/display/tuna-sde-display-cdp.dtsi b/display/tuna-sde-display-cdp.dtsi index e306ac89..35f2ef16 100644 --- a/display/tuna-sde-display-cdp.dtsi +++ b/display/tuna-sde-display-cdp.dtsi @@ -5,6 +5,17 @@ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &pm8550vs_d_gpios { lcd_backlight_ctrl { lcd_backlight_en_default: lcd_backlight_en_default { diff --git a/display/tuna-sde-display-mtp.dtsi b/display/tuna-sde-display-mtp.dtsi index e330558d..237c7780 100644 --- a/display/tuna-sde-display-mtp.dtsi +++ b/display/tuna-sde-display-mtp.dtsi @@ -1,10 +1,21 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; From f61c034cdf482641c911a64a31da68cd7f0c1e77 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Thu, 20 Mar 2025 07:31:10 +0530 Subject: [PATCH 238/242] ARM: dts: msm: remove mmrm support from kera This change removes support for display clock scaling through mmrm is not supported in kera target. Change-Id: Idb83968784dcd1e6cabc5bc107a5bd8013612686 Signed-off-by: Mahadevan Signed-off-by: lnxdisplay --- display/kera-sde.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/display/kera-sde.dtsi b/display/kera-sde.dtsi index f2714059..e08b2156 100644 --- a/display/kera-sde.dtsi +++ b/display/kera-sde.dtsi @@ -230,7 +230,6 @@ clock-names = "branch_clk", "core_clk", "xo"; clock-rate = <660000000 660000000 19200000>; clock-max-rate = <660000000 660000000 19200000>; - clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, From ede1e06af139fba94ad5e040c7604e361ec0c993 Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 25 Feb 2025 17:23:17 +0530 Subject: [PATCH 239/242] ARM: dts: msm: Update PHY timings for CMD VTDR panels on Kera CDP/RCM This update adjusts the PHY timings for the VTDR command mode panel on Kera RCM/CDP platforms based on the required FPS, following the removal of the qcom,mdss-dsi-panel-clockrate hardcoding. Previously, the hardcoding resulted in uniform panel PHY timings across all FPS. Some Kera RCMs have exhibited screen freeze issues when switching from 120 FPS to 60 FPS in command mode after the removal of the hardcoded clock rate. Interestingly, this issue has not been observed on Kera CDPs and other platforms, suggesting potential underlying hardware differences between CDPs and RCMs that necessitate proper tuning of panel PHY timings. Update the panel PHY timings to fix this. Fixes: I1c3c77eed76 ("ARM: dts: msm: remove hard coded panel clk rate for kera RCM"). Change-Id: Iffd1d5da485d6961baa49ff96a65882c491a8ff6 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display-cdp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/display/kera-sde-display-cdp.dtsi b/display/kera-sde-display-cdp.dtsi index 0dca9ffd..faa2551e 100644 --- a/display/kera-sde-display-cdp.dtsi +++ b/display/kera-sde-display-cdp.dtsi @@ -67,14 +67,20 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@3 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -111,10 +117,14 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; }; timing@2 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; @@ -151,6 +161,8 @@ timing@1 { /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; }; }; }; From bb0164b4b0f6eaad55d280889e7c85c0e7b3314b Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Thu, 13 Feb 2025 11:13:37 +0530 Subject: [PATCH 240/242] ARM: dts: msm: add ulps & roi support for 120hz VTDR6130 panel on Kera Add ulps and roi support for 120hz, 90hz & 60hz VTDR6130 panel on Kera target. Change-Id: I21bf599aadc6d4f10d25c3f1d232c1ba37a0d8b1 Signed-off-by: Abhinav Saurabh Signed-off-by: lnxdisplay --- display/kera-sde-display.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/display/kera-sde-display.dtsi b/display/kera-sde-display.dtsi index 5b448fb8..5bf58b4f 100644 --- a/display/kera-sde-display.dtsi +++ b/display/kera-sde-display.dtsi @@ -116,6 +116,34 @@ }; }; +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,ulps-enabled; +}; + &dsi_vtdr6130_amoled_qsync_144hz_cmd { qcom,ulps-enabled; }; From 914167ae87124023769400f9d026984b015cd3df Mon Sep 17 00:00:00 2001 From: Lei Chen Date: Tue, 10 Dec 2024 14:52:46 +0800 Subject: [PATCH 241/242] ARM: dts: msm: update dvdd initial voltage for tuna QRD Increase dvdd initial voltage from 1.06v to 1.09v to avoid voltage drop issue caused by IR on tuna QRD target. Change-Id: I23bc8d44ec13260b9281e3c08968daa5e97fafb6 Signed-off-by: Lei Chen Signed-off-by: lnxdisplay --- display/tuna-sde-display-qrd.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/display/tuna-sde-display-qrd.dtsi b/display/tuna-sde-display-qrd.dtsi index 1ffc9332..312952ed 100644 --- a/display/tuna-sde-display-qrd.dtsi +++ b/display/tuna-sde-display-qrd.dtsi @@ -5,6 +5,17 @@ #include "tuna-sde-display.dtsi" +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + &dsi_nt37801_amoled_cmd { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; From 70a86b3f2de3d7dd35a31efe4002891f59d9a703 Mon Sep 17 00:00:00 2001 From: Jinfeng Gu Date: Mon, 10 Mar 2025 10:59:21 +0800 Subject: [PATCH 242/242] ARM: dts: msm: enable esd check for sharp qhd panel This change enables esd check for sharp qhd panel. Change-Id: I8cd0d670bbb71492b665b1a52a48a08848f90c0f Signed-off-by: Jinfeng Gu Signed-off-by: lnxdisplay --- display/sun-sde-display-common.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/display/sun-sde-display-common.dtsi b/display/sun-sde-display-common.dtsi index a6b1b5b2..fffb51e2 100644 --- a/display/sun-sde-display-common.dtsi +++ b/display/sun-sde-display-common.dtsi @@ -796,6 +796,14 @@ &dsi_sharp_qhd_plus_dsc_cmd { qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x07>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 @@ -812,6 +820,13 @@ qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-display-timings { timing@0 { /* 120 FPS */ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07