diff --git a/qcom/display/Kbuild b/qcom/display/Kbuild new file mode 100644 index 00000000..31654078 --- /dev/null +++ b/qcom/display/Kbuild @@ -0,0 +1,71 @@ +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_SUN) += display/sun-sde.dtbo \ + display/sun-sde-display-cdp-overlay.dtbo \ + display/sun-sde-display-mtp-overlay.dtbo \ + display/sun-sde-display-rumi-overlay.dtbo \ + display/sun-sde-display-rcm-overlay.dtbo \ + display/sun-sde-display-qrd-sku1-overlay.dtbo \ + display/sun-sde-display-qrd-sku1-v8-overlay.dtbo \ + display/sun-sde-display-qrd-sku2-v8-overlay.dtbo \ + display/sun-sde-display-cdp-kiwi-overlay.dtbo \ + display/sun-sde-display-mtp-kiwi-overlay.dtbo \ + display/sun-sde-display-cdp-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-mtp-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-cdp-nfc-overlay.dtbo \ + display/sun-sde-display-mtp-nfc-overlay.dtbo \ + display/sun-sde-display-cdp-v8-overlay.dtbo \ + display/sun-sde-display-mtp-v8-overlay.dtbo \ + display/sun-sde-display-atp-overlay.dtbo \ + display/sun-sde-display-mtp-3-5mm-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-overlay.dtbo \ + display/sun-sde-display-rcm-kiwi-v8-overlay.dtbo \ + display/sun-sde-display-rcm-v8-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-overlay.dtbo \ + display/sun-sde-display-mtp-qmp1000-v8-overlay.dtbo \ + display/sun-sde-display-hdk-overlay.dtbo \ + display/sun-sde-display-cdp-no-display-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_SUN) += display/trustedvm-sun-sde-display-cdp-overlay.dtbo \ + display/trustedvm-sun-sde-display-mtp-overlay.dtbo \ + display/trustedvm-sun-sde-display-qrd-overlay.dtbo +endif + +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_TUNA) += display/tuna-sde.dtbo \ + display/tuna-sde-display-atp-overlay.dtbo \ + display/tuna-sde-display-cdp-overlay.dtbo \ + display/tuna-sde-display-mtp-overlay.dtbo \ + display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ + display/tuna-sde-display-qrd-overlay.dtbo \ + display/tuna-sde-display-rumi-overlay.dtbo \ + display/tuna-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-tuna-sde-display-atp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-cdp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-overlay.dtbo \ + display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dtbo \ + display/trustedvm-tuna-sde-display-qrd-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rumi-overlay.dtbo \ + display/trustedvm-tuna-sde-display-rcm-overlay.dtbo +endif + +ifneq ($(CONFIG_ARCH_QTI_VM), y) +dtbo-$(CONFIG_ARCH_KERA) += display/kera-sde.dtbo \ + display/kera-sde-display-atp-overlay.dtbo \ + display/kera-sde-display-cdp-overlay.dtbo \ + display/kera-sde-display-mtp-overlay.dtbo \ + display/kera-sde-display-qrd-overlay.dtbo \ + display/kera-sde-display-rumi-overlay.dtbo \ + display/kera-sde-display-rcm-overlay.dtbo +else +dtbo-$(CONFIG_ARCH_TUNA) += display/trustedvm-kera-sde-display-atp-overlay.dtbo \ + display/trustedvm-kera-sde-display-cdp-overlay.dtbo \ + display/trustedvm-kera-sde-display-mtp-overlay.dtbo \ + display/trustedvm-kera-sde-display-qrd-overlay.dtbo \ + display/trustedvm-kera-sde-display-rumi-overlay.dtbo \ + display/trustedvm-kera-sde-display-rcm-overlay.dtbo +endif + +always-y := $(dtb-y) $(dtbo-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb *.dtbo diff --git a/qcom/display/Makefile b/qcom/display/Makefile new file mode 100644 index 00000000..b1e0dfe9 --- /dev/null +++ b/qcom/display/Makefile @@ -0,0 +1,9 @@ +KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=. + +all: dtbs + +clean: + $(MAKE) -C $(KERNEL_SRC) M=$(M) clean + +%: + $(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS) diff --git a/qcom/display/bindings/dsi.yaml b/qcom/display/bindings/dsi.yaml new file mode 100644 index 00000000..4fc3c0a6 --- /dev/null +++ b/qcom/display/bindings/dsi.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI Controller output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,mdss-dsi-ctrl + + reg: + description: Physical base address and length of the registers of controller + + reg-names: + description: The names of register regions. + required: + - "dsi_ctrl" + + interrupts: + description: The interrupt signal from the DSI block. + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + description: > + Clocks necessary for DSI operation. For DSIv2, we need an additional clock "src" and for + DSI6G v2.0 onwards, we also need the clock "byte_intf". + required: + - "mdp_core" + - "iface" + - "bus" + - "core_mmss" + - "byte" + - "pixel" + - "core" + + assigned-clocks: + description: Parents of "byte" and "pixel" for the given platform. + + assigned-clock-parents: + description: > + The Byte clock and Pixel clock PLL outputs provided + by a DSI PHY block. See [1] for details on clock bindings. + + vdd-supply: + description: phandle to vdd regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vddio-supply: + description: phandle to vdd-io regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + phys: + description: phandle to DSI PHY device node + $ref: /schemas/types.yaml#/definitions/phandle + + phy-names: + description: the name of the corresponding PHY device + $ref: /schemas/types.yaml#/definitions/string-array + + syscon-sfpb: + description: A phandle to mmss_sfpb syscon node (only for DSIv2) + $ref: /schemas/types.yaml#/definitions/phandle + + panel@0: + description: > + Node of panel connected to this DSI controller. + See files in [4] for each supported panel. + + qcom,dual-dsi-mode: + description: > + Boolean value indicating if the DSI controller is + driving a panel which needs 2 DSI links. + + qcom,master-dsi: + description: > + Boolean value indicating if the DSI controller is driving + the master link of the 2-DSI panel. + + qcom,sync-dual-dsi: + description: > + Boolean value indicating if the DSI controller is + driving a 2-DSI panel whose 2 links need receive command simultaneously. + + pinctrl-names: + description: the pin control state names; should contain "default" + + pinctrl-0: + description: the default pinctrl state (active) + + pinctrl-n: + description: the "sleep" pinctrl state + + qcom,dsi-ctrl-shared: + description: > + Boolean value indicating if the DSI controller is + shared between dual displays. + +required: + - compatible + - reg + - reg-names + - interrupts + - power-domains + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents + - vdd-supply + - vddio-supply + - vdda-supply + - phys + - phy-names + - syscon-sfpb + - ports + +examples: + - | + dsi0: dsi@fd922800 { + compatible = "qcom,mdss-dsi-ctrl"; + qcom,dsi-host-index = <0>; + interrupt-parent = <&mdp>; + interrupts = <4 0>; + reg-names = "dsi_ctrl"; + reg = <0xfd922800 0x200>; + power-domains = <&mmcc MDSS_GDSC>; + clock-names = + "bus", + "byte", + "core", + "core_mmss", + "iface", + "mdp_core", + "pixel"; + clocks = + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_PCLK0_CLK>; + + assigned-clocks = + <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = + <&dsi_phy0 0>, + <&dsi_phy0 1>; + + vdda-supply = <&pma8084_l2>; + vdd-supply = <&pma8084_l22>; + vddio-supply = <&pma8084_l12>; + + phys = <&dsi_phy0>; + phy-names ="dsi-phy"; + + qcom,dual-dsi-mode; + qcom,master-dsi; + qcom,sync-dual-dsi; + qcom,dsi-ctrl-shared; + + qcom,mdss-mdp-transfer-time-us = <12000>; + frame-threshold-time-us = <800>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dsi_active>; + pinctrl-1 = <&dsi_suspend>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&panel_in>; + data-lanes = <0 1 2 3>; + }; + }; + }; + + panel: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + link2 = <&secondary>; + + power-supply = <...>; + backlight = <...>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/qcom/display/bindings/dsi_phy.yaml b/qcom/display/bindings/dsi_phy.yaml new file mode 100644 index 00000000..7d99e278 --- /dev/null +++ b/qcom/display/bindings/dsi_phy.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dsi_phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc. Snapdragon DSI PHY output + +description: > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt + [2] Documentation/devicetree/bindings/graph.txt + [3] Documentation/devicetree/bindings/media/video-interfaces.txt + [4] Documentation/devicetree/bindings/display/panel/ + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + enum: + - qcom,dsi-phy-28nm-hpm + - qcom,dsi-phy-28nm-lp + - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8960 + - qcom,dsi-phy-14nm + - qcom,dsi-phy-10nm + + reg: + description: > + Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. + + reg-names: + description: > + The names of register regions. For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY "dsi_phy_regulator" + is needed and for DSI 14nm and 10nm PHYs "dsi_phy_lane" is needed. + required: + - "dsi_pll" + - "dsi_phy" + + clock-cells: + description: > + Must be 1. The DSI PHY block acts as a clock provider, creating + 2 clocks: A byte clock (index 0), and a pixel clock (index 1). + const: 1 + + power-domains: + const: <&mmcc MDSS_GDSC> + + clocks: + description: Phandles to device clocks. See [1] for details on clock bindings. + $ref: /schemas/types.yaml#/definitions/phandle + + clock-names: + const: iface + $ref: /schemas/types.yaml#/definitions/string-array + + vddio-supply: + description: > + For 28nm HPM/LP, 28nm 8960 PHYs and 20nm PHY, this is phandle to vdd-io regulator + device node + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: For 14nm PHY and 20nm PHY this is phandle to vcca regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + vdds-supply: + description: For 10nm PHY , phandle to vdds regulator device node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsi-phy-regulator-ldo-mode: + description: Boolean value indicating if the LDO mode PHY regulator is wanted. + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split is enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + $ref: /schemas/types.yaml#/definitions/uint32 + + frame-threshold-time-us: + description: > + For command mode panels, this specifies the idle + time for dsi controller where no active data is + send to the panel, as controller is done sending + active pixels. If there is no desired DSI clocks + specified, then clocks will be derived from this + threshold time, which has a default value in chipset + based on the CPU processing power. + $ref: /schemas/types.yaml#/definitions/uint32 + + dsi_pll_codes: + description: Contain an u32 array data to store dsi pll codes which were passed from UEFI. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-phy-shared: + description: Boolean value indicating if the DSI phy is shared between dual displays. + +required: + - compatible + - reg + - reg-names + - clock-cells + - power-domains + - clocks + - clock-names + - vddio-supply + - vcca-supply + - vdds-supply + +examples: + - | + dsi_phy0: dsi-phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-hpm"; + qcom,dsi-phy-index = <0>; + reg-names = + "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x2b0>, + <0xfd922d80 0x7b>; + clock-names = "iface"; + clocks = <&mmcc MDSS_AHB_CLK>; + #clock-cells = <1>; + vddio-supply = <&pma8084_l12>; + + qcom,dsi-phy-regulator-ldo-mode; + qcom,panel-allow-phy-poweroff; + qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>; + qcom,panel-force-clock-lane-hs; + pll_codes_region = <&dsi_pll_codes_data>; + qcom,dsi-phy-shared; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +... diff --git a/qcom/display/bindings/mdss-dsi-panel.yaml b/qcom/display/bindings/mdss-dsi-panel.yaml new file mode 100644 index 00000000..accf1822 --- /dev/null +++ b/qcom/display/bindings/mdss-dsi-panel.yaml @@ -0,0 +1,2089 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mdss-dsi-panel.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QTI mdss-dsi-panel + +description: > + mdss-dsi-panel is a dsi panel device which supports panels that + are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +properties: + compatible: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + This property specifies the version + for DSI HW that this panel will work with + "qcom,dsi-panel-v2" = DSI V2.0 + + status: + description: > + This property applies to DSI V2 panels only. + This property should not be added for panels + that work based on version "V6.0" + DSI panels that are of different versions + are initialized by the drivers for dsi controller. + A string that has to be set to "okay/ok" + to enable the panel driver. By default this property + will be set to "disable". Will be set to "ok/okay" + status for specific platforms. + default: disable + + qcom,mdss-dsi-panel-controller: + description: > + Specifies the phandle for the DSI controller that + this panel will be mapped to. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,mdss-dsi-panel-width: + description: Specifies panel width in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-height: + description: Specifies panel height in pixels. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bpp: + description: > + Specifies the panel bits per pixel. + 3 = for rgb111 + 8 = for rgb332 + 12 = for rgb444 + 16 = for rgb565 + 18 = for rgb666 + 24 = for rgb888 + enum: [3, 8, 12, 16, 18, 24] + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-destination: + description: > + A string that specifies the destination display for the panel. + "display_1" = DISPLAY_1 + "display_2" = DISPLAY_2 + $ref: /schemas/types.yaml#/definitions/string-array + enum: [display_1, display_2] + + qcom,mdss-dsi-panel-timings: + description: > + An array of length 12 that specifies the PHY timing settings for + the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 12 + maxItems: 12 + + qcom,mdss-dsi-panel-timings-8996: + description: > + An array of length 40 char that specifies the 8996 PHY lane + timing settings for the panel. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 40 + maxItems: 40 + + qcom,mdss-dsi-on-command: + description: > + A byte stream formed by multiple dcs packets base on + qcom dsi controller protocol. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: Message flags + byte 4: wait number of specified ms after dcs command transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in + qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit, + then 3 options can be tried. + 1. Send the packet as a long packet instead + Byte 0: dcs data type = 05 (DCS short Packet) + Byte 0: dcs data type = 29 (DCS long Packet) + 2. Send the packet in one burst by prepending with the next packet in packet stream + Byte 3 = 00 (indicates this is an individual packet) + Byte 3 = 40 (indicates this will be appended to the next + individual packet in the packet stream) + 3. Prepend a NULL packet to the short packet and send both in one burst instead of + combining multiple short packets and sending them in one burst. + + qcom,mdss-dsi-off-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol. + Refer to qcom,mdss-dsi-on-command for command format. + + qcom,mdss-dsi-post-panel-on-command: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + sent after displaying an image. + + qcom,platform-reset-gpio: + description: > + Specifies the reset gpio of primary display, not required for simulation + panels. + + cell-index: + description: Timing node index to help driver maintain the device tree ordering. + + qcom,platform-sec-reset-gpio: + description: Specifies the reset gpio of secondary display. + + qcom,platform-bklight-en-gpio: + description: Specifies the gpio for enabling backlight. + + qcom,mdss-dsi-panel-name: + description: A string used as a descriptive name of the panel + + qcom,vid-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for video mode. + + qcom,vid-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for video mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + default: dsi_lp_mode + + qcom,cmd-on-commands: + description: > + same as "qcom,mdss-dsi-on-command" except commands are + only sent for command mode. + + qcom,cmd-on-commands-state: + description: > + String that specifies the ctrl state for sending panel on commands. + for command mode. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + + qcom,mdss-dsi-physical-type: + description: > + A string used as a decriptive type of the panel. + "oled" : That indicate it's an OLED panel. + "lcd" : That indicate it's an LCD panel. + If it is not set, consider it is a LCD panel as default. + default: lcd + enum: [oled, lcd] + + qcom,mdss-dsi-panel-phy-timings: + description: > + An array of length 'n' char that specifies the DSI PHY lane + timing settings for the panel. This is specific to SDE DRM driver. + The value of 'n' depends on the DSI PHY h/w revision and parsing this + property properly will be taken care in the DSI PHY DRM driver. + + qcom,cmd-sync-wait-broadcast: + description: Boolean used to broadcast dcs command to panels. + + qcom,mdss-dsi-fbc-enable: + description: Boolean used to enable frame buffer compression mode. + + qcom,mdss-dsi-panel-mode-switch: + description: Boolean used to enable panel operating mode switch. + + qcom,poms-align-panel-vsync: + description: Boolean used to align panel TE with timing engine vsync in POMS + + qcom,mdss-dsi-bpp-switch: + description: Boolean used to enable bpp mode switch for non-DSC modes. + + qcom,mdss-dsi-bpp-mode: + description: > + Specifies the panel bits per pixel per timing node, only used when "qcom,mdss-dsi-bpp-switch" + is set. + 24 = for rgb888, default mode if "qcom,mdss-dsi-bpp-mode" is not set. + 30 = for rgb101010. + enum: [24, 30] + + qcom,mdss-dsi-fbc-slice-height: + description: > + Slice height(in lines) of compressed block. + Expressed as power of 2. To set as 128 lines, + this should be set to 7. + + qcom,mdss-dsi-fbc-2d-pred-mode: + description: Boolean to enable 2D map prediction. + + qcom,mdss-dsi-fbc-ver2-mode: + description: Boolean to enable FBC 2.0 that supports 1/3 compression. + + qcom,mdss-dsi-fbc-bpp: + description: > + Compressed bpp supported by the panel. + Specified color order is used as default value. + + qcom,mdss-dsi-fbc-packing: + description: Component packing. 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-quant-error: + description: Boolean used to enable quantization error calculation. + + qcom,mdss-dsi-fbc-bias: + description: > + Bias for CD. + 0 = default value. + default: 0 + + qcom,mdss-dsi-fbc-pat-mode: + description: Boolean used to enable PAT mode. + + qcom,mdss-dsi-fbc-vlc-mode: + description: Boolean used to enable VLC mode. + + qcom,mdss-dsi-fbc-bflc-mode: + description: Boolean used to enable BFLC mode. + + qcom,mdss-dsi-fbc-h-line-budget: + description: > + Per line extra budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-budget-ctrl: + description: > + Extra budget level. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-block-budget: + description: Per block budget. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossless-threshold: + description: > + Lossless mode threshold. + 0 = default value.. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-threshold: + description: > + Lossy mode threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-rgb-threshold: + description: > + Lossy RGB threshold. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-lossy-mode-idx: + description: > + Lossy mode index value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-fbc-max-pred-err: + description: > + Max quantization prediction error. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-back-porch: + description: > + Horizontal back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-front-porch: + description: > + Horizontal front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-pulse-width: + description: > + Horizontal pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-skew: + description: > + Horizontal sync skew value. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-back-porch: + description: > + Vertical back porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-front-porch: + description: > + Vertical front porch value in pixel. + 6 = default value. + default: 6 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-pulse-width: + description: > + Vertical pulse width. + 2 = default value. + default: 2 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-left-border: + description: > + Horizontal left border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-right-border: + description: > + Horizontal right border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-top-border: + description: > + Vertical top border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-v-bottom-border: + description: > + Vertical bottom border in pixel. + 0 = default value + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-underflow-color: + description: > + Specifies the controller settings for the + panel under flow color. + 0xff = default value. + default: 0xff + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-border-color: + description: > + Defines the border color value if border is present. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-jitter: + description: > + Panel jitter value is expressed in terms of numerator + and denominator. It contains two u32 values - numerator + followed by denominator. The jitter configurition causes + the early wakeup if panel needs to adjust before vsync. + Default jitter value is 2.0%. Max allowed value is 10%. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 2 + minItems: 2 + items: + - description: numerator of jitter configuration + - description: denominator of jitter configuration + + qcom,dsi-wd-jitter-enable: + description: Boolean used to enable watchdog jitter in simulator panels + + qcom,dsi-wd-ltj-max-jitter: + description: > + A u32 pair with numerator and denominator specifying the + maximum jitter over a long time. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + + qcom,dsi-wd-ltj-time-sec: + description: A u32 value to specify the time over which the jitter increases. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-prefill-lines: + description: > + An integer value defines the panel prefill lines required to + calculate the backoff time of rsc. + Default value is 16 lines. Max allowed value is vtotal. + default: 16 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-pan-enable-dynamic-fps: + description: Boolean used to enable change in frame rate dynamically. + + qcom,mdss-dsi-pan-fps-update: + description: > + A string that specifies when to change the frame rate. + "dfps_suspend_resume_mode"= FPS change request is + implemented during suspend/resume. + "dfps_immediate_clk_mode" = FPS change request is + implemented immediately using DSI clocks. + "dfps_immediate_porch_mode_hfp" = FPS change request is + implemented immediately by changing panel horizontal + front porch values. + "dfps_immediate_porch_mode_vfp" = FPS change request is + implemented immediately by changing panel vertical + front porch values. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-supported-dfps-list: + description: List containing all the supported refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-supported-qsync-min-fps-list: + description: > + The fps value in this list indicates the qsync min fps + corresponding to the mode in the qcom,dsi-supported-dfps-list with same index. + qcom,dsi-supported-qsync-min-fps-list cannot be defined along with + qcom,mdss-dsi-qsync-min-refresh-rate. "qcom,qsync-enable" property should be + set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,qsync-mode-min-refresh-rate: + description: > + This u32 property is used to define qsync min fps per timing node instead + of using same qsync min fps for different timing modes. For defining qsync min + fps per timing node, this property should be defined in all timing nodes or else + to define single qsync fps for all modes, + "qcom,mdss-dsi-qsync-min-refresh-rate" property can be used. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-list: + description: > + The u32 fps values in this optional list indicate the avr step + requirement for qsync/AVR video mode panels. When a late frame is triggered, + AVR will delay the trigger to ensure the frame transfer snaps to the next step + interval. The step rate must be a common multiple of refresh and min-fps rates. + The values in this list should correspond to the dfps-list with same indeces + when DFPS is used, or a single value which applies to all rates. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-mode-avr-step-fps: + description: > + This u32 property is used to define avr step fps per timing node instead + of using same qsync avr step fps for different timing modes. + For defining avr step fps per timing node, this property should be defined + in all timing nodes or else to define single qsync avr step fps for all modes + use "qcom,mdss-dsi-qsync-avr-step-fps". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-qsync-avr-step-fps: + description: > + A u32 entry to specify avr step rate supported by the panel. + "qcom,qsync-enable" property should be set along with this property + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-min: + description: > + Minimum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. + qcom,mdss-dsi-transfer-time-us must be greater than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-transfer-time-us-max: + description: > + Maximum supported mdp transfer time in us. This entry enables support to + dynamically set the transfer time for the given mode within the defined + range. Both min & max must be defined to enable. This time should not be + greater than vsync duration. + qcom,mdss-dsi-transfer-time-us must be less than this value. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,min-refresh-rate: + description: Minimum refresh rate supported by the panel. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,max-refresh-rate: + description: > + Maximum refresh rate supported by the panel. If max refresh + rate is not specified, then the frame rate of the panel in + qcom,mdss-dsi-panel-framerate is used. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dsi-dyn-clk-enable: + description: > + Boolean to indicate dsi dynamic clock switch feature + is supported. + + qcom,dsi-dyn-clk-type: + description: > + A string that specifies the sub-type for the dynamic + clk feature. If dyn clk type is not specified, default + value "legacy" is used. + "legacy" = FPS is not maintained after dynamic clock switch. + "constant-fps-adjust-hfp" = FPS is maintained even after + dynamic clock switch by changing panel horizontal front + porch values. + "constant-fps-adjust-vfp" = FPS is maintained even after + dynamic clock switch by changing panel vertical front + porch values. + "adjust-hfp" = Dynamic clock switch is achieved by adjusting the + horizontal front porch value according to the qcom,dsi-dyn-hfp-list. + FPS may not be maintained after the switch. + "adjust-vfp" = Dynamic clock switch is achieved by adjusting the + vertical front porch value according to the qcom,dsi-dyn-vfp-list. + FPS may not be maintatined after the switch. + This dyn-clk-type entry is an optional binding which is + contingent on the enabling of dynamic clock switch. + $ref: /schemas/types.yaml#/definitions/string-array + default: legacy + + qcom,mdss-dsi-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for this panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-sec-bl-pmic-control-type: + description: > + A string that specifies the implementation of backlight + control for secondary panel. + "bl_ctrl_pwm" = Backlight controlled by PWM gpio. + "bl_ctrl_wled" = Backlight controlled by WLED. + "bl_ctrl_dcs" = Backlight controlled by DCS commands. + "bl_ctrl_external" = Backlight controlled by externally + other: Unknown backlight control. (default) + $ref: /schemas/types.yaml#/definitions/string-array + default: other + + qcom,mdss-dsi-bl-pwm-pmi: + description: Boolean to indicate that PWM control is through second pmic chip. + + qcom,mdss-dsi-bl-pmic-bank-select: + description: > + LPG channel for backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-pmic-pwm-frequency: + description: > + PWM period in microseconds. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-pwm-gpio: + description: > + PMIC gpio binding to backlight. + Required if backlight pmic control type is PWM + + qcom,mdss-dsi-bl-min-level: + description: > + Specifies the min backlight level supported by the panel. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-max-level: + description: > + Specifies the max backlight level supported by the panel. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-bl-inverted-dbv: + description: > + A boolean to specify whether to invert the display brightness value. + When this boolean is set, will inverted display brightness value. + + qcom,bl-dsc-cmd-state: + description: > + String that specifies the ctrl state for sending dcs brightness commands. + "dsi_hs_mode" = DSI high speed mode (default) + "dsi_lp_mode" = DSI low power mode + If the string was not set, dsi_hs_mode will be set as default mode. + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_hs_mode + enum: [dsi_hs_mode, dsi_lp_mode] + + qcom,mdss-brightness-max-level: + description: > + Specifies the max brightness level supported. + 255 = default value. + default: 255 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,bl-update-flag: + description: > + A string that specifies controls for backlight update of the panel. + "delay_until_first_frame" = Delay backlight update of the panel + until the first frame is received from the HW. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-interleave-mode: + description: > + Specifies interleave mode. + 0 = default value. + default: 0 + + qcom,mdss-dsi-panel-type: + description: > + Specifies the panel operating mode. + "dsi_video_mode" = enable video mode (default). + "dsi_cmd_mode" = enable command mode. + default: dsi_video_mode + + qcom,5v-boost-gpio: + description: Specifies the panel gpio for display 5v boost. + + qcom,mdss-dsi-te-check-enable: + description: Boolean to enable Tear Check configuration. + + qcom,mdss-dsi-te-using-wd: + description: > + Boolean entry enables the watchdog timer support to generate the vsync signal + for command mode panel. By default, panel TE will be used to generate the vsync. + + qcom,mdss-dsi-te-using-te-pin: + description: Boolean to specify whether using hardware vsync. + + qcom,mdss-esync: + description: > + Boolean entry to enable esync. "qcom,mdss-esync-hsync-milli-pulse-width" + property should be set along with this property. + + qcom,mdss-esync-milli-skew: + description: > + u32 entry to specify the skew between the esync signal and the timing + engine, in 1/1000ths of a pulse period. Example: + qcom,mdss-esync-milli-skew = <150>; + This would set the esync signal to precede the timing engine's output by + 0.15 of a pulse period. + default: 0 + + qcom,mdss-esync-hsync-milli-pulse-width: + description: > + u32 entry to specify the pulse width of the hsync portion of the esync + signal, in 1/1000ths of a pulse period. Example: + qcom,mdss-esync-hsync-milli-pulse-width = <750>; + This would set the esync line high for 0.75 of a pulse period, every hsync. + + qcom,mdss-esync-emsync-fps: + description: > + u32 entry to specify how frequently the esync signal should be modulated + with an EM pulse, in Hz. + + qcom,mdss-esync-emsync-milli-pulse-width: + description: > + u32 entry to specify the pulse width of the modulated esync signal, in + 1/1000ths of a pulse period. See "qcom,mdss-esync-hsync-milli-pulse-width". + + qcom,qsync-enable: + description: Boolean property to indicate if qsync is enabled/disabled. + + qcom,mdss-dsi-qsync-min-refresh-rate: + description: > + A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature. + "qcom,qsync-enable" property should be set along with this property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-qsync-on-commands: + description: String that specifies the commands to enable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-on-commands-state: + description: > + String that specifies the ctrl state for sending qsync on commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-qsync-off-commands: + description: String that specifies the commands to disable qsync feature. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-qsync-off-commands-state: + description: > + String that specifies the ctrl state for sending qsync off commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-esync-post-on-commands: + description: > + List of panel resume commands that need to be sent after the esync + generator has been enabled. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,mdss-dsi-sticky_still_en-command: + description: > + Command to enable panel GRAM and write to it in video mode. + + qcom,mdss-dsi-sticky_still_disable-command: + description: > + Command to disable panel GRAM in video mode. + + qcom,mdss-dsi-sticky_on_fly-command: + description: > + Command to enable panel GRAM and write to it for a self refresh for + exactly one frame. + + qcom,mdss-dsi-qsync-freq-step-sequence-interval: + description: > + Array of 3-value tuples that describe the value of the + "qcom,mdss-dsi-qsync-freq-step-sequence" property. + Within each tuple, first value corresponds to the type of frequency + stepping sequence (0 for normal usecase and 1 for video usecase), second + value corresponds to the starting framerate for the sequence (in mHz), + and third value corresponds to the number of steps in the sequence. + + qcom,mdss-dsi-qsync-freq-step-sequence: + description: > + Array of 2-value tuples that describe the framerate and duration of a step + in a sequence. + Within each tuple, first value corresponds to the framerate for this step + in the sequence, and second value corresponds to the duration in frames + of this step. + The tuples are arranged into groups defined by the + "qcom,mdss-dsi-qsync-freq-step-sequence-interval" property, which specifies + the length of a frequency stepping sequence in steps. + + qcom,mdss-dsi-freq-step-pattern1-command: + description: > + List of panel commands to indicate to the panel the beginning of the first + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern2-command: + description: > + List of panel commands to indicate to the panel the beginning of the second + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern3-command: + description: > + List of panel commands to indicate to the panel the beginning of the third + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern4-command: + description: > + List of panel commands to indicate to the panel the beginning of the fourth + frequency stepping pattern, and information about that pattern. + + qcom,mdss-dsi-freq-step-pattern5-command: + description: > + List of panel commands to indicate to the panel the beginning of the fifth + frequency stepping pattern, and information about that pattern. + + qcom,vrr-enable: + description: > + Boolean entry that restricts the inter-vsync frame latching to discrete + boundaries. + + qcom,video-psr-enable: + description: > + Boolean entry to specify that the panel supports GRAM usage in video mode. + + qcom,mdss-dsi-te-pin-select: + description: > + Specifies TE operating mode. + 0 = TE through embedded dcs command + 1 = TE through TE gpio pin. (default) + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-te-dcs-command: + description: > + Inserts the dcs command. + 1 = default value. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-start: + description: > + DCS command for write_memory_start. + 0x2c = default value. + default: 0x2c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-wr-mem-continue: + description: > + DCS command for write_memory_continue. + 0x3c = default value. + default: 0x3c + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-h-sync-pulse: + description: > + Specifies the pulse mode option for the panel. + 0 = Don't send hsa/he following vs/ve packet(default) + 1 = Send hsa/he following vs/ve packet + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-hfp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal front porch (HFP) blanking period. + + qcom,mdss-dsi-hbp-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal back porch (HBP) blanking period. + + qcom,mdss-dsi-hsa-power-mode: + description: > + Boolean to determine DSI lane state during + horizontal sync active (HSA) mode. + + qcom,mdss-dsi-last-line-interleave: + description: > + Boolean to determine if last line + interleave flag needs to be enabled. + + qcom,mdss-dsi-bllp-eof-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) EOF mode. + + qcom,mdss-dsi-bllp-power-mode: + description: > + Boolean to determine DSI lane state during + blanking low power period (BLLP) mode. + + qcom,mdss-dsi-traffic-mode: + description: > + Specifies the panel traffic mode. + "non_burst_sync_pulse" = non burst with sync pulses (default). + "non_burst_sync_event" = non burst with sync start event. + "burst_mode" = burst mode. + default: non_burst_sync_pulse + enum: [non_burst_sync_pulse, non_burst_sync_event, burst_mode] + + qcom,mdss-dsi-pixel-packing: + description: > + Specifies if pixel packing is used (in case of RGB666). + "tight" = Tight packing (default value). + "loose" = Loose packing. + default: tight + enum: [tight, loose] + + qcom,mdss-dsi-virtual-channel-id: + description: > + Specifies the virtual channel identefier. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-color-order: + description: > + Specifies the R, G and B channel ordering. + "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value) + "rgb_swap_rbg" = DSI_RGB_SWAP_RBG + "rgb_swap_brg" = DSI_RGB_SWAP_BRG + "rgb_swap_grb" = DSI_RGB_SWAP_GRB + "rgb_swap_gbr" = DSI_RGB_SWAP_GBR + default: rgb_swap_rgb + enum: [rgb_swap_rgb, rgb_swap_rbg, rgb_swap_brg, rgb_swap_grb, rgb_swap_gbr] + + qcom,mdss-dsi-lane-0-state: + description: Boolean that specifies whether data lane 0 is enabled. + + qcom,mdss-dsi-lane-1-state: + description: Boolean that specifies whether data lane 1 is enabled. + + qcom,mdss-dsi-lane-2-state: + description: Boolean that specifies whether data lane 2 is enabled. + + qcom,mdss-dsi-lane-3-state: + description: Boolean that specifies whether data lane 3 is enabled. + + qcom,mdss-dsi-t-clk-post: + description: > + Specifies the byte clock cycles after mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-t-clk-pre: + description: > + Specifies the byte clock cycles before mode switch. + 0x00 = default value. + default: 0x00 + + qcom,mdss-dsi-stream: + description: > + Specifies the packet stream to be used. + 0 = stream 0 (default) + 1 = stream 1 + default: 0 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,mdss-dsi-mdp-trigger: + description: > + Specifies the trigger mechanism to be used for MDP path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_te] + + qcom,mdss-dsi-dma-trigger: + description: > + Specifies the trigger mechanism to be used for DMA path. + "none" = no trigger + "trigger_te" = Tear check signal line used for trigger + "trigger_sw" = Triggered by software (default) + "trigger_sw_seof" = Software trigger and start/end of frame trigger. + "trigger_sw_te" = Software trigger and TE + $ref: /schemas/types.yaml#/definitions/string-array + default: trigger_sw + enum: [none, trigger_te, trigger_sw, trigger_sw_seof, trigger_sw_te] + + qcom,mdss-dsi-panel-framerate: + description: > + Specifies the frame rate for the panel. + 60 = 60 frames per second (default) + default: 60 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-clockrate: + description: > + A 64 bit value specifies the panel clock speed in Hz. + 0 = default value. + default: 0 + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,mdss-mdp-transfer-time-us: + description: > + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + 14000 = default value. + default: 14000 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-off-command-state: + description: > + String that specifies the ctrl state for sending OFF commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-post-mode-switch-on-command-state: + description: > + String that specifies the ctrl state for sending ON commands post mode switch. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-pan-physical-width-dimension: + description: > + Specifies panel physical width in mm which corresponds + to the physical width in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-pan-physical-height-dimension: + description: > + Specifies panel physical height in mm which corresponds + to the physical height in the framebuffer information. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-panel-test-pin: + description: Specifies the panel test gpio. + + qcom,mdss-dsi-mode-sel-gpio-state: + description: > + String that specifies the lcd mode for panel + (such as single-port/dual-port), if qcom,panel-mode-gpio + binding is defined in dsi controller. + "dual_port" = Set GPIO to LOW + "single_port" = Set GPIO to HIGH + "high" = Set GPIO to HIGH + "low" = Set GPIO to LOW + The default value is "dual_port". + $ref: /schemas/types.yaml#/definitions/string-array + default: dual_port + enum: [dual_port, single_port, high, low] + + qcom,mdss-tear-check-disable: + description: > + Boolean to disable mdp tear check. Tear check is enabled by default to avoid + tearing. Other tear-check properties are ignored if this property is present. + The below tear check configuration properties can be individually tuned if + tear check is enabled. + + qcom,mdss-tear-check-sync-cfg-height: + description: > + Specifies the vertical total number of lines. + The default value is 0xfff0. + default: 0xfff0 + + qcom,mdss-tear-check-sync-init-val: + description: > + Specifies the init value at which the read pointer gets loaded + at vsync edge. The reader pointer refers to the line number of + panel buffer that is currently being updated. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-start: + description: > + Allows the first ROI line write to an panel when read pointer is + between the range of ROI start line and ROI start line plus this + setting. + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-sync-threshold-continue: + description: > + The minimum number of lines the write pointer needs to be + above the read pointer so that it is safe to write to the panel. + (This check is not done for the first ROI line write of an update) + The default value is 4. + default: 4 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-start-pos: + description: > + Specify the y position from which the start_threshold value is + added and write is kicked off if the read pointer falls within that + region. + The default value is panel height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-rd-ptr-trigger-intr: + description: > + Specify the read pointer value at which an interrupt has to be + generated. + The default value is panel height + 1. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-tear-check-frame-rate: + description: > + Specify the value to be a real frame rate(fps) x 100 factor to tune the + timing of TE simulation with more precision. + The default value is 6000 with 60 fps. + $ref: /schemas/types.yaml#/definitions/uint32 + + qqcom,mdss-dsi-reset-sequence: + description: > + An array that lists the + sequence of reset gpio values and sleeps + Each command will have the format defined + as below: + --> Reset GPIO value + --> Sleep value (in ms) + + qcom,partial-update-enabled: + description: > + String used to enable partial + panel update for command mode panels. + "none": partial update is disabled + "single_roi": default enable mode, only single roi is sent to panel + "dual_roi": two rois are merged into one big roi. Panel ddic should be able + to process two roi's along with the DCS command to send two rois. + disabled if property is not specified. This property is specified + per timing node to support resolution restrictions. + $ref: /schemas/types.yaml#/definitions/string-array + default: single_roi + enum: [none, single_roi, dual_roi] + + qcom,mdss-dsi-horizontal-line-idle: + description: > + List of width ranges (EC - SC) in pixels indicating + additional idle time in dsi clock cycles that is needed + to compensate for smaller line width. + + qcom,partial-update-roi-merge: + description: > + Boolean indicates roi combination is need + and function has been provided for dcs + 2A/2B command. This property is specified per timing node to support + resolution restrictions. + + qcom,dcs-cmd-by-left: + description: > + Boolean to indicate that dcs command are sent + through the left DSI controller only in a dual-dsi configuration + + qcom,mdss-dsi-panel-hdr-enabled: + description: > + Boolean to indicate HDR support in panel. + + qcom,mdss-dsi-panel-hdr-color-primaries: + description: > + Array of 8 unsigned integers denoting chromaticity of panel.These + values are specified in nits units. The value range is 0 through 50000. + To obtain real chromacity, these values should be divided by factor of + 50000. The structure of array is defined in below order + value 1: x value of white chromaticity of display panel + value 2: y value of white chromaticity of display panel + value 3: x value of red chromaticity of display panel + value 4: y value of red chromaticity of display panel + value 5: x value of green chromaticity of display panel + value 6: y value of green chromaticity of display panel + value 7: x value of blue chromaticity of display panel + value 8: y value of blue chromaticity of display panel + $ref: /schemas/types.yaml#/definitions/uint32-array + minimum: 0 + maximum: 50000 + items: + - description: x value of white chromaticity of display panel + - description: y value of white chromaticity of display panel + - description: x value of red chromaticity of display panel + - description: y value of red chromaticity of display panel + - description: x value of green chromaticity of display panel + - description: y value of green chromaticity of display panel + - description: x value of blue chromaticity of display panel + - description: y value of blue chromaticity of display panel + + qcom,mdss-dsi-panel-peak-brightness: + description: > + Maximum brightness supported by panel.In absence of maximum value + typical value becomes peak brightness. Value is specified in nits units. + To obtain real peak brightness, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-panel-blackness-level: + description: > + Blackness level supported by panel. Blackness level is defined as + ratio of peak brightness to contrast. Value is specified in nits units. + To obtain real blackness level, this value should be divided by factor of + 10000. + + qcom,mdss-dsi-lp11-init: + description: > + Boolean used to enable the DSI clocks and data lanes (low power 11) + before issuing hardware reset line. + + qcom,mdss-dsi-init-delay-us: + description: > + Delay in microseconds(us) before performing any DSI activity in lp11 + mode. This master delay (t_init_delay as per DSI spec) should be sum + of DSI internal delay to reach fuctional after power up and minimum + delay required by panel to reach functional. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-rx-eot-ignore: + description: Boolean used to enable ignoring end of transmission packets. + + qcom,mdss-dsi-tx-eot-append: + description: Boolean used to enable appending end of transmission packets. + + qcom,ulps-enabled: + description: Boolean to enable support for Ultra Low Power State (ULPS) mode. + + qcom,suspend-ulps-enabled: + description: Boolean to enable support for ULPS mode for panels during suspend state. + + qcom,spr-pack-type: + description: > + String to specify the SPR pack type of panel pixel layout + Expected string for the pack types supported by MDSS are, + "pentile", "rgbw", "yygm", "yygw" + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-roi-alignment: + description: | + Specifies the panel ROI alignment restrictions on its + left, top, width, height alignments and minimum width and + height values. This property is specified per timing node to support + resolution's alignment restrictions. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,esd-check-enabled: + description: Boolean used to enable ESD recovery feature. + + qcom,mdss-dsi-panel-status-command: + description: > + A byte stream formed by multiple dcs packets based on + qcom dsi controller protocol, to read the panel status. + This value is used to kick in the ESD recovery. + byte 0: dcs data type + byte 1: Unused + byte 2: virtual channel number + byte 3: expect ack from client (dcs read command) + byte 4: wait number of specified ms after dcs command + transmitted + byte 5, 6: 16 bits length in network byte order + byte 7 and beyond: number byte of payload + + qcom,mdss-dsi-panel-status-command-mode: + description: > + String that specifies the ctrl state for reading the panel status. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp1-command: + description: > + An optional byte stream to request low + power mode on a panel + + qcom,mdss-dsi-lp1-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-lp2-command: + description: > + An optional byte stream to request ultra + low power mode on a panel + + qcom,mdss-dsi-lp2-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-nolp-command: + description: An optional byte stream to disable low power and ultra low power panel modes + + qcom,mdss-dsi-nolp-command-mode: + description: > + String that specifies the ctrl state for + setting the panel power mode. + "dsi_lp_mode" = DSI low power mode + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,mdss-dsi-panel-status-check-mode: + description: > + Specifies the panel status check method for ESD recovery. + "bta_check" = Uses BTA to check the panel status + "reg_read" = Reads panel status register to check the panel status + "reg_read_nt35596" = Reads panel status register to check the panel + status for NT35596 panel. + "te_signal_check" = Uses TE signal behaviour to check the panel status + enum: [bta_check, reg_read, reg_read_nt35596, te_signal_check] + + qcom,mdss-dsi-panel-status-read-length: + description: > + Integer array that specify the expected read-back length of values + for each of panel registers. Each length is corresponding to number of + returned parameters of register introduced in specification. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-valid-params: + description: > + Integer array that specify the valid returned values which need to check + for each of register. + Some panel need only check the first few values returned from panel. + So: if this property is the same to qcom,mdss-dsi-panel-status-read-length, + then just ignore this one. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,mdss-dsi-panel-status-value: + description: > + Multiple integer arrays, each specifies the values of the panel status register + which is used to check the panel status. The size of each array is the sum of + length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal. + This can cover that Some panel may return several alternative values. + + qcom,mdss-dsi-panel-max-error-count: + description: > + Integer value that specifies the maximum number of errors from register + read that can be ignored before treating that the panel has gone bad. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dynamic-mode-switch-enabled: + description: > + Boolean used to mention whether panel supports + dynamic switching from video mode to command mode + and vice versa. + + qcom,dynamic-mode-switch-type: + description: > + A string specifies how to perform dynamic mode switch. + If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is + dynamic-switch-suspend-resume. + "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will + go blank during transition. + "dynamic-switch-immediate"= Switch on next frame update. Panel will + not go blank for this transition. + "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will + not go blank for this transition. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,mdss-dsi-post-mode-switch-on-command: + description: > + Multiple dcs packets used for turning on DSI panel + after panel has switch modes. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,cmd-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in command mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,cmd-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending command mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-out-commands: + description: > + List of commands that need to be sent + to panel in order to switch out video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-out-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch out + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,video-mode-switch-in-commands: + description: > + List of commands that need to be sent + to panel in order to switch in video mode dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,video-mode-switch-in-commands-state: + description: > + String that specifies the ctrl state for sending video mode switch in + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,send-pps-before-switch: + description: > + Boolean propety to indicate when PPS commands should be sent, + either before or after switch commands during dynamic resolution + switch in DSC panels. If the property is not present, the default + behavior is to send PPS commands after the switch commands. + + qcom,mdss-dsi-panel-orientation: + description: > + String used to indicate orientation of panel + "180" = panel is flipped in both horizontal and vertical directions + "hflip" = panel is flipped in horizontal direction + "vflip" = panel is flipped in vertical direction + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-ack-disabled: + description: > + A boolean property to indicate, whether we need to wait for any ACK from the panel + for any commands that we send. + + qcom,mdss-dsi-force-clock-lane-hs: + description: Boolean to force dsi clock lanes to HS mode always. + + qcom,panel-cphy-mode: + description: Boolean to specify whether panel is using cphy. + + qcom,compression-mode: + description: > + Select compression mode for panel. + "fbc" - frame buffer compression + "dsc" - display stream compression. + "vdc" - VESA display compression. + If "dsc" or "vdc" compression is used then config subnodes needs to be defined. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,panel-supply-entries: + description: > + A node that lists the elements of the supply used to + power the DSI panel. There can be more than one instance + of this binding, in which case the entry would be appended + with the supply entry index. For a detailed description of + fields in the supply entry, refer to the qcom,ctrl-supply-entries + binding above. + + qcom,mdss-dsc-version: + description: > + An 8 bit value indicates the DSC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only DSC rev 1(Major).1(Minor) + right now. + + qcom,mdss-dsc-scr-version: + description: > + Each DSC version can have multiple SCR. This 8 bit value indicates + current SCR revision information supported by panel. + + qcom,mdss-dsc-encoders: + description: > + An integer value indicating how many DSC encoders should be used + to drive data stream to DSI. + Default value is 1 and max value is 2. + 2 encoder should be used only if qcom,mdss-lm-split or + qcom,split-mode with pingpong-split is used. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + + qcom,mdss-dsc-slice-height: + description: An integer value indicates the dsc slice height. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-width: + description: > + An integer value indicates the dsc slice width. + Multiple of slice width should be equal to panel-width. + Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders + are used then minimum slice width is equal to panel-width/4. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-slice-per-pkt: + description: An integer value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-component: + description: An integer value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-bit-per-pixel: + description: An integer value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsc-block-prediction-enable: + description: A boolean value to enable/disable the block prediction at decoder. + + qcom,mdss-dsc-rc-override_v1: + description: A boolean value to enable override rc_range_bpg_ofs in sde_dsc_rc_range_bpg_override_v1. + + qcom,mdss-dsc-config-by-manufacture-cmd: + description: > + A boolean to indicates panel use manufacture command to setup pps + instead of standard dcs type 0x0A. + + qcom,vdc-version: + description: > + An 8 bit value indicates the VDC version supported by panel. Bits[0.3] + provides information about minor version while Bits[4.7] provides + major version information. It supports only VDC rev 1(Major).2(Minor) + right now. + + qqcom,vdc-version-release: + description: An 8 bit value indicated VDC version release. This has to be set to 0. + const: 0 + + qcom,vdc-slice-height: + description: An u32 value which indicates slice height. This should be at least 16 lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-width: + description: > + An u32 value which indicates slice width. This should be at least 64 pixels and + should also be a multiple of 8 + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-slice-per-pkt: + description: An u32 value indicates the slice per dsi packet. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-component: + description: An u32 value indicates the bits per component before compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vdc-bit-per-pixel: + description: An u32 value indicates the bits per pixel after compression. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,src-color-space: + description: > + An u32 value indicating the source color space. It can either be RGB or YUV. + Default value is assumed to be RGB + 0 - RGB + 1 - YUV + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0,1] + + qcom,src-chroma-format: + description: > + An u32 value indicating the source color space. It can either be 444, 420 or 422. + Default value is assumed to be 444 + 0 - 444 + 1 - 422 + 2 - 420 + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: [0, 1, 2] + + qcom,mdss-pps-delay-ms: + description: > + An u32 value that indicates post PPS command + delay in milliseconds. If no value is specified, it chooses zero by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,display-topology: + description: > + Array of u32 values which specifies the list of topologies available + for the display. A display topology is defined by a + set of 3 values in the order: + - number of mixers + - number of compression encoders + - number of interfaces + Therefore, the array should always contain a tuple of 3 elements. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 3 + items: + - description: number of mixers + - description: number of compression encoders + - description: number of interfaces + + qcom,default-topology-index: + description: > + An u32 value which indexes the topology set + specified by the node "qcom,display-topology" + to identify the default topology for the + display. The first set is indexed by the + value 0. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-ext-bridge-mode: + description: External bridge chip is connected instead of panel. + + qcom,mdss-dsi-dma-schedule-line: + description: > + An integer value indicates the line number after vertical active + region for video mode panels and line number after TE for command mode + panels, at which command DMA needs to be triggered. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-dma-schedule-window: + description: > + An integer value indicates the width of the DMA window during which a + DCS command will be triggered for command mode panels + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-mdp-idle-ctrl-en: + description: > + A boolean to enable LP11 insertion after transmission of every line. + This requires command mdp burst mode to be disabled. + + qcom,mdss-dsi-mdp-idle-ctrl-len: + description: > + An u32 value indicating the number of dsi pclk cycles of idle time + to insert between command mode mdp packets. This time must be long + enough to cover the time link takes to switch between HS to LP11 mode. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,vert-padding-value: + description: > + An u32 value indicating the second display height while using two displays + in shared display feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,dba-panel: + description: > + Indicates whether the current panel is used as a display bridge + to a non-DSI interface. + + qcom,bridge-name: + description: > + A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name + is required if qcom,dba-panel is defined for the panel. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,adjust-timer-wakeup-ms: + description: > + An integer value to indicate the timer delay(in ms) to accommodate + s/w delay while configuring the event timer wakeup logic. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mdss-dsi-display-timings: + description: > + Parent node that lists the different resolutions that the panel supports. + Each child represents timings settings for a specific resolution. + + qcom,mdss-dsi-post-init-delay: + description: > + Specifies required number of frames to wait so that panel can be functional + to show proper display. + + qcom,mdss-dsi-video-mode: + description: A boolean to indicates current timing can only work in video mode. + + qcom,mdss-dsi-cmd-mode: + description: A boolean to indicates current timing can only work in command mode. + +# Additional properties added to the second level nodes that represent timings properties: + + qcom,mdss-dsi-timing-default: + description: > + Property that specifies the current child as the default + timing configuration that will be used. + + qcom,mdss-dsi-timing-switch-command: + description: > + List of commands that need to be sent + to panel when the resolution/timing switch happens dynamically. + Refer to "qcom,mdss-dsi-on-command" section for adding commands. + + qcom,mdss-dsi-timing-switch-command-state: + description: > + String that specifies the ctrl state for sending resolution switch + commands. + "dsi_lp_mode" = DSI low power mode (default) + "dsi_hs_mode" = DSI high speed mode + $ref: /schemas/types.yaml#/definitions/string-array + default: dsi_lp_mode + enum: [dsi_lp_mode, dsi_hs_mode] + + qcom,dsi-dyn-clk-list: + description: > + An u32 array of all the supported dsi bit clock + frequencies in Hz for the given mode, listed in + order of preference. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-dyn-clk-hfp-list: + description: > + An u32 array of horizontal front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-hfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,dsi-dyn-clk-vfp-list: + description: > + An u32 array of vertical front porch values corresponding to the + dsi bit clock frequencies in qcom,dsi-dyn-clk-list for the given mode. + This property is essential for the adjust-vfp dynamic clock type, + which is used for specific horizontal porch adjustments when maintaining + a constant frame rate is not required. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,disable-rsc-solver: + description: > + Timing node property to dynamically disable RSC solver for + high FPS usecase due to lower bitclk rate. + +required: + - compatible + - status + - qcom,mdss-dsi-panel-controller + - qcom,mdss-dsi-panel-width + - qcom,mdss-dsi-panel-height + - qcom,mdss-dsi-bpp + - qcom,mdss-dsi-panel-destination + - qcom,mdss-dsi-panel-timings + - qcom,mdss-dsi-panel-timings-8996 + - qcom,mdss-dsi-on-command + - qcom,mdss-dsi-off-command + - qcom,mdss-dsi-post-panel-on-command + - qcom,platform-reset-gpio + +if: + properties: + contains: + const: bl_ctrl_pwm +then: + required: + - qcom,mdss-dsi-bl-pmic-bank-select + - qcom,mdss-dsi-bl-pmic-pwm-frequency + - qcom,mdss-dsi-pwm-gpio + +examples: + - | + &mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "simulator video mode dsi panel"; + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-pixel-packing = <0>; + qcom,mdss-dsi-panel-destination = "display_1"; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-fbc-enable; + qcom,mdss-dsi-panel-mode-switch; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-bpp-switch; + qcom,mdss-dsi-fbc-slice-height = <5>; + qcom,mdss-dsi-fbc-2d-pred-mode; + qcom,mdss-dsi-fbc-ver2-mode; + qcom,mdss-dsi-fbc-bpp = <0>; + qcom,mdss-dsi-fbc-packing = <0>; + qcom,mdss-dsi-fbc-quant-error; + qcom,mdss-dsi-fbc-bias = <0>; + qcom,mdss-dsi-fbc-pat-mode; + qcom,mdss-dsi-fbc-vlc-mode; + qcom,mdss-dsi-fbc-bflc-mode; + qcom,mdss-dsi-fbc-h-line-budget = <0>; + qcom,mdss-dsi-fbc-budget-ctrl = <0>; + qcom,mdss-dsi-fbc-block-budget = <0>; + qcom,mdss-dsi-fbc-lossless-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-threshold = <0>; + qcom,mdss-dsi-fbc-rgb-threshold = <0>; + qcom,mdss-dsi-fbc-lossy-mode-idx = <0>; + qcom,mdss-dsi-fbc-max-pred-err = <2>; + qcom,mdss-dsi-h-front-porch = <140>; + qcom,mdss-dsi-h-back-porch = <164>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <1>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = < 15>; + qcom,mdss-brightness-max-level = <255>; + qcom,bl-update-flag = "delay_until_first_frame"; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-interleave-mode = <0>; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-h-sync-pulse = <1>; + qcom,mdss-dsi-hfp-power-mode; + qcom,mdss-dsi-hbp-power-mode; + qcom,mdss-dsi-hsa-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-last-line-interleave; + qcom,mdss-dsi-traffic-mode = <0>; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-color-order = <0>; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x20>; + qcom,mdss-dsi-t-clk-pre = <0x2c>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-mdp-trigger = <0>; + qcom,mdss-dsi-dma-trigger = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 + 22 27 1e 03 04 00]; + qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 20 06 09 05 03 04 a0 + 23 2e 06 08 05 03 04 a0]; + qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 FF 99]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; + qcom,dsi-supported-dfps-list = <30 45 60>; + qcom,dsi-supported-qsync-min-fps-list = <30 40 55>; + qcom,dsi-qsync-avr-step-list = <0 360 660>; + qcom,dsi-qsync-avr-step-fps = <360>; + qcom,min-refresh-rate = <30>; + qcom,max-refresh-rate = <60>; + qcom,mdss-dsi-bl-pmic-bank-select = <0>; + qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; + qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; + qcom,5v-boost-gpio = <&pm8994_gpios 14 0>; + qcom,mdss-pan-physical-width-dimension = <60>; + qcom,mdss-pan-physical-height-dimension = <140>; + qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode"; + qcom,mdss-tear-check-sync-cfg-height = <0xfff0>; + qcom,mdss-tear-check-sync-init-val = <1280>; + qcom,mdss-tear-check-sync-threshold-start = <4>; + qcom,mdss-tear-check-sync-threshold-continue = <4>; + qcom,mdss-tear-check-start-pos = <1280>; + qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>; + qcom,mdss-tear-check-frame-rate = <6000>; + qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-init-delay-us = <100>; + mdss-dsi-rx-eot-ignore; + mdss-dsi-tx-eot-append; + qcom,ulps-enabled; + qcom,suspend-ulps-enabled; + qcom,mdss-esync; + qcom,mdss-esync-milli-skew = <150>; + qcom,mdss-esync-hsync-milli-pulse-width = <750>; + qcom,mdss-esync-emsync-fps = <240>; + qcom,mdss-esync-emsync-milli-pulse-width = <300>; + qcom,qsync-enable; + qcom,vrr-enable; + qcom,video-psr-enable; + qcom,dsi-qsync-avr-step-fps = <240>; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-read-length = <8>; + qcom,mdss-dsi-panel-max-error-count = <3>; + qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-switch-immediate"; + qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00 + 29 01 00 00 10 00 02 B0 03]; + qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B + 15 01 00 00 00 00 02 C2 08]; + qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03]; + qcom,send-pps-before-switch; + qcom,panel-ack-disabled; + qcom,mdss-dsi-horizontal-line-idle = <0 40 256>, + <40 120 128>, + <128 240 64>; + qcom,mdss-dsi-panel-orientation = "180" + qcom,mdss-dsi-panel-jitter = <0x8 0x10>; + qcom,mdss-dsi-panel-prefill-lines = <0x10>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,platform-reset-gpio = <&tlmm 0 0>; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "adjust-hfp"; + + qcom,mdss-dsi-display-timings { + wqhd { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-bpp-mode = <24>; + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <728>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <424000000>; + qcom,mdss-mdp-transfer-time-us = <12500>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-mdp-transfer-time-us-min = <10000>; + qcom,mdss-mdp-transfer-time-us-max = <15000>; + qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00]; + qcom,mdss-dsi-t-clk-post = <0x02>; + qcom,mdss-dsi-t-clk-pre = <0x2a>; + qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-esync-post-on-commands = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_still_en-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_still_disable-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-sticky_on_fly-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-qsync-freq-step-sequence-interval = + <0 120000 2>, <0 10000 1>; + qcom,mdss-dsi-qsync-freq-step-sequence = + <60000 1>, <10000 1>, + <10000 2>; + qcom,mdss-dsi-freq-step-pattern1-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern2-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern3-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern4-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-freq-step-pattern5-command = [05 01 00 00 a0 00 02 11 00 + 05 01 00 00 02 00 02 29 00]; + qcom,mdss-dsi-timing-switch-command = [ + 29 00 00 00 00 00 02 B0 04 + 29 00 00 00 00 00 02 F1 00]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,qsync-mode-min-refresh-rate = <48>; + qcom,dsi-qsync-mode-avr-step-fps = <360>; + qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 49]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 40]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 04 80 42]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 06 b2 00 5d 01 02 50]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + + qcom,dsi-dyn-clk-list = <524637388 525735938 528842882>; + qcom,dsi-dyn-clk-hfp-list = <52 64 96>; + + qcom,vert-padding-value = <2940>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <4 4 2 2 20 20>; + }; + }; + qcom,panel-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <2800000>; + qcom,supply-max-voltage = <2800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + qcom,dba-panel; + qcom,bridge-name = "adv7533"; + qcom,mdss-dsc-version = <0x11>; + qcom,mdss-dsc-scr-version = <0x1>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsc-config-by-manufacture-cmd; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <0>; + qcom,vdc-version = <0x12>; + qcom,vdc-version-release = <0>; + qcom,vdc-slice-height = <256>; + qcom,vdc-slice-width = <720>; + qcom,vdc-slice-per-pkt = <2>; + qcom,vdc-bit-per-component = <8>; + qcom,vdc-bit-per-pixel = <6>; + qcom,src-color-space = <0>; + qcom,src-chroma-format = <0>; + qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,mdss-dsi-dma-schedule-window = <50>; + }; + }; +... diff --git a/qcom/display/bindings/msm_hdcp.yaml b/qcom/display/bindings/msm_hdcp.yaml new file mode 100644 index 00000000..8ce3fccf --- /dev/null +++ b/qcom/display/bindings/msm_hdcp.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/msm_hdcp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSM HDCP driver + +description: | + Standalone driver managing HDCP related communications between TZ and HLOS for MSM chipset. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,msm-hdcp + +required: + - compatible + +examples: + - | + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; +... diff --git a/qcom/display/bindings/sde-dp.yaml b/qcom/display/bindings/sde-dp.yaml new file mode 100644 index 00000000..b8907930 --- /dev/null +++ b/qcom/display/bindings/sde-dp.yaml @@ -0,0 +1,579 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE DP + +description: | + sde-dp is the master Display Port device which supports DP host controllers that are compatible + with VESA Display Port interface specification. + msm_ext_disp is a device which manages the interaction between external + display interfaces, e.g. Display Port, and the audio subsystem. + [Optional child nodes]: These nodes are for devices which are + dependent on msm_ext_disp. If msm_ext_disp is disabled then + these devices will be disabled as well. Ex. Audio Codec device. + +maintainers: + - Rajkumar Subbiah + - Vishnuvardhan Prodduturi + +properties: + compatible: + const: qcom,dp-display + + reg: + description: | + Base address and length of DP hardware's memory mapped regions. + + reg-names: + description: | + A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region. + "dp_ahb" - AHB memory region. + "dp_aux" - AUX memory region. + "dp_link" - LINK memory region. + "dp_p0" - PCLK0 memory region. + "dp_phy" - PHY memory region. + "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region. + "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region. + "dp_mmss_cc" - Display Clock Control memory region. + "dp_pll" - USB3 DP combo PLL memory region. + "usb3_dp_com" - USB3 DP PHY combo memory region. + "hdcp_physical" - DP HDCP memory region. + "dp_p1" - DP PCLK1 memory region. + "gdsc" - DISPCC GDSC memory region. + + cell-index: + description: Specifies the controller instance. + + '#clock-cells': + description: Denotes the DP driver as a clock producer (has one or more clock outputs) + + clocks: + description: Clocks required for Display Port operation. + + clock-names: + items: + - const: core_aux_clk + - const: core_usb_ref_clk_src + - const: core_usb_pipe_clk + - const: link_clk + - const: link_clk_src + - const: link_iface_clk + - const: pixel_clk_rcg + - const: pixel_parent + - const: pixel1_clk_rcg + - const: strm0_pixel_clk + - const: strm1_pixel_clk + + vdda-1p2-supply: + description: phandle to vdda 1.2V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-0p9-supply: + description: phandle to vdda 0.9V regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,aux-cfg0-settings: + description: | + Specifies the DP AUX configuration 0 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg1-settings: + description: | + Specifies the DP AUX configuration 1 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg2-settings: + description: | + Specifies the DP AUX configuration 2 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg3-settings: + description: | + Specifies the DP AUX configuration 3 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg4-settings: + description: | + Specifies the DP AUX configuration 4 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg5-settings: + description: | + Specifies the DP AUX configuration 5 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg6-settings: + description: | + Specifies the DP AUX configuration 6 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg7-settings: + description: | + Specifies the DP AUX configuration 7 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg8-settings: + description: | + Specifies the DP AUX configuration 8 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,aux-cfg9-settings: + description: | + Specifies the DP AUX configuration 9 settings. The first + entry in this array corresponds to the register offset + within DP AUX, while the remaining entries indicate the + programmable values. + + qcom,max-pclk-frequency-khz: + description: An integer specifying the max. pixel clock in KHz supported by Display Port. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,mst-enable: + description: MST feature enable control node. + + qcom,dsc-feature-enable: + description: DSC feature enable control node. + + qcom,fec-feature-enable: + description: FEC feature enable control node. + + qcom,qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,qos-cpu-latency-us: + description: A u32 value indicating desired PM QoS CPU latency in usec + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,altmode-dev: + description: Phandle for the AltMode GLink driver. + $ref: /schemas/types.yaml#/definitions/phandle + + usb-controller: + description: Phandle for the USB controller. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,pll-revision: + description: PLL hardware revision. + + usb-phy: + description: Phandle for USB PHY driver. This is used to register for USB cable events. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dsc-continuous-pps: + description: | + Control node for sending PPS every frame in hardware for DSC over DP. + This is needed by certain bridge chips where there is such a requirement to do so. + + qcom,dp-aux-switch: + description: Phandle for the driver used to program the AUX switch for Display Port orientation. + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,dp-hpd-gpio: + description: HPD gpio for direct DP connector without USB PHY or AUX switch. + + qcom,dp-gpio-aux-switch: + description: Gpio DP AUX switch chipset support. + + clock-mmrm: + description: | + List of the clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' + properties. The 'DISP_CC' ID of the clock must be used to enable + the property for the respective clock, whereas a value of zero + disables the property. + + vdd_mx-supply: + description: phandle to vdda MX regulator node + $ref: /schemas/types.yaml#/definitions/phandle + + qcom,aux-en-gpio: + description: Specifies the aux-channel enable gpio. + + qcom,aux-sel-gpio: + description: Specifies the aux-channel select gpio. + + qcom,usbplug-cc-gpio: + description: Specifies the usbplug orientation gpio. + + qcom,ext-disp: + description: phandle for msm-ext-display module + $ref: /schemas/types.yaml#/definitions/phandle + + compatible: + const: qcom,msm-ext-disp + + qcom,dp-low-power-hw-hpd: + description: Low power hardware HPD feature enable control node + + qcom,phy-version: + description: Phy version + + pinctrl-names: + description: | + List of names to assign mdss pin states defined in pinctrl device node + Refer to pinctrl-bindings.txt + + pinctrl-<0..n>: + description: | + Lists phandles each pointing to the pin configuration node within a pin + controller. These pin configurations are installed in the pinctrl + device node. Refer to pinctrl-bindings.txt + + qcom,max-lclk-frequency-khz: + description: An integer specifying the max. link clock in KHz supported by Display Port. + + qcom,mst-fixed-topology-ports: + description: u32 values of which MST output port to reserve, start from one + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hbr-rbr-voltage-swing: + description: Specifies the voltage swing levels for HBR and RBR rates. + + qcom,hbr-rbr-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR and RBR rates. + + qcom,hbr2-3-voltage-swing: + description: Specifies the voltage swing levels for HBR2 and HBR3 rates. + + qcom,hbr2-3-pre-emphasis: + description: Specifies the pre-emphasis levels for HBR2 and HBR3 rates. + + compatible: + const: qcom,msm-ext-disp-audio-codec-rx + + ext_disp_audio_codec: + description: Node for Audio Codec. + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + - reg-names + - cell-index + - '#clock-cells' + - clocks + - clock-names + - vdda-1p2-supply + - vdda-0p9-supply + - interrupt-parent + - interrupts + - qcom,aux-cfg0-settings + - qcom,aux-cfg1-settings + - qcom,aux-cfg2-settings + - qcom,aux-cfg3-settings + - qcom,aux-cfg4-settings + - qcom,aux-cfg5-settings + - qcom,aux-cfg6-settings + - qcom,aux-cfg7-settings + - qcom,aux-cfg8-settings + - qcom,aux-cfg9-settings + - qcom,max-pclk-frequency-khz + - qcom,mst-enable + - qcom,dsc-feature-enable + - qcom,fec-feature-enable + - qcom,qos-cpu-mask + - qcom,qos-cpu-latency-us + - qcom,altmode-dev + - usb-controller + - qcom,pll-revision + - usb-phy + - qcom,dp-aux-switch + - qcom,dp-hpd-gpio + - qcom,dp-gpio-aux-switch + - qcom,-supply-entries + +examples: + - | + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + - | + sde_dp: qcom,dp_display@0 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + qcom,dp-aux-switch = <&fsa4480>; + qcom,ext-disp = <&ext_disp>; + qcom,altmode-dev = <&altmode 0>; + usb-controller = <&usb0>; + + reg = <0xae90000 0x0dc>, + <0xae90200 0x0c0>, + <0xae90400 0x508>, + <0xae91000 0x094>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0xaf02000 0x1a0>, + <0x88ea000 0x200>, + <0x88e8000 0x20>, + <0x0aee1000 0x034>, + <0xae91400 0x094>, + <0xaf03000 0x8>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_mmss_cc", "dp_pll", "usb3_dp_com", + "hdcp_physical", "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&clock_rpmh RPMH_CXO_CLK>, + <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, + <&sde_dp DP_PHY_PLL_VCO_DIV_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, + <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; + clock-names = "core_aux_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + clock-mmrm = <0 0 0 0 DISP_CC_MDSS_DP_LINK_CLK_SRC 0 0 0 0 0 0>; + + qcom,pll-revision = "5nm-v1"; + qcom,phy-version = <0x420>; + qcom,dp-aux-switch = <&fsa4480>; + + qcom,aux-cfg0-settings = [1c 00]; + qcom,aux-cfg1-settings = [20 13 23 1d]; + qcom,aux-cfg2-settings = [24 00]; + qcom,aux-cfg3-settings = [28 00]; + qcom,aux-cfg4-settings = [2c 0a]; + qcom,aux-cfg5-settings = [30 26]; + qcom,aux-cfg6-settings = [34 0a]; + qcom,aux-cfg7-settings = [38 03]; + qcom,aux-cfg8-settings = [3c bb]; + qcom,aux-cfg9-settings = [40 03]; + qcom,max-pclk-frequency-khz = <593470>; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + vdda-1p2-supply = <&L6B>; + vdda-0p9-supply = <&L1B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <21700>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <115000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,core-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,core-supply-entry@0 { + reg = <0>; + qcom,supply-name = "refgen"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; +... diff --git a/qcom/display/bindings/sde-dsi.yaml b/qcom/display/bindings/sde-dsi.yaml new file mode 100644 index 00000000..9ff4625e --- /dev/null +++ b/qcom/display/bindings/sde-dsi.yaml @@ -0,0 +1,364 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MDSS DSI + +description: | + mdss-dsi is the master DSI device which supports multiple DSI host controllers + that are compatible with MIPI display serial interface specification. + +maintainers: + - Vara Reddy + - Vishnuvardhan Prodduturi + +pattern properties: + "qcom,+\w+\-supply\-entries": + description: | + A node that lists the elements of the supply used by the + a particular "type" of DSI module. The module "types" + can be "core", "ctrl", and "phy". Within the same type, + there can be more than one instance of this binding, + in which case the entry would be appended with the + supply entry index. + e.g. qcom,ctrl-supply-entry@0 + type: object + patternProperties: + "qcom,ctrl\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,core\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + "qcom,phy\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + +properties: + compatible: + enum: + - qcom,dsi-ctrl-hw-v2.4 + - qcom,dsi-ctrl-hw-v2.5 + - qcom,dsi-ctrl-hw-v2.6 + - qcom,dsi-ctrl-hw-v2.7 + - qcom,dsi-ctrl-hw-v2.8 + - qcom,dsi-ctrl-hw-v2.9 + - qcom,dsi-phy-v3.0 + - qcom,dsi-phy-v4.0 + - qcom,dsi-phy-v4.1 + - qcom,dsi-phy-v4.2 + - qcom,dsi-phy-v4.3 + - qcom,dsi-phy-v4.3.2 + - qcom,dsi-phy-v5.2 + - qcom,dsi-phy-v7.2 + + reg: + description: | + List of base address and length of memory mapped + regions of DSI controller, disp_cc and mdp_intf. + + reg-names: + items: + - const: dsi_ctrl + - const: disp_cc_base + - const: mdp_intf_base + + cell-index: + description: Specifies the controller instance. + + clocks: + items: + - const: mdp_core_clk + - const: iface_clk + - const: core_mmss_clk + - const: bus_clk + - const: byte_clk + - const: pixel_clk + - const: core_clk + - const: byte_clk_rcg + - const: pixel_clk_rcg + + pll-label: + description: Supported versions of DSI PLL. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dsi_pll_5nm, dsi_pll_4nm, dsi_pll_3nm] + + gdsc-supply: + description: phandle to gdsc regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdda-supply: + description: phandle to vdda regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + vcca-supply: + description: phandle to vcca regulator node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: phandle to the interrupt parent device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupts: + description: The interrupt signal from the DSI block. + + qcom,dsi-default-panel: + description: Specifies the default panel. + + qcom,mdp: + description: Specifies the list of phandles to all sde kms device nodes. + + qcom,demura-panel-id: + description: | + Specifies the u64 demura panel ID as an array <2> + If demura is not used this node must be set to <0,0>. + $ref: /schemas/types.yaml#/definitions/uint64 + + qcom,msm-bus,name: + description: String property describing MDSS client. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,msm-bus,num-cases: + description: | + This is the number of bus scaling use cases + defined in the vectors property. This must be + set to <2> for MDSS DSI driver where use-case 0 + is used to remove BW votes from the system. Use + case 1 is used to generate bandwidth requestes + when sending command packets. + + qcom,msm-bus,num-paths: + description: | + This represents number of paths in each bus + scaling usecase. This value depends on number of + AXI master ports dedicated to MDSS for + particular chipset. + + qcom,msm-bus,vectors-KBps: + description: | + A series of 4 cell properties, with a format + of (src, dst, ab, ib) which is defined at + Documentation/devicetree/bindings/arm/msm/msm_bus.txt. + DSI driver should always set average bandwidth + (ab) to 0 and always use instantaneous + bandwidth(ib) values. + + label: + description: String to describe controller. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,platform-te-gpio: + description: Specifies the gpio used for TE. + + qcom,panel-te-source: + description: Specifies the source pin for Vsync from panel or WD Timer. + + qcom,dsi-ctrl: + description: handle to dsi controller device + + qcom,dsi-phy: + description: handle to dsi phy device + + qcom,dsi-ctrl-num: + description: Specifies the DSI controllers to use for primary panel + + qcom,dsi-sec-ctrl-num: + description: Specifies the DSI controllers to use for secondary panel + + qcom,dsi-phy-num: + description: Specifies the DSI PHYs to use for primary panel + + qcom,dsi-sec-phy-num: + description: Specifies the DSI PHYs to use for secondary panel + + qcom,dsi-select-clocks: + description: Specifies the required clocks to use for primary panel + + qcom,dsi-select-sec-clocks: + description: Specifies the required clocks to use for secondary panel + + qcom,dsi-select-sec-sync-clocks: + description: Specifies the required clocks to use for secondary + panel when sync mode is enabled. + + qcom,dsi-display-list: + description: Specifies the list of supported displays. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,dsi-manager: + description: Specifies dsi manager is present + + qcom,dsi-display: + description: Specifies dsi display is present + + qcom,hdmi-display: + description: Specifies hdmi is present + + qcom,dp-display: + description: Specified dp is present + + qcom,mdss-mdp-transfer-time-us: + description: | + Specifies the dsi transfer time for command mode + panels in microseconds. Driver uses this number to adjust + the clock rate according to the expected transfer time. + Increasing this value would slow down the mdp processing + and can result in slower performance. + Decreasing this value can speed up the mdp processing, + but this can also impact power consumption. + As a rule this time should not be higher than the time + that would be expected with the processing at the + dsi link rate since anyways this would be the maximum + transfer time that could be achieved. + If ping pong split enabled, this time should not be higher + than two times the dsi link rate time. + If the property is not specified, then the default value is 14000 us. + + qcom,dsi-phy-pll-bypass: + description: | + A boolean property that enables bypassing hardware access in DSI + PHY/PLL drivers to allow the DSI driver to run on emulation platforms + that might be missing those modules. + + qcom,null-insertion-enabled: + description: A boolean to enable NULL packet insertion feature for DSI controller. + + ports: + description: | + This video port is used when external bridge is present. + The connection is modeled using the OF graph bindings + specified in Documentation/devicetree/bindings/graph.txt. + Video port 0 reg 0 is for the bridge output. The remote + endpoint phandle should be mipi_dsi_device device node. + + qcom,dsi-pll-ssc-en: + description: Boolean property to indicate that ssc is enabled. + + qcom,dsi-pll-ssc-mode: + description: | + Spread-spectrum clocking. It can be either "down-spread" + or "center-spread". Default is "down-spread" if it is not specified. + $ref: /schemas/types.yaml#/definitions/string-array + default: down-spread + enum: [down-spread, center-spread] + + qcom,ssc-frequency-hz: + description: | + Integer property to specify the spread frequency + to be programmed for the SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,ssc-ppm: + description: Integer property to specify the Parts per Million value of SSC. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,avdd-regulator-gpio: + description: Specifies the gpio pin used for avdd power supply regulator. + +required: + - compatible + - reg + - reg-names + - cell-index + - clocks + - clock-names + - pll-label + - gdsc-supply + - vdda-supply + - vcca-supply + - interrupt-parent + - qcom,dsi-default-panel + - qcom,mdp + - qcom,demura-panel-id + - qcom,msm-bus,name + - qcom,msm-bus,num-cases + - qcom,msm-bus,num-paths + - qcom,msm-bus,vectors-KBps + +... diff --git a/qcom/display/bindings/sde-wb.yaml b/qcom/display/bindings/sde-wb.yaml new file mode 100644 index 00000000..b87ecaf9 --- /dev/null +++ b/qcom/display/bindings/sde-wb.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde-wb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + +properties: + compatible: + const: qcom,wb-display + + cell-index: + description: Index of writeback device instance. Default to 0 if not specified. + default: 0 + + label: + description: String to describe this writeback display. Default to "unknown" if not specified. + default: "unknown" + +required: + - compatible + +examples: + - | + sde_wb: qcom,wb-display { + compatible = "qcom,wb-display"; + cell-index = <2>; + label = "wb_display"; + }; +... diff --git a/qcom/display/bindings/sde.yaml b/qcom/display/bindings/sde.yaml new file mode 100644 index 00000000..8f7361bc --- /dev/null +++ b/qcom/display/bindings/sde.yaml @@ -0,0 +1,2076 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sde.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SDE KMS + +maintainers: + - Veera Sundaram Sankaran + - Kalyan Thota + - Ravi Teja Tamatam + - Jatin Srivastava + +description: | + Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user + interface to different panel interfaces. SDE driver is the core of + display subsystem which manage all data paths to different panel interfaces + Please refer to ../../interrupt-controller/interrupts.txt for a general + description of interrupt bindings. + +properties: + compatible: + const: qcom,sde-kms + + qcom,msm-hdmi-audio-rx: + type: object + compatible: + const: qcom,msm-hdmi-audio-codec-rx + + reg: + description: | + Offset and length of the register set for the device.Base address and length of DP hardware's + memory mapped regions. + + reg-names: + description: Names to refer to register sets related to this device + $ref: /schemas/types.yaml#/definitions/string-array + + clocks: + description: List of Phandles for clock device nodes needed by the device. + + clock-names: + description: List of clock names needed by the device. + $ref: /schemas/types.yaml#/definitions/string-array + + mmagic-supply: + description: Phandle for mmagic mdss supply regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + vdd-supply: + description: Phandle for vdd regulator device node. + $ref: /schemas/types.yaml#/definitions/phandle + + interrupt-parent: + description: Must be core interrupt controller. + + interrupts: + description: Interrupt associated with MDSS. + + interrupt-controller: + description: Mark the device node as an interrupt controller. + + '#interrupt-cells': + description: Should be one. The first cell is interrupt number. + + iommus: + description: Specifies the SID's used by this context bank. + + qcom,sde-sspp-type: + description: | + Array of strings for SDE source surface pipes type information. + A source pipe can be "vig", "rgb", "dma" or "cursor" type. + Number of xin ids defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [vig, rgb, dma, cursor] + + qcom,sde-sspp-off: + description: | + Array of offset for SDE source surface pipes. The offsets + are calculated from register "mdp_phys" defined in + reg property + "sde-off". The number of offsets defined here should + reflect the amount of pipes that can be active in SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective source pipes. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ctl-off: + description: | + Array of offset addresses for the available ctl + hw blocks within SDE, these offsets are + calculated from register "mdp_phys" defined in + reg property. The number of ctl offsets defined + here should reflect the number of control paths + that can be configured concurrently on SDE for + this configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-off: + description: | + Array of offset addresses for the programmable + writeback blocks within SDE. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-xin-id: + description: | + Array of VBIF clients ids (xins) corresponding + to the respective writeback. Number of xin ids + defined should match the number of offsets + defined in property: qcom,sde-wb-off.. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-off: + description: | + Array of offset addresses for the available + mixer blocks that can drive data to panel + interfaces. These offsets are be calculated from + register "mdp_phys" defined in reg property. + The number of offsets defined should reflect the + amount of mixers that can drive data to a panel + interface. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-top-off: + description: | + Offset address for the dspp top block. + The offset is calculated from register "mdp_phys" + defined in reg property. + + qcom,sde-dspp-off: + description: | + Array of offset addresses for the available dspp + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-off: + description: | + Array of offset addresses for the available + pingpong blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-slave: + description: | + Array of flags indicating whether each ping pong + block may be configured as a pp slave. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-pp-merge-3d-id: + description: | + Array of index ID values for the merge 3d block + connected to each pingpong, starting at 0. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-merge-3d-off: + description: | + Array of offset addresses for the available + merge 3d blocks. These offsets are calculated + from register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-intf-off: + description: | + Array of offset addresses for the available SDE + interface blocks that can drive data to a + panel controller. The offsets are calculated + from "mdp_phys" defined in reg property. The number + of offsets defined should reflect the number of + programmable interface blocks available in hardware. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-blend-op-off: + description: | + Array of offset addresses for the available + blending stages. The offsets are relative to + qcom,sde-mixer-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-mixer-pair-mask: + description: | + Array of mixer numbers that can be paired with + mixer number corresponding to the array index. + $ref: /schemas/types.yaml#/definitions/uint32-array + + clock-rate: + description: List of clock rates in Hz. + + clock-max-rate: + description: List of maximum clock rate in Hz that this device supports. + + clock-mmrm: + description: | + List of clocks that enable setting the clk rate through MMRM driver. + The order of the list must match the 'clocks' and 'clock-names' properties. + The 'DISP_CC' ID of the clock must be used to enable the property for the + respective clock, whereas a value of zero disables the property. + + qcom,platform-supply-entries: + description: | + A node that lists the elements of the supply. There + can be more than one instance of this binding, + in which case the entry would be appended with + the supply entry index. + e.g. qcom,platform-supply-entry@0 + type: object + patternProperties: + "qcom,platform\-supply\-entry\@+\w": + properties: + reg: + description: offset and length of the register set for the device. + qcom,supply-name: + description: name of the supply (vdd/vdda/vddio) + $ref: /schemas/types.yaml#/definitions/string-array + qcom,supply-min-voltage: + description: minimum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-max-voltage: + description: maximum voltage level (uV) + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-enable-load: + description: load drawn (uA) from enabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-disable-load: + description: load drawn (uA) from disabled supply + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-on-sleep: + description: time to sleep (ms) before turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-on-sleep: + description: time to sleep (ms) after turning on + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-pre-off-sleep: + description: time to sleep (ms) before turning off + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,supply-post-off-sleep: + description: time to sleep (ms) after turning off + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-hw-version: + description: A u32 value indicates the MDSS hw version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,hw-fence-sw-version: + description: | + A u32 value to indicate the hw fencing version. If set to a value + greather than zero, driver will attempt to enable the feature (if + supported by the HW). Otherwise, if this value is not set or set + to zero, feature will remain disabled. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-src-size: + description: A u32 value indicates the address range for each sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-size: + description: A u32 value indicates the address range for each mixer. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ctl-size: + description: A u32 value indicates the address range for each ctl. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-size: + description: A u32 value indicates the address range for each dspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-size: + description: A u32 value indicates the address range for each intf. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-size: + description: A u32 value indicates the address range for each dsc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-size: + description: A u32 value indicates the address range for each vdc. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cdm-size: + description: A u32 value indicates the address range for each cdm. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-size: + description: A u32 value indicates the address range for each pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-merge-3d-size: + description: A u32 value indicates the address range for each merge 3d. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-pp-cwb: + description: | + Array of u32 flags indicating whether each ping pong + block may be configured as a cwb pp block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-size: + description: A u32 value indicates the address range for each writeback. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-len: + description: A u32 entry for SDE address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-intf-max-prefetch-lines: + description: Array of u32 values for max prefetch lines on each interface. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-linewidth: + description: A u32 value indicates the max sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vig-sspp-linewidth: + description: A u32 value indicates the max vig sspp line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-scaling-linewidth: + description: A u32 value indicates the max vig source pipe line width for scaling purposes. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-linewidth: + description: A u32 value indicates the max mixer line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth: + description: A u32 value indicates the max writeback line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-wb-linewidth-linear: + description: A u32 value indicates the max line width supported by WB for linear color formats. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-scale-size: + description: A u32 value indicates the scaling block size on sspp. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blendstages: + description: A u32 value indicates the max mixer blend stages for alpha blending. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qseed-sw-lib-rev: + description: | + A string entry indicates qseed sw library revision + supporting the qseed HW block. It supports + "qseedv3", "qseedv3lite" and "qseedv2" entries for qseed + revision. By default "qseedv2" is used if this + optional property is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: qseedv2 + + qcom,sde-qseed-scalar-version: + description: A u32 value indicating the HW version of the QSEED hardware block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-csc-type: + description: | + A string entry indicates csc support on sspp and wb. + It supports "csc" and "csc-10bit" entries for csc + type. + $ref: /schemas/types.yaml#/definitions/string-array + enum: [csc, csc-10bit] + + qcom,sde-highest-bank-bit: + description: | + Property to specify GPU/Camera/Video highest memory + bank bit used for tile format buffers. First value + in the array represents the ddr type and the second + value is the hbb value corresponding to the ddr type. + + qcom,sde-ubwc-version: + description: | + Property to specify the UBWC feature version. A u32 UBWC version is based on + MDSS support. + + qcom,sde-ubwc-static: + description: Property to specify the default UBWC static configuration value. + + qcom,sde-ubwc-bw-calc-version: + description: A u32 property to specify version of UBWC bandwidth calculation algorithm + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ubwc-swizzle: + description: Property to specify the default UBWC swizzle configuration value. + + qcom,sde-smart-panel-align-mode: + description: | + A u32 property to specify the align mode for + split display on smart panel. Possible values: + 0x0 - no alignment + 0xc - align at start of frame + 0xd - align at start of line + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0x0, 0xc, 0xd] + + qcom,sde-panic-per-pipe: + description: | + Boolean property to indicate if panic signal control feature is available on each + source pipe. + + qcom,sde-has-src-split: + description: | + Boolean property to indicate if source split + feature is available or not. + + qcom,sde-has-dim-layer: + description: | + Boolean property to indicate if mixer has dim layer + feature is available or not. + + qcom,sde-has-idle-pc: + description: | + Boolean property to indicate if target has idle + power collapse feature available or not. + + qcom,sde-wakeup-with-touch: + description: | + Boolean property to indicate if command mode display + will exit from power collapse based on display input + touch event or not. + + qcom,sde-has-mixer-gc: + description: | + Boolean property to indicate if mixer has gamma correction + feature available or not. + + qcom,sde-has-dest-scaler: + description: | + Boolean property to indicate if destination scaler + feature is available or not. + + qcom,sde-max-dest-scaler-input-linewidth: + description: | + A u32 value indicates the + maximum input line width to destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-dest-scaler-output-linewidth: + description: | + A u32 value indicates the + maximum output line width of destination scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-off: + description: | + A u32 value provides the + offset from mdp base to destination scaler block. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-top-size: + description: A u32 value indicates the address range for ds top + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scaler-off: + description: | + Array of u32 offsets indicate the qseed3 scaler blocks + offset from destination scaler top offset. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dest-scaler-size: + description: A u32 value indicates the address range for each scaler block + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-clk-status: + description: | + Array of offsets describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-sspp-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-excl-rect: + description: | + Array of u32 values indicating exclusion rectangle + support on each sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-smart-dma-priority: + description: | + Array of u32 values indicating hw pipe + priority of secondary rectangles when smart dma + is supported. Number of priority values should + match the number of offsets defined in + qcom,sde-sspp-off node. Zero indicates no support + for smart dma for the sspp. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-smart-dma-rev: + description: | + A string entry indicating the smart dma version + supported on the device. Supported entries are + "smart_dma_v1" and "smart_dma_v2". + $ref: /schemas/types.yaml#/definitions/string-array + enum: [smart_dma_v1, smart_dma_v2] + + qcom,sde-vdc-hw-rev: + description: A string indicating the hw version of vdc. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-intf-type: + description: | + Array of string provides the interface type information. + Possible string values + "dsi" - dsi display interface + "dp" - Display Port interface + "hdmi" - HDMI display interface + An interface is considered as "none" if interface type + is not defined. + $ref: /schemas/types.yaml#/definitions/string-array + default: none + enum: [dsi, dp, hdmi] + + qcom,sde-intf-tear-irq-off: + description: | + Array of offset addresses for the available + tear effect (TE) IRQ blocks from "mdp_phys". + There should be one entry per INTF instance with + a zero value for INTFs without TE IRQ block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-emulated-env: + description: | + Boolean property to indicate if the MDSS is running in an + emulated environment. + + qcom,sde-off: + description: SDE offset from "mdp_phys" defined in reg property. + + qcom,sde-cdm-off: + description: | + Array of offset addresses for the available + cdm blocks. These offsets will be calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-off: + description: | + Array of offset addresses for the available + vbif blocks. These offsets will be calculated from + register "vbif_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-size: + description: A u32 value indicates the vbif block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-off: + description: | + A u32 value with the offset for the uidle block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-uidle-size: + description: A u32 value indicates the uidle block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-off: + description: | + A u32 offset indicates the te block offset on pingpong. + This offset is 0x0 by default. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-off: + description: A u32 offset indicates the te2 block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te-size: + description: A u32 value indicates the te block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-te2-size: + description: A u32 value indicates the te2 block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-off: + description: | + Array of offset addresses for the available dsc + blocks. These offsets are calculated from + register "mdp_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-hw-rev: + description: A string value indicates the dsc hw block version. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-dsc-enc: + description: | + Array of offset addresses for the available dsc + encoder blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-ctl: + description: | + Array of offset addresses for the available dsc + ctl blocks. These offsets are calculated from + the corresponding DSC base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dsc-native422-supp: + description: | + Array of flags indicating whether corresponding dsc + block can support native 422 and native 420 + encoding. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dsc-linewidth: + description: A u32 value indicates the max dsc line width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-off: + description: | + A u32 offset address for the available vdc blocks. + This offset is calculated from register "mdp_phys" + defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc-size: + description: A u32 value indicates the enc block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-enc: + description: | + A u32 offset address for the vdc encoder block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl: + description: | + A u32 offset address for the vdc ctl block. This offset is + calculated from qcom,sde-vdc-off. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vdc-ctl-size: + description: A u32 value indicates the ctl block offset range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qdss-off: + description: A u32 offset indicates the qdss block offset. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-off: + description: A u32 offset indicates the dither block offset on pingpong. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-version: + description: A u32 value indicates the dither block version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-cwb-dither: + description: | + Array of u32 flags indicating whether each dither block + may be configured as a cwb dither block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-sspp-vig-blocks: + description: | + A node that lists the blocks inside the VIG hardware. There can + be more than one instance of this binding, in which case the + entry would be appended with the vcm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP VIG contains + that feature hardware. Eg: vcm@0 + type: object + patternProperties: + "vcm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-off: + description: offset of QSEED hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-qseed-size: + description: A u32 address range for qseed scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-gamut: + description: offset and version of 3D LUT Gamut hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-igc: + description: offset and version of 1D LUT IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-vig-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on VIG pipe + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-dma-blocks: + description: | + A node that lists the blocks inside the DMA hardware. There + can be more than one instance of this binding, in which case the + entry would be appended with dgm entry index. Each entry will + contain the offset and version (if needed) of each feature block. + The presence of a block entry indicates that the SSPP DMA contains + that feature hardware. + e.g. qcom,sde-sspp-dma-blocks + -- dgm@0 + type: object + patternProperties: + "dgm@+\w": + properties: + cell-index: + description: A u32 index for the sub-block. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-top-off: + description: A u32 offset of the sub-block top. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-igc: + description: offset and version of DMA IGC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-gc: + description: offset and version of DMA GC + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dma-inverse-pma: + description: | + Boolean property to indicate if inverse PMA feature is + available on DMA pipe. + qcom,sde-dma-csc-off: + description: offset of CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-igc: + description: u32 offset and version of the FP16 IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-unmult: + description: u32 offset and version of the FP16 Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-gc: + description: u32 offset and version of the FP16 GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-fp16-csc: + description: u32 offset and version of the FP16 CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-igc: + description: u32 offset and version of the UCSC IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-unmult: + description: u32 offset and version of the UCSC Unmult hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-gc: + description: u32 offset and version of the UCSC GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-csc: + description: u32 offset and version of the UCSC CSC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-ucsc-alpha-dither: + description: u32 offset and version of the UCSC Alpha Dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-sspp-rgb-blocks: + description: | + A node that lists the blocks inside the RGB hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the SSPP RGB contains that feature hardware. + e.g. qcom,sde-sspp-rgb-blocks + type: object + properties: + qcom,sde-rgb-scaler-off: + description: offset of RGB scaler hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-scaler-size: + description: A u32 address range for scaler. + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-rgb-pcc: + description: offset and version of PCC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-blocks: + description: | + A node that lists the blocks inside the DSPP hardware. The + block entries will contain the offset and version of each + feature block. The presence of a block entry indicates that + the DSPP contains that feature hardware. + e.g. qcom,sde-dspp-blocks + type: object + properties: + qcom,sde-dspp-pcc: + description: offset and version of PCC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gc: + description: offset and version of GC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-igc: + description: offset and version of IGC hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hsic: + description: offset and version of global PA adjustment + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-memcolor: + description: offset and version of PA memcolor hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-sixzone: + description: offset and version of PA sixzone hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-gamut: + description: offset and version of Gamut mapping hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-dither: + description: offset and version of dither hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-hist: + description: offset and version of histogram hardware + $ref: /schemas/types.yaml#/definitions/uint32 + qcom,sde-dspp-vlut: + description: offset and version of PA vLUT hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-mixer-blocks: + description: | + A node that lists the blocks inside the layer mixer hardware. The + block entries will contain the offset and version (if needed) + of each feature block. The presence of a block entry + indicates that the layer mixer contains that feature hardware. + e.g. qcom,sde-mixer-blocks + - qcom,sde-mixer-gc: offset and version of mixer GC hardware + + qcom,sde-dspp-ad-off: + description: | + Array of u32 offsets indicate the ad block offset from the + DSPP offset. Since AD hardware is represented as part of + DSPP block, the AD offsets must be offset from the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-ad-version: + description: A u32 value indicating the version of the AD hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-version: + description: | + A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits) + version of the LTM hardware + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-ltm-off: + description: | + Array of u32 offsets indicate the LTM block offsets from the + DSPP offsets. Since LTM hardware is represented as part of + DSPP block, the LTM offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-rc-version: + description: A u32 value indicating the version of the RC hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-off: + description: | + Array of u32 offsets indicate the RC block offsets from the + DSPP offsets. Since RC hardware is represented as part of + DSPP block, the RC offsets are calculated based on the + corresponding DSPP base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-size: + description: A u32 value indicating the RC block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-mem-size: + description: A u32 value indicating the RC block shared memory size. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-rc-min-region-width: + description: A u32 value indicating the RC block minimum region width. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-off: + description: | + Array of u32 offsets indicate the SPR block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-spr-size: + description: A u32 value indicating the SPR block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-spr-version: + description: A u32 value indicating the version of SPR hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-off: + description: | + Array of u32 offsets indicate the demura block offsets from the + corresponding DSPP block offset as base. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-demura-size: + description: A u32 value indicating the demura block register address range + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-demura-version: + description: A u32 value indicating the version of demura hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-off: + description: | + Array of u32 values indicating the offset of each AIQE block + relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-version: + description: A u32 value indicating the version of the AIQE hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-size: + description: | + A u32 value indicating the shared memory size of each AIQE + hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-off: + description: | + Array of u32 values indicating the offset of each AIQE + dither block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-dither-version: + description: A u32 value indicating the version of the AIQE dither hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-dither-size: + description: | + A u32 value indicating the shared memory size of each AIQE + dither hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-off: + description: | + Array of u32 values indicating the offset of each AIQE + wrapper block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-wrapper-version: + description: A u32 value indicating the version of the AIQE wrapper hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-wrapper-size: + description: | + A u32 value indicating the shared memory size of each AIQE + wrapper hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-off: + description: | + Array of u32 values indicating the offset of each AIQE + AI Scaler block relative to its parent DSPP block. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dspp-aiqe-aiscaler-version: + description: A u32 value indicating the version of the AIQE AI Scaler hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dspp-aiqe-aiscaler-size: + description: | + A u32 value indicating the shared memory size of each AIQE + AI Scaler hardware block instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-aiqe-has-feature-mdnie: + description: Boolean property indicating the presence of AIQE feature mDNIe hardware. + + qcom,sde-aiqe-has-feature-abc: + description: Boolean property indicating the presence of AIQE feature ABC hardware. + + qcom,sde-aiqe-has-feature-ssrc: + description: Boolean property indicating the presence of AIQE feature SSRC hardware. + + qcom,sde-aiqe-has-feature-copr: + description: Boolean property indicating the presence of AIQE feature COPR hardware. + + qcom,sde-aiqe-has-feature-aiscaler: + description: Boolean property indicating the presence of AIQE feature AI Scaler hardware. + + qcom,sde-lm-noise-off: + description: A u32 value indicating noise layer offset from mixer base. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-lm-noise-version: + description: A u32 value indicating the noise layer version. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-id: + description: | + Array of vbif ids corresponding to the + offsets defined in property: qcom,sde-vbif-off. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-default-ot-rd-limit: + description: A u32 value indicates the default read OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-default-ot-wr-limit: + description: A u32 value indicates the default write OT limit + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vbif-dynamic-ot-rd-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the read limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-dynamic-ot-wr-limit: + description: | + A series of 2 cell property, with a format + of (pps, OT limit), where pps is pixel per second and + OT limit is the write limit to apply if the given + pps is not exceeded. + + qcom,sde-vbif-memtype-0: + description: Array of u32 vbif memory type settings, group 0 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-memtype-1: + description: Array of u32 vbif memory type settings, group 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-wb-id: + description: | + Array of writeback ids corresponding to the + offsets defined in property: qcom,sde-wb-off. + + qcom,sde-wb-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-wb-clk-status: + description: | + Array of 2 cell property describing clk status + offsets for clock active state. 1st value + in the array represents offset of the status + register. 2nd value represents bit offset within + status register. Number of offsets defined should + match the number of offsets defined in + property: qcom,sde-wb-off + + qcom,sde-reg-dma-off: + description: | + Array of u32 offset addresses of the dma hardware blocks, + relative to "regdma_phys" defined in reg property. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-id: + description: | + Array of u32 DMA block type ids corresponding to the + offsets declared in property: qcom,sde-reg-dma-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-reg-dma-version: + description: Version of the reg dma hardware blocks. + + qcom,sde-reg-dma-trigger-off: + description: | + Offset of the lut dma trigger reg from "mdp_phys" + defined in reg property. + + qcom,sde-reg-dma-broadcast-disabled: + description: | + Boolean property to indicate if broadcast + functionality in the register dma hardware block should be used. + + qcom,sde-reg-dma-xin-id: + description: VBIF clients id (xin) corresponding to the LUTDMA block. + + qcom,sde-reg-dma-clk-ctrl: + description: | + Array of 2 cell property describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: offset of the control register + - description: bit offset within the control register + + qcom,sde-dram-channels: + description: This represents the number of channels in the Bus memory controller. + + qcom,sde-num-nrt-paths: + description: | + Integer property represents the number of non-realtime + paths in each Bus Scaling Usecase. This value depends on + number of AXI ports that are dedicated to non-realtime VBIF + for particular chipset. + These paths must be defined after rt-paths in + "qcom,msm-bus,vectors-KBps" vector request. + + qcom,sde-max-bw-low-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow. + This is a low bandwidth threshold which should + be applied in most scenarios to be safe from + underflows when unable to satisfy bandwidth + requirements. + + qcom,sde-max-bw-high-kbps: + description: | + This value indicates the max bandwidth in Kbps + that can be supported without underflow in the + event where there is no VFE. + This is a high bandwidth threshold which can be + applied in scenarios where panel interface can + be more tolerant to memory latency such as + command mode panels. + + qcom,sde-core-ib-ff: + description: A string entry indicating the fudge factor for core ib calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-core-clk-ff: + description: | + A string entry indicating the fudge factor for + core clock calculation. + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-min-core-ib-kbps: + description: | + This u32 value indicates the minimum mnoc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-llcc-ib-kbps: + description: | + This u32 value indicates the minimum llcc ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-min-dram-ib-kbps: + description: | + This u32 value indicates the minimum dram ib + vote in Kbps that can be reduced without hitting underflow. + BW calculation logic will choose the IB bandwidth requirement + based on usecase if this floor value is not defined. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-comp-ratio-rt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-comp-ratio-nrt: + description: | + A string entry indicating the compression ratio + for each supported compressed format on non-realtime interface. + The string is composed of one or more of + /// + separated with spaces. + + qcom,sde-undersized-prefill-lines: + description: A u32 value indicates the size of undersized prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-xtra-prefill-lines: + description: A u32 value indicates the extra prefill in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dest-scale-prefill-lines: + description: A u32 value indicates the latency of destination scaler in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-macrotile-prefill-lines: + description: A u32 value indicates the latency of macrotile in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-yuv-nv12-prefill-lines: + description: A u32 value indicates the latency of yuv/nv12 in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-linear-prefill-lines: + description: A u32 value indicates the latency of linear in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-downscaling-prefill-lines: + description: A u32 value indicates the latency of downscaling in lines. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-max-per-pipe-bw-kbps: + description: Array of u32 value indicates the max per pipe bandwidth in Kbps. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-amortizable-threshold: + description: This value indicates the min for traffic shaping in lines. + + qcom,sde-vbif-qos-rt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-nrt-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for non-realtime clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cwb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for concurrent writeback clients. First 8 entries are + for rp_remap and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-lutdma-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for lutdma client. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-cnoc-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for cnoc clients. First 8 entries are for rp_remap and + the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-offline-wb-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for offline-wb clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-vbif-qos-wb-rot-remap: + description: | + This u32 array is used to program vbif qos remapper register + priority for wb-rotation clients. First 8 entries are for rp_remap + and the next 8 entries are for lvl_remap. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-qos-refresh-rates: + description: | + This u32 array indicates danger, safe and creq luts + qos configuration for different refresh rates. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-danger-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the danger luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-safe-lut: + description: | + This u32 array of 18 cell property, with a format of + for each entry, + , indicating the safe luts on sspp and wb. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-creq-lut: + description: | + This u64 array of 18 cell property, with a format of + for each + entry, for qos cases from , with of-node count based + on the qos refresh rates count. + $ref: /schemas/types.yaml#/definitions/uint64-array + + qcom,sde-cdp-setting: + description: | + Array of 2 cell property, with a format of + for cdp use cases in + order of , and . + + qcom,sde-qos-cpu-mask: + description: A u32 value indicating desired PM QoS CPU affine mask. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-mask-performance: + description: | + Each bit represents a CPU mask. For example + 0xf represents 4 cpu cores. These cores can be + silver or gold or gold+. + + qcom,sde-qos-cpu-dma-latency: + description: A u32 value indicating desired PM QoS CPU DMA latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-qos-cpu-irq-latency: + description: A u32 value indicating desired PM QoS CPU irq latency in usec. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-protocol-id: + description: A u32 value indicating ipcc protocol id used for hw fencing feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-ipcc-client-dpu-phys-id: + description: | + A u32 value indicating ipcc physical client id of dpu used + for ipcc registers access. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-inline-rot-xin: + description: An integer array of xin-ids related to inline rotation. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-inline-rot-xin-type: + description: | + A string array indicating the type of xin, + namely sspp or wb. Number of entries should match + the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/string-array + enum: [sspp, wb] + + qcom,sde-inline-rot-clk-ctrl: + description: | + Array of offsets describing clk control + offsets for dynamic clock gating. 1st value + in the array represents offset of the control + register. 2nd value represents bit offset within + control register. Number of offsets defined should + match the number of xin-ids defined in + property: qcom,sde-inline-rot-xin + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-secure-sid-mask: + description: Array of secure SID masks used during secure-camera/secure-display usecases. + $ref: /schemas/types.yaml#/definitions/uint32-array + + '#power-domain-cells': + description: Number of cells in a power-domain specifier and should contain 0. + + '#list-cells': + description: Number of mdp cells, must be 1. + + qcom,sde-mixer-display-pref: + description: | + A string array indicating the preferred display type + for the mixer block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-mixer-cwb-pref: + description: | + A string array indicating the preferred mixer block. + for CWB. Possible values: + "cwb" - preferred for cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [cwb, none] + + qcom,sde-mixer-dcwb-pref: + description: | + A string array indicating the preferred mixer block. + for Dedicated-CWB. Possible values: + "dcwb" - preferred for dedicated-cwb + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [dcwb, none] + + qcom,sde-ctl-display-pref: + description: | + A string array indicating the preferred display type + for the ctl block. Possible values: + "primary" - preferred for primary display + "none" - no preference on display + $ref: /schemas/types.yaml#/definitions/string-array + enum: [primary, none] + + qcom,sde-pipe-order-version: + description: | + A u32 property to indicate version of pipe + ordering block + 0: lower priority pipe has to be on the left for a given pair of pipes. + 1: priority have to be explicitly configured for a given pair of pipes. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + qcom,sde-trusted-vm-env: + description: | + Boolean property to indicate if the device + driver is executing in a trusted VM + + qcom,sde-max-trusted-vm-displays: + description: | + A u32 property to indicate the maximum + number of concurrent displays supported in the + trusted vm environment + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-vm-exclude-reg-names: + description: | + A string array indicating the reg-names which + should be excluded from IO memory validation list + in trusted vm environment + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,tvm-include-reg: + description: | + An array of u32 tuplets indicating the address + ranges of the display sub-device registers + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,vram-size: + description: A u32 value indicating the size of the VRAM in bytes + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,pmic-arb-address: + description: | + A u32 array of display related SPMI address + bit mask, which is a combination of SID and pheripheral id's. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-ib-bw-vote: + description: | + A u32 array of IB bandwidth vote values in kbps for + MNOC, LLCC and DDR/EBI respectively. + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-version: + description: A u32 value indicating the downscale blur version + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-off: + description: | + An array of u32 values with the offset for the downscale blur + block, from the "mdp_phys". + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-size: + description: A u32 value indicates the downscale blur block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-gaus-lut-off: + description: | + An array of u32 values with the offset for gaussian LUT + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-gaus-lut-size: + description: A u32 value indicates the gaussian LUT block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + + qcom,sde-dnsc-blur-dither-off: + description: | + An array of u32 values with the offset for dither + block, from the dnsc-blur-off + $ref: /schemas/types.yaml#/definitions/uint32-array + + qcom,sde-dnsc-blur-dither-size: + description: A u32 value indicates the dither block address range. + $ref: /schemas/types.yaml#/definitions/uint32 + +Bus Scaling: + interconnects: + description: | + An array of 4 cell properties with the format of + (src-noc master-id dst-noc slave-id) as described in: + Documentation/devicetree/bindings/interconnect/interconnect.txt + One entry for each interconnect path available. + Master/Slave ID bindings can be found at: + include/dt-bindings/interconnect/ + $ref: /schemas/types.yaml#/definitions/uint32-array + + interconnect-names: + description: | + An array of string properties associated with "interconnects" + each with a unique name used to lookup the respective path. + The following paths are currently supported: qcom,sde-reg-bus, + qcom,sde-data-bus0, qcom,sde-data-bus1, qcom,sde-llcc-bus, + qcom,sde-ebi-bus + $ref: /schemas/types.yaml#/definitions/string-array + + qcom,sde-reg-bus,vectors-KBps: + description: | + A series of 2 cell properties with a format of + (ab, ib) specified in kilobytes-per-second. + Used when applying reg-bus votes and must be + given whenever "qcom,sde-reg-bus" is used. + + qcom,sde-inline-rotator: + description: | + A 2 cell property, with format of (rotator phandle, + instance id), of inline rotator device. + +patternProperties: + "qcom,smmu_sde_+\w": + description: Child nodes representing sde smmu virtual devices + $ref: /schemas/types.yaml#/definitions/string-array + compatible: + enum: + - qcom,smmu_sde_unsec: + description: smmu context bank device for unsecure sde real time domain. + - qcom,smmu_sde_sec: + description: smmu context bank device for secure sde real time domain. + - qcom,smmu_sde_nrt_unsec: + description: smmu context bank device for unsecure sde non-real time domain. + - qcom,smmu_sde_nrt_sec: + description: smmu context bank device for secure sde non-real time domain. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mmagic-supply + - vdd-supply + - interrupt-parent + - interrupts + - interrupt-controller + - '#interrupt-cells' + - iommus + - qcom,sde-sspp-type + - qcom,sde-sspp-off + - qcom,sde-sspp-xin-id + - qcom,sde-ctl-off + - qcom,sde-wb-off + - qcom,sde-wb-xin-id + - qcom,sde-mixer-off + - qcom,sde-dspp-top-off + - qcom,sde-dspp-off + - qcom,sde-pp-off + - qcom,sde-pp-slave + - qcom,sde-pp-merge-3d-id + - qcom,sde-merge-3d-off + - qcom,sde-intf-off + - qcom,sde-mixer-blend-op-off + - qcom,sde-mixer-pair-mask + +examples: + - | + mdss_mdp: qcom,mdss_mdp@900000 { + compatible = "qcom,sde-kms"; + reg = <0x00900000 0x90000>, + <0x009b0000 0x1040>, + <0x009b8000 0x1040>, + <0x0aeac000 0x00f0>; + reg-names = "mdp_phys", + "vbif_phys", + "vbif_nrt_phys", + "regdma_phys"; + qcom,tvm-include-reg = <0xaf20000 0x4d68>, + <0xaf30000 0x3fd4>; + clocks = <&clock_mmss clk_mdss_ahb_clk>, + <&clock_mmss clk_mdss_axi_clk>, + <&clock_mmss clk_mdp_clk_src>, + <&clock_mmss clk_mdss_mdp_vote_clk>, + <&clock_mmss clk_smmu_mdp_axi_clk>, + <&clock_mmss clk_mmagic_mdss_axi_clk>, + <&clock_mmss clk_mdss_vsync_clk>; + clock-names = "iface_clk", + "bus_clk", + "core_clk_src", + "core_clk", + "iommu_clk", + "mmagic_clk", + "vsync_clk"; + clock-rate = <0>, <0>, <0>; + clock-max-rate= <0 320000000 0>; + qcom,hw-fence-sw-version = <0x1>; + clock-mmrm = <0 0 DISP_CC_MDSS_MDP_CLK_SRC 0 0 0 0>; + mmagic-supply = <&gdsc_mmagic_mdss>; + vdd-supply = <&gdsc_mdss>; + interrupt-parent = <&intc>; + interrupts = <0 83 0>; + interrupt-controller; + #interrupt-cells = <1>; + iommus = <&mdp_smmu 0>; + #power-domain-cells = <0>; + + qcom,sde-hw-version = <0x70000000>; + qcom,sde-emulated-env; + qcom,sde-off = <0x1000>; + qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400 + 0x00002600 0x00002800>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none"; + qcom,sde-mixer-off = <0x00045000 0x00046000 + 0x00047000 0x0004a000>; + qcom,sde-mixer-display-pref = "primary", "none", + "none", "none"; + qcom,sde-mixer-cwb-pref = "none", "none", + "cwb", "none"; + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-off = <0x00055000 0x00057000>; + qcom,sde-dspp-ad-off = <0x24000 0x22800>; + qcom,sde-dspp-ad-version = <0x00030000>; + qcom,sde-dspp-rc-version = <0x00010000>; + qcom,sde-dspp-rc-off = <0x15800 0x14c00>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-min-region-width = <20>; + qcom,sde-dspp-spr-off = <0x15400 0x14400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00010000>; + qcom,sde-dspp-demura-off = <0x15600 0x14800>; + qcom,sde-dspp-demura-size = <0x200>; + qcom,sde-dspp-demura-version = <0x00010000>; + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dest-scaler-top-off = <0x00061000>; + qcom,sde-dest-scaler-off = <0x800 0x1000>; + qcom,sde-wb-off = <0x00066000>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-intf-off = <0x0006b000 0x0006b800 + 0x0006c000 0x0006c800>; + qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi"; + qcom,sde-intf-tear-irq-off = <0 0x6e800 0x6e900 0>; + qcom,sde-pp-off = <0x00071000 0x00071800 + 0x00072000 0x00072800>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1>; + qcom,sde-cdm-off = <0x0007a200>; + qcom,sde-dsc-off = <0x00081000 0x00081400>; + qcom,sde-vdc-off = <0x7C000>; + qcom,sde-vdc-size = <0xf10>; + qcom,sde-vdc-hw-rev = "vdc_1_2"; + qcom,sde-vdc-enc = <0x200>; + qcom,sde-vdc-ctl = <0xf00>; + qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>; + + qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>; + qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 + 0xb0 0xc8 0xe0 0xf8 0x110>; + + qcom,sde-qdss-off = <0x81a00>; + + qcom,sde-sspp-type = "vig", "vig", "vig", + "vig", "rgb", "rgb", + "rgb", "rgb", "dma", + "dma", "cursor", "cursor"; + + qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000 + 0x0000b000 0x00015000 0x00017000 + 0x00019000 0x0001b000 0x00025000 + 0x00027000 0x00035000 0x00037000>; + + qcom,sde-sspp-xin-id = <0 4 8 + 12 1 5 + 9 13 2 + 10 7 7>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, + <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>, + <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>, + <0x3b0 16>; + qcom,sde-scaling-linewidth = <2560>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <2560>; + qcom,sde-mixer-blendstages = <0x7>; + qcom,sde-dsc-linewidth = <2048>; + qcom,sde-highest-bank-bit = <0x7 0x2>; + qcom,sde-ubwc-version = <0x10000000>; + qcom,sde-ubwc-static = <0x100>; + qcom,sde-ubwc-swizzle = <0>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-smart-panel-align-mode = <0xd>; + qcom,sde-panic-per-pipe; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-sspp-src-size = <0x100>; + qcom,sde-mixer-size = <0x100>; + qcom,sde-ctl-size = <0x100>; + qcom,sde-dspp-top-size = <0xc>; + qcom,sde-dspp-size = <0x100>; + qcom,sde-intf-size = <0x100>; + qcom,sde-dsc-size = <0x100>; + qcom,sde-cdm-size = <0x100>; + qcom,sde-pp-size = <0x100>; + qcom,sde-wb-size = <0x100>; + qcom,sde-dest-scaler-top-size = <0xc>; + qcom,sde-dest-scaler-size = <0x800>; + qcom,sde-len = <0x100>; + qcom,sde-wb-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <5120>; + qcom,sde-sspp-scale-size = <0x100>; + qcom,sde-mixer-blendstages = <0x8>; + qcom,sde-qseed-sw-lib-rev = "qseedv2"; + qcom,sde-qseed-scalar-version = <0x3000>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-highest-bank-bit = <15>; + qcom,sde-has-mixer-gc; + qcom,sde-has-idle-pc; + qcom,sde-wakeup-with-touch; + qcom,fullsize-va-map; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-sspp-max-rects = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-excl-rect = <1 1 1 1 + 1 1 1 1 + 1 1 + 1 1>; + qcom,sde-sspp-smart-dma-priority = <0 0 0 0 + 0 0 0 0 + 0 0 + 1 2>; + qcom,sde-smart-dma-rev = "smart_dma_v2"; + qcom,sde-te-off = <0x100>; + qcom,sde-te2-off = <0x100>; + qcom,sde-te-size = <0xffff>; + qcom,sde-te2-size = <0xffff>; + qcom,sde-trusted-vm-env; + + qcom,sde-wb-id = <2>; + qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; + + qcom,sde-qos-refresh-rates = <60 120>; + qcom,sde-danger-lut = <0x3ffff 0x3ffff 0x0 0x0 0x0 0x3fffff 0x3fffff>, + <0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3fffff, + 0xffff0000 0xffff0000>; + qcom,sde-safe-lut = <0xFE00 0xFE00 0xFFFF 0x01 0x03FF 0xF800 0xF800>, + <0xE000 0xE000 0xFFFF 0x01 0x03FF 0xE000 0xF800, 0xff, + 0xff>; + qcom,sde-creq-lut = <0x00112234 0x45566777 0x00112236 0x67777777 + 0x00112234 0x45566777 0x00112236 0x67777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>, + <0x02344455 0x56667777 0x02366677 0x77777777 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x00000000 0x77776541 0x00000000 + 0x02344455 0x56667777 0x02366677 0x77777777 + 0x00123445 0x56677777 0x00123667 0x77777777 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0xf>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x2>; + qcom,sde-ipcc-client-dpu-phys-id = <0x19>; + + qcom,sde-vbif-off = <0 0>; + qcom,sde-vbif-id = <0 1>; + qcom,sde-vbif-default-ot-rd-limit = <32>; + qcom,sde-vbif-default-ot-wr-limit = <16>; + qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>, + <124416000 4>, <248832000 16>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x70>; + + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <1>; + + qcom,sde-max-bw-high-kbps = <9000000>; + qcom,sde-max-bw-low-kbps = <9000000>; + + qcom,sde-core-ib-ff = "1.1"; + qcom,sde-core-clk-ff = "1.0"; + qcom,sde-min-core-ib-kbps = <2400000>; + qcom,sde-min-llcc-ib-kbps = <800000>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3"; + qcom,sde-undersized-prefill-lines = <4>; + qcom,sde-xtra-prefill-lines = <5>; + qcom,sde-dest-scale-prefill-lines = <6>; + qcom,sde-macrotile-prefill-lines = <7>; + qcom,sde-yuv-nv12-prefill-lines = <8>; + qcom,sde-linear-prefill-lines = <9>; + qcom,sde-downscaling-prefill-lines = <10>; + qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000 + 2400000 2400000 2400000 2400000>; + qcom,sde-amortizable-threshold = <11>; + qcom,sde-secure-sid-mask = <0x200801 0x200c01>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,vram-size = <0x200000>; + qcom,pmic-arb-address = <0x3F800 0x3F900 0x3FA00>; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + + qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3 3 3 4 4 5 5 6 3>; + qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4 3 3 3 3 4 4 4 4>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-reg-dma-off = <0 0x400>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00020000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-broadcast-disabled = <0>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0xa00>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + /* Offset from vig top, version of HSIC */ + qcom,sde-vig-hsic = <0x200 0x00010000>; + qcom,sde-vig-memcolor = <0x200 0x00010000>; + qcom,sde-vig-pcc = <0x1780 0x00010000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x800>; + qcom,sde-dma-igc = <0x400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010000>; + qcom,sde-ucsc-unmult = <0x700 0x00010000>; + qcom,sde-ucsc-gc = <0x700 0x00010000>; + qcom,sde-ucsc-csc = <0x700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-dma-igc = <0x1400 0x00050000>; + qcom,sde-dma-gc = <0x600 0x00050000>; + qcom,sde-dma-inverse-pma; + qcom,sde-dma-csc-off = <0x1200>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010000>; + qcom,sde-ucsc-unmult = <0x1700 0x00010000>; + qcom,sde-ucsc-gc = <0x1700 0x00010000>; + qcom,sde-ucsc-csc = <0x1700 0x00010000>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-rgb-blocks { + qcom,sde-rgb-scaler-off = <0x200>; + qcom,sde-rgb-scaler-size = <0x74>; + qcom,sde-rgb-pcc = <0x380 0x00010000>; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x0 0x00010000>; + qcom,sde-dspp-pcc = <0x1700 0x00010000>; + qcom,sde-dspp-gc = <0x17c0 0x00010000>; + qcom,sde-dspp-hsic = <0x0 0x00010000>; + qcom,sde-dspp-memcolor = <0x0 0x00010000>; + qcom,sde-dspp-sixzone = <0x0 0x00010000>; + qcom,sde-dspp-gamut = <0x1600 0x00010000>; + qcom,sde-dspp-dither = <0x0 0x00010000>; + qcom,sde-dspp-hist = <0x0 0x00010000>; + qcom,sde-dspp-vlut = <0x0 0x00010000>; + }; + + qcom,sde-mixer-blocks { + qcom,sde-mixer-gc = <0x3c0 0x00010000>; + }; + + qcom,msm-hdmi-audio-rx { + compatible = "qcom,msm-hdmi-audio-codec-rx"; + }; + + qcom,sde-inline-rotator = <&mdss_rotator 0>; + qcom,sde-inline-rot-xin = <10 11>; + qcom,sde-inline-rot-xin-type = "sspp", "wb"; + qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-pre-on-sleep = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-pre-off-sleep = <0>; + qcom,supply-post-off-sleep = <0>; + }; + }; + + interconnects = <&mmss_noc MASTER_MDP0 &mmss_noc SLAVE_MNOC_HF_MEM_NOC> + <&mmss_noc MASTER_MDP1 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>, + <&gem_noc MASTER_MNOC_HF_MEM_NOC &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1", + "qcom,sde-llcc-bus", "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 76800>, + <0 150000>, + <0 300000>; + + smmu_kms_unsec: qcom,smmu_kms_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&mmss_smmu 0>; + }; + + smmu_kms_sec: qcom,smmu_kms_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&mmss_smmu 1>; + }; + }; +... diff --git a/qcom/display/display/dsi-panel-ext-bridge-1080p.dtsi b/qcom/display/display/dsi-panel-ext-bridge-1080p.dtsi new file mode 100644 index 00000000..0dc8ae2a --- /dev/null +++ b/qcom/display/display/dsi-panel-ext-bridge-1080p.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p { + qcom,mdss-dsi-panel-name = "ext video mode dsi bridge"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x24>; + qcom,mdss-dsi-force-clock-lane-hs; + qcom,mdss-dsi-ext-bridge-mode; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi new file mode 100644 index 00000000..5d19e90e --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-10bit-cmd.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_cmd: qcom,mdss_dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1223800000>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 28 00 28 f2 + 00 02 c2 03 e1 00 0a 03 14 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 03 04 55 77 + 77 77 99 9b 10 00 1e 48 9a bb bc de + f0 11 30 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-10bit-video.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-10bit-video.dtsi new file mode 100644 index 00000000..010d6f73 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-10bit-video.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_dsc_10b_video: qcom,mdss_dsi_nt37801_amoled_dsc_10b_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC 10bit"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 c2 81 + 39 01 00 00 00 00 06 f0 55 aa 52 08 03 + 39 01 00 00 00 00 02 c6 a2 + 39 01 00 00 00 00 06 f0 55 aa 52 08 05 + 39 01 00 00 00 00 02 6f 08 + 39 01 00 00 00 00 06 ec 10 00 00 00 ff + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3b 00 14 00 2c + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 02 c3 19 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 04 c5 0b 0b 0b + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 02 f5 10 + 39 01 00 00 00 00 02 6f 1b + 39 01 00 00 00 00 02 f4 55 + 39 01 00 00 00 00 02 6f 18 + 39 01 00 00 00 00 02 f8 19 + 39 01 00 00 00 00 02 6f 0f + 39 01 00 00 00 00 02 fc 00 + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 ab 2a 00 28 f1 + 9a 02 68 03 92 00 0e 03 14 02 56 10 + ec + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 04 56 77 + 77 77 99 9b f0 00 02 78 9a bb bc dd + ee ff 00 + 39 01 00 00 00 00 02 f3 dc + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 ff 07 ff 0f + ff + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5f 00 + 39 01 00 00 00 00 02 9c 01 + 05 01 00 00 00 00 01 2c + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 b2 55 01 ff 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 00000000..84dfd229 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_fhd_plus_cmd: qcom,mdss_dsi_nt37801_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled fhd plus cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 5F + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 13 93 89 28 00 28 D2 00 02 25 03 B6 00 07 02 AB 02 8B 10 F0 + 39 01 00 00 00 00 13 95 89 28 00 28 D2 00 01 C3 02 FC 00 05 02 AB 03 D1 10 F0 + 39 01 00 00 00 00 02 03 00 + 39 01 00 00 00 00 02 8F 01 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <680000000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2a 00 00 04 37 + 39 01 00 00 00 00 05 2b 00 00 09 5f + 39 01 00 00 00 00 02 90 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 0e 03 dd 00 07 02 77 02 8B 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 8f 01 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi new file mode 100644 index 00000000..f7807289 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <161>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <728870000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <548200000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <728870000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi new file mode 100644 index 00000000..a23f1478 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi new file mode 100644 index 00000000..08e9b8b7 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd_spr: qcom,mdss_dsi_nt37801_wqhd_plus_cmd_spr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC and AP SPR"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsc-version = <0x12>; + qcom,src-chroma-format = <1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 A0 F0 00 32 D1 + 00 01 E2 01 9B 00 3C 02 20 08 A4 11 + 50 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 02 DE 00 + 39 01 00 00 00 00 02 6F 09 + 39 01 00 00 00 00 07 DE 10 34 25 30 14 25 + 39 01 00 00 00 00 05 FF AA 55 A5 81 + 39 01 00 00 00 00 02 6F 1D + 39 01 00 00 00 00 02 FB 6F + + 39 01 00 00 00 00 06 F0 55 AA 52 08 07 + 39 01 00 00 00 00 02 B0 24 + 39 01 00 00 00 00 02 03 10 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi new file mode 100644 index 00000000..5f34e53e --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi @@ -0,0 +1,597 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_cmd: qcom,mdss_dsi_nt37801_wqhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 02 8F 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 02 2f 01 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 24 45 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 01 01 00 01 + 01 01 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 02 02 00 01 + 02 02 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1199900000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 05 2a 00 00 05 9f + 39 01 00 00 00 00 05 2b 00 00 0c 7f + 39 01 00 00 00 00 02 8f 00 + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 02 26 01 + 39 01 00 00 00 00 02 5a 01 + 39 01 00 00 00 00 02 2f 30 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1c + 39 01 00 00 00 00 09 ba 91 03 03 00 01 + 03 03 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 06 c0 54 c0 00 21 43 + 39 01 00 00 00 00 06 f0 55 aa 52 08 02 + 39 01 00 00 00 00 02 cc 30 + 39 01 00 00 00 00 02 ce 01 + 39 01 00 00 20 00 02 cc 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi new file mode 100644 index 00000000..fd8f2e99 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_video_cphy: qcom,mdss_dsi_nt37801_wqhd_plus_vid_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <74>; + qcom,mdss-pan-physical-height-dimension = <161>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi new file mode 100644 index 00000000..f94d9550 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_video_ddicspr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_ddicspr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC and bypass DDIC SPR"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 39 01 00 00 00 00 07 b1 00 10 00 10 00 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi new file mode 100644 index 00000000..21e44730 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_vid_spr: qcom,mdss_dsi_nt37801_wqhd_plus_vid_spr { + qcom,mdss-dsi-panel-name = + "nt37801 amoled vid mode dsi csot panel with DSC and AP SPR"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsc-version = <0x12>; + qcom,src-chroma-format = <1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 D2 + 00 02 86 04 3A 00 0A 02 AB 01 E9 10 + F0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 02 DE 00 + 39 01 00 00 00 00 02 6F 09 + 39 01 00 00 00 00 07 DE 10 34 25 30 14 25 + 39 01 00 00 00 00 05 FF AA 55 A5 81 + 39 01 00 00 00 00 02 6F 1D + 39 01 00 00 00 00 02 FB 6F + + 39 01 00 00 00 00 06 F0 55 AA 52 08 07 + 39 01 00 00 00 00 02 B0 24 + 39 01 00 00 00 00 02 03 10 + + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi new file mode 100644 index 00000000..64d790cd --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_video: qcom,mdss_dsi_nt37801_wqhd_plus_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled video mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + /* + * ############################################################### + * # Pentile SPR phases for SM8750 and later + * ############################################################### + * # RG/BG Type A BG/RG Type A GR/GB Type A GB/GR Type A + * # R B R B ... B R B R ... R B R B ... B R B R ... + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # + * # RG/BG Type B BG/RG Type B GR/GB Type B GB/GR Type B + * # G G G G ... G G G G ... G G G G ... G G G G ... + * # R B R B ... B R B R ... R B R B ... B R B R ... + * ############################################################### + */ + qcom,spr-pentile-pack-type = "BG-RG Type B"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi new file mode 100644 index 00000000..3384bf40 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <22>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi new file mode 100644 index 00000000..5a534706 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_cmd: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync cmd mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <60>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 05 3B 00 18 00 10 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2F 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 39 01 00 00 00 00 02 6f 1f + 39 01 00 00 00 00 02 c0 50 + 39 01 00 00 00 00 02 6f 22 + 39 01 00 00 00 00 03 c0 0C bf + 39 01 00 00 00 00 02 6f 13 + 39 01 00 00 00 00 03 c0 00 cc + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 2f 10 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 02 2f 00 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi new file mode 100644 index 00000000..f1fd60ce --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video_cphy: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid_cphy { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC CPHY"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,panel-cphy-mode; + qcom,spr-pack-type = "pentile"; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <90>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 05 FF AA 55 A5 82 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 03 F3 CC 0C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi new file mode 100644 index 00000000..9b8dfcd4 --- /dev/null +++ b/qcom/display/display/dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_nt37801_amoled_qsync_video: qcom,mdss_dsi_nt37801_qsync_wqhd_plus_vid { + qcom,mdss-dsi-panel-name = + "nt37801 amoled qsync video mode dsi csot panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,spr-pack-type = "pentile"; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <90>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15150 15750 34250 + 15700 12250 35800 6750 2550>; + qcom,mdss-dsi-panel-peak-brightness = <13000000>; + qcom,mdss-dsi-panel-blackness-level = <10>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <44>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 06 F0 55 AA 52 08 00 + 39 01 00 00 00 00 02 C2 81 + 39 01 00 00 00 00 06 F0 55 AA 52 08 03 + 39 01 00 00 00 00 02 C6 A2 + 39 01 00 00 00 00 06 F0 55 AA 52 08 05 + 39 01 00 00 00 00 02 6F 08 + 39 01 00 00 00 00 06 EC 10 00 00 00 FF + 39 01 00 00 00 00 02 17 01 + 39 01 00 00 00 00 05 3B 00 14 00 2C + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 02 C3 19 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 04 C5 0B 0B 0B + 39 01 00 00 00 00 05 FF AA 55 A5 80 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 02 F5 10 + 39 01 00 00 00 00 02 6F 1B + 39 01 00 00 00 00 02 F4 55 + 39 01 00 00 00 00 02 6F 18 + 39 01 00 00 00 00 02 F8 19 + 39 01 00 00 00 00 02 6F 0F + 39 01 00 00 00 00 02 FC 00 + 39 01 00 00 00 00 05 2A 00 00 05 9F + 39 01 00 00 00 00 05 2B 00 00 0C 7F + 39 01 00 00 00 00 03 90 03 03 + 39 01 00 00 00 00 13 91 89 28 00 28 c2 + 00 02 68 04 6c 00 0a 02 77 01 e9 10 + f0 + 39 01 00 00 00 00 05 ff aa 55 a5 81 + 39 01 00 00 00 00 02 6f 23 + 39 01 00 00 00 00 15 fb 00 01 00 11 33 + 33 33 55 57 d0 00 00 44 56 77 78 9a + bc dd f0 + 39 01 00 00 00 00 02 6F 06 + 39 01 00 00 00 00 02 F3 DC + 39 01 00 00 00 00 02 26 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 07 51 07 FF 07 FF 0F + FF + 39 01 00 00 00 00 02 5A 01 + 39 01 00 00 00 00 02 5F 00 + 39 01 00 00 00 00 02 9C 01 + 05 01 00 00 00 00 01 2C + 39 01 00 00 00 00 02 2f 00 + 39 01 00 00 00 00 06 F0 55 AA 52 08 01 + 39 01 00 00 00 00 05 B2 55 01 FF 03 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-rc-override_v1; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/qcom/display/display/dsi-panel-sharp-dsc-4k-cmd.dtsi new file mode 100644 index 00000000..e303a6d5 --- /dev/null +++ b/qcom/display/display/dsi-panel-sharp-dsc-4k-cmd.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,dcs-cmd-by-left; + qcom,mdss-dsi-tx-eot-append; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sharp-dsc-4k-video.dtsi b/qcom/display/display/dsi-panel-sharp-dsc-4k-video.dtsi new file mode 100644 index 00000000..efe59f9b --- /dev/null +++ b/qcom/display/display/dsi-panel-sharp-dsc-4k-video.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <129>; + qcom,mdss-dsi-tx-eot-append; + + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 10 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + /* sleep out + delay 120ms */ + 05 01 00 00 78 00 01 11 + /* display on + delay 120ms */ + 05 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi b/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi new file mode 100644 index 00000000..ff0dfc0f --- /dev/null +++ b/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_cmd: qcom,mdss_dsi_sharp_qhd_plus_dsc_cmd { + qcom,mdss-dsi-panel-name = "Sharp qhd cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-mdp-transfer-time-us = <7933>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 44 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi b/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi new file mode 100644 index 00000000..00a7ea92 --- /dev/null +++ b/qcom/display/display/dsi-panel-sharp-dsc-qhd-plus-video.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sharp_qhd_plus_dsc_video: qcom,mdss_dsi_sharp_qhd_plus_dsc_video { + qcom,mdss-dsi-panel-name = "Sharp qhd video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750 + 15800 13250 34450 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <6450000>; + qcom,mdss-dsi-panel-blackness-level = <4961>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <39>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 04 df 97 51 e8 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 05 d9 00 00 00 04 + 39 01 00 00 00 00 03 bc 3f 66 + 39 01 00 00 00 00 04 dd 66 19 b7 + 39 01 00 00 00 00 07 b7 00 e7 00 00 e7 00 + 39 01 00 00 00 00 07 bb 00 33 69 55 11 33 + 39 01 00 00 00 00 09 cf 66 66 52 52 30 0a + 00 00 + 39 01 00 00 00 00 03 c1 58 10 + 39 01 00 00 00 00 08 c3 12 05 00 00 45 01 + 45 + 39 01 00 00 00 00 0a c4 03 06 18 54 00 08 + 00 0b 10 + 39 01 00 00 00 00 34 c6 00 12 45 00 08 00 + 0b 01 20 25 30 01 49 01 49 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 03 00 00 00 45 01 45 4b 02 4b 05 + 05 05 05 + 39 01 00 00 00 00 0e ce 00 41 25 01 40 03 + 49 00 99 01 49 01 49 + 39 01 00 00 00 00 36 d0 00 02 00 08 04 0a + 06 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 36 d1 00 03 01 09 05 0b + 07 1f 1f 1f 1f 1f 1f 1f 1f 10 1f 1f 1f 1f + 1f 1f 1f 1f 1f 1f 1f af af af af af af ff + ff ff ff ff ff ff ff aa ff ff ff ff ff ff + ff ff ff ff ff + 39 01 00 00 00 00 3a d4 03 00 00 32 5a 07 + 32 5a 0c 40 00 04 00 00 00 01 00 02 41 25 + 60 00 00 20 00 01 02 01 40 00 73 00 05 01 + 20 25 30 00 0a 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 08 02 02 04 + 39 01 00 00 00 00 31 d5 00 00 00 00 00 00 + 00 00 00 00 00 01 49 01 49 00 00 07 40 40 + 07 99 00 99 00 00 00 00 03 00 00 00 00 00 + 00 1f 00 1f 03 49 03 c0 00 00 02 06 08 08 + 39 01 00 00 00 00 02 de 02 + 39 01 00 00 00 00 09 c9 71 7d 94 18 71 7d + 94 18 + 39 01 00 00 00 00 09 bb 00 5c 4e 40 40 40 + 40 40 + 39 01 00 00 00 00 02 c7 08 + 39 01 00 00 00 00 0d cc 15 85 54 a6 15 85 + 54 a6 82 d0 04 3c + 39 01 00 00 00 00 0b c2 00 00 40 f0 01 f0 + 14 9d 0a 29 + 39 01 00 00 00 00 02 de 03 + 39 01 00 00 00 00 03 b0 04 f0 + 39 01 00 00 00 00 02 b2 10 + 39 01 00 00 00 00 02 b3 01 + 39 01 00 00 00 00 5a b4 00 11 00 00 8a 30 + 80 0c 30 02 d0 00 08 01 68 01 68 02 00 01 + b4 00 20 00 97 00 05 00 0c 0d b7 13 12 18 + 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a + 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 + 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a + 78 1a b6 2a f6 2b 34 2b 74 3b 74 6b f4 + 39 01 00 00 00 00 02 b5 68 + 39 01 00 00 00 00 0c b7 00 08 00 12 08 70 + 0f 00 16 11 bf + 39 01 00 00 00 00 02 de 04 + 39 01 00 00 00 00 12 b0 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 b6 00 + 39 01 00 00 00 00 03 bf 02 ff + 39 01 00 00 00 00 1a eb 00 02 00 02 00 03 + 00 00 00 00 00 00 ab 00 02 0b 00 18 00 00 + 00 00 00 00 00 + 39 01 00 00 00 00 0c b2 7c ea ca 07 11 12 + 07 00 05 02 02 + 39 01 00 00 00 00 2c ed 00 00 00 00 00 + 00 00 00 00 00 00 00 05 00 00 10 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 39 01 00 00 00 00 02 de 06 + 39 01 00 00 00 00 16 b2 01 40 00 e7 9e 79 + 9e 79 e7 79 e7 9e 9e 79 e7 e7 9e 79 9e 79 + e7 + 39 01 00 00 00 00 02 bd 20 + 39 01 00 00 00 00 02 de 07 + 39 01 00 00 00 00 14 b0 53 aa 01 1d 1e 01 + 1e 3d 05 18 13 0f 1d 2c 0f 2d 3d 05 17 + 39 01 00 00 00 00 05 b2 00 00 00 00 + 39 01 00 00 00 00 0e b3 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b4 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b5 00 e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e b6 00 29 ab 67 83 45 + 01 92 ba 76 38 54 10 + 39 01 00 00 00 00 0e b7 00 01 23 45 67 89 + ab 10 32 54 76 98 ba + 39 01 00 00 00 00 0e b8 00 9a b6 78 34 50 + 12 a9 6b 87 43 05 21 + 39 01 00 00 00 00 0e b9 0f e0 12 34 56 78 + 9a 0e 21 43 65 87 a9 + 39 01 00 00 00 00 0e ba 00 2c d5 01 83 4b + 67 c2 e4 10 38 5a 76 + 39 01 00 00 00 00 04 bb 1e cc 66 + 39 01 00 00 00 00 11 bc 0c ed ce af 88 69 + 4a 2b 04 e5 c6 a7 80 61 42 23 + 39 01 00 00 00 00 11 bd 0c ad ce ef 08 29 + 4a 6b 84 a5 c6 e7 00 21 42 63 + 39 01 00 00 00 00 05 be 3f ff ff ff + 39 01 00 00 00 00 05 bf 3e ff ff ff + 39 01 00 00 00 00 05 c0 2b ff ff ff + 39 01 00 00 00 00 05 c1 1a 7f fb ff + 39 01 00 00 00 00 05 c2 1a ff ff ff + 39 01 00 00 00 00 05 c3 15 ff ff ff + 39 01 00 00 00 00 05 c4 15 ff ff ff + 39 01 00 00 00 00 05 c5 00 ff ff ff + 39 01 00 00 00 00 03 c6 00 00 + 39 01 00 00 00 00 03 c7 00 00 + 39 01 00 00 00 00 05 c8 22 00 00 00 + 39 01 00 00 00 00 0c c9 10 f1 f0 ff + ff ff ff ff ff ee 02 + 39 01 00 00 00 00 02 de 08 + 39 01 00 00 00 00 1a b2 52 07 11 01 + 13 41 02 01 11 11 0e 15 15 15 0e 0e + 0e 0e 0e 0e 0e 0e 0e 15 15 + 39 01 00 00 00 00 02 b6 18 + 39 01 00 00 00 00 02 de 0a + /* 8bit 78 10bit 7f */ + 39 01 00 00 00 00 04 d5 3f 78 00 + 39 01 00 00 00 00 02 de 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 be 2c e0 + 39 01 00 00 00 00 03 c0 27 78 + 39 01 00 00 00 00 08 cc 00 b3 0c 24 02 + 33 0c + 39 01 00 00 00 00 05 b0 01 23 06 09 + 39 01 00 00 78 00 01 11 + 39 01 00 00 78 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 02 de 00 + 05 01 00 00 05 00 01 28 + 05 01 00 00 78 00 01 10 + ]; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-cmd-au.dtsi b/qcom/display/display/dsi-panel-sim-cmd-au.dtsi new file mode 100644 index 00000000..fcb8df52 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-cmd-au.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_panel_au: qcom,mdss_dsi_cmd_sim_panel_au { + qcom,mdss-dsi-panel-name = "cmd mode dsi sim panel au"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,vert-padding-value = <2940>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 07 FF + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 02 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-cmd.dtsi b/qcom/display/display/dsi-panel-sim-cmd.dtsi new file mode 100644 index 00000000..813fe166 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-cmd.dtsi @@ -0,0 +1,1280 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_cmd: qcom,mdss_dsi_sim_cmd { + qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-mode-switch; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-t-clk-post = <0x03>; + qcom,mdss-dsi-t-clk-pre = <0x27>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,panel-ack-disabled; + qcom,qsync-enable; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,cmd-on-commands = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + qcom,vid-on-commands = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + ]; + qcom,video-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 10 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0c + ]; + qcom,video-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-in-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 04 80 49 + 15 01 00 00 00 00 02 3d 11 + 15 01 00 00 00 00 02 36 00 + 15 01 00 00 00 00 02 55 0b + ]; + qcom,cmd-mode-switch-in-commands-state = "dsi_lp_mode"; + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 03 b0 a5 00 + 07 01 00 00 00 00 02 01 00 + 39 01 00 00 00 00 06 b2 00 5d 01 02 49 + ]; + qcom,cmd-mode-switch-out-commands-state = "dsi_lp_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <110>; + qcom,mdss-dsi-h-back-porch = <110>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <90>; + qcom,mdss-dsi-v-front-porch = <110>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <840>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,disable-rsc-solver; + + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00]; + /* CABC brightness */ + + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <240>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,disable-rsc-solver; + + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@8 { + cell-index = <8>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <460>; + qcom,mdss-dsi-h-pulse-width = <40>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <100>; + qcom,mdss-dsi-v-front-porch = <100>; + qcom,mdss-dsi-v-pulse-width = <40>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-timings = + [00 21 09 09 24 23 08 08 08 03 04 00]; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@9 { + cell-index = <9>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <1>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@10 { + cell-index = <10>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <5>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@11 { + cell-index = <11>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <10>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@12 { + cell-index = <12>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@13 { + cell-index = <13>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@14 { + cell-index = <14>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-mdp-transfer-time-us = <15866>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@15 { + cell-index = <15>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@16 { + cell-index = <16>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@17 { + cell-index = <17>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3660>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@18 { + cell-index = <18>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3200>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <12>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,mdss-dsi-on-command = + [29 01 00 00 00 00 02 b0 03 + 05 01 00 00 0a 00 01 00 + /* Soft reset, wait 10ms */ + 15 01 00 00 0a 00 02 3a 77 + /* Set Pixel format (24 bpp) */ + 39 01 00 00 0a 00 05 2a 00 00 04 ff + /* Set Column address */ + 39 01 00 00 0a 00 05 2b 00 00 05 9f + /* Set page address */ + 15 01 00 00 0a 00 02 35 00 + /* Set tear on */ + 39 01 00 00 0a 00 03 44 00 00 + /* Set tear scan line */ + 15 01 00 00 0a 00 02 51 ff + /* write display brightness */ + 15 01 00 00 0a 00 02 53 24 + /* write control brightness */ + 15 01 00 00 0a 00 02 55 00 + /* CABC brightness */ + 05 01 00 00 78 00 01 11 + /* exit sleep mode, wait 120ms */ + 05 01 00 00 10 00 01 29]; + /* Set display on, wait 16ms */ + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/qcom/display/display/dsi-panel-sim-dsc-10bit-cmd.dtsi new file mode 100644 index 00000000..8e5cba14 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-dsc-10bit-cmd.dtsi @@ -0,0 +1,1230 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC3:1 10bit dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <30>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <180>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,disable-rsc-solver; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-framerate = <240>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,disable-rsc-solver; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <1>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@7 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <10>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@8 { + cell-index = <8>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <24>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@9 { + cell-index = <9>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-mdp-transfer-time-us = <15652>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@10 { + cell-index = <10>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + + timing@11 { + cell-index = <11>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 28 00 01 29]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-version = <0x12>; + qcom,mdss-dsc-slice-height = <20>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <10>; + qcom,mdss-dsc-block-prediction-enable; + qcom,src-chroma-format = <1>; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-dsc375-cmd.dtsi b/qcom/display/display/dsi-panel-sim-dsc375-cmd.dtsi new file mode 100644 index 00000000..bed6ed91 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-dsc375-cmd.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Simulator cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <10>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 ff 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1e + 15 01 00 00 00 00 02 0b 73 + 15 01 00 00 00 00 02 0c 73 + 15 01 00 00 00 00 02 0e b0 + 15 01 00 00 00 00 02 0f aE + 15 01 00 00 00 00 02 11 b8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5a 00 + 15 01 00 00 00 00 02 5b 01 + 15 01 00 00 00 00 02 5c 80 + 15 01 00 00 00 00 02 5d 81 + 15 01 00 00 00 00 02 5e 00 + 15 01 00 00 00 00 02 5f 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1c + 15 01 00 00 00 00 02 01 0b + 15 01 00 00 00 00 02 02 0c + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0f + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8a + 15 01 00 00 00 00 02 0a 13 + 15 01 00 00 00 00 02 0b 13 + 15 01 00 00 00 00 02 0c 15 + 15 01 00 00 00 00 02 0d 15 + 15 01 00 00 00 00 02 0e 17 + 15 01 00 00 00 00 02 0f 17 + 15 01 00 00 00 00 02 10 1c + 15 01 00 00 00 00 02 11 0b + 15 01 00 00 00 00 02 12 0c + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0f + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8a + 15 01 00 00 00 00 02 1a 13 + 15 01 00 00 00 00 02 1b 13 + 15 01 00 00 00 00 02 1c 15 + 15 01 00 00 00 00 02 1d 15 + 15 01 00 00 00 00 02 1e 17 + 15 01 00 00 00 00 02 1f 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6d + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 e0 00 + 15 01 00 00 00 00 02 dc 21 + 15 01 00 00 00 00 02 dd 22 + 15 01 00 00 00 00 02 de 07 + 15 01 00 00 00 00 02 df 07 + 15 01 00 00 00 00 02 e3 6d + 15 01 00 00 00 00 02 e1 07 + 15 01 00 00 00 00 02 e2 07 + /* UD */ + 15 01 00 00 00 00 02 29 d8 + 15 01 00 00 00 00 02 2a 2a + /* CLK */ + 15 01 00 00 00 00 02 4b 03 + 15 01 00 00 00 00 02 4c 11 + 15 01 00 00 00 00 02 4d 10 + 15 01 00 00 00 00 02 4e 01 + 15 01 00 00 00 00 02 4f 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5b 43 + 15 01 00 00 00 00 02 5c 00 + 15 01 00 00 00 00 02 5f 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7a 80 + 15 01 00 00 00 00 02 7b 91 + 15 01 00 00 00 00 02 7c d8 + 15 01 00 00 00 00 02 7d 60 + 15 01 00 00 00 00 02 7f 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 b3 c0 + 15 01 00 00 00 00 02 b4 00 + 15 01 00 00 00 00 02 b5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0a + 15 01 00 00 00 00 02 94 0a + /* Inversion Type */ + 15 01 00 00 00 00 02 8a 00 + 15 01 00 00 00 00 02 9b ff + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9d b0 + 15 01 00 00 00 00 02 9f 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 ec 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VESA DSC PPS settings + * (1440x2560 slide 16H) + */ + 39 01 00 00 00 00 11 c1 09 + 20 00 10 02 00 02 68 01 bb + 00 0a 06 67 04 c5 + + 39 01 00 00 00 00 03 c2 10 f0 + /* C0h = 0x0(2 Port SDC) + * 0x01(1 PortA FBC) + * 0x02(MTK) 0x03(1 PortA VESA) + */ + 15 01 00 00 00 00 02 c0 03 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3b 03 0a 0a + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 e5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 bb 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 fb 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <0>; + qcom,mdss-dsi-h-back-porch = <0>; + qcom,mdss-dsi-h-pulse-width = <0>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <0>; + qcom,mdss-dsi-v-front-porch = <0>; + qcom,mdss-dsi-v-pulse-width = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 15 01 00 00 00 00 02 bb 10 + 15 01 00 00 00 00 02 b0 03 + 05 01 00 00 78 00 01 11 + 15 01 00 00 00 00 02 51 ff + 15 01 00 00 00 00 02 53 24 + 15 01 00 00 00 00 02 ff 23 + 15 01 00 00 00 00 02 08 05 + 15 01 00 00 00 00 02 46 90 + 15 01 00 00 00 00 02 ff 10 + 15 01 00 00 00 00 02 ff f0 + 15 01 00 00 00 00 02 92 01 + 15 01 00 00 00 00 02 ff 10 + /* enable TE generation */ + 15 01 00 00 00 00 02 35 00 + 05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 10 00 01 28 + 05 01 00 00 40 00 01 10]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-dualmipi-cmd.dtsi b/qcom/display/display/dsi-panel-sim-dualmipi-cmd.dtsi new file mode 100644 index 00000000..275c0960 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-dualmipi-cmd.dtsi @@ -0,0 +1,263 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd { + qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + qcom,mdss-dsi-bpp-switch; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <30>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-mdp-transfer-time-us-min = <14000>; + qcom,mdss-mdp-transfer-time-us-max = <16000>; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <28>; + qcom,mdss-dsi-h-back-porch = <4>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <12>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,dsi-wd-jitter-enable; + qcom,mdss-dsi-panel-jitter = <0x2 0x1>; + qcom,dsi-wd-ltj-max-jitter = <0x4 0x1>; + qcom,dsi-wd-ltj-time-sec = <3600>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-mdp-transfer-time-us-min = <6900>; + qcom,mdss-mdp-transfer-time-us-max = <7900>; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <40>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@4 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <80>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + + timing@5 { + cell-index = <5>; + qcom,mdss-dsi-bpp-mode= <24>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <80>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + + timing@6 { + cell-index = <6>; + qcom,mdss-dsi-bpp-mode= <30>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <80>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command = [05 01 00 00 f0 00 01 00]; + qcom,mdss-dsi-off-command = + [05 01 00 00 00 00 02 28 00 + 05 01 00 00 00 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/qcom/display/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi new file mode 100644 index 00000000..28f2c96f --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi @@ -0,0 +1,1463 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-panel-name = + "Sim dual cmd mode DSC 3.75:1 dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,cmd-sync-wait-broadcast; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-hor-line-idle = <0 40 256>, + <40 120 128>, + <120 240 64>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-using-te-pin; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <3840>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <1080>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <4>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@4 { + cell-index = <5>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@5 { + cell-index = <6>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@6 { + cell-index = <7>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@7 { + cell-index = <8>; + qcom,mdss-dsi-panel-framerate = <30>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@8 { + cell-index = <9>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@9 { + cell-index = <10>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@10 { + cell-index = <11>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-on-command = [ + /* CMD2_P0 */ + 15 01 00 00 00 00 02 FF 20 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 01 + 15 01 00 00 00 00 02 01 55 + 15 01 00 00 00 00 02 02 45 + 15 01 00 00 00 00 02 05 40 + 15 01 00 00 00 00 02 06 19 + 15 01 00 00 00 00 02 07 1E + 15 01 00 00 00 00 02 0B 73 + 15 01 00 00 00 00 02 0C 73 + 15 01 00 00 00 00 02 0E B0 + 15 01 00 00 00 00 02 0F AE + 15 01 00 00 00 00 02 11 B8 + 15 01 00 00 00 00 02 13 00 + 15 01 00 00 00 00 02 58 80 + 15 01 00 00 00 00 02 59 01 + 15 01 00 00 00 00 02 5A 00 + 15 01 00 00 00 00 02 5B 01 + 15 01 00 00 00 00 02 5C 80 + 15 01 00 00 00 00 02 5D 81 + 15 01 00 00 00 00 02 5E 00 + 15 01 00 00 00 00 02 5F 01 + 15 01 00 00 00 00 02 72 31 + 15 01 00 00 00 00 02 68 03 + /* CMD2_P4 */ + 15 01 00 00 00 00 02 ff 24 + 15 01 00 00 00 00 02 fb 01 + 15 01 00 00 00 00 02 00 1C + 15 01 00 00 00 00 02 01 0B + 15 01 00 00 00 00 02 02 0C + 15 01 00 00 00 00 02 03 01 + 15 01 00 00 00 00 02 04 0F + 15 01 00 00 00 00 02 05 10 + 15 01 00 00 00 00 02 06 10 + 15 01 00 00 00 00 02 07 10 + 15 01 00 00 00 00 02 08 89 + 15 01 00 00 00 00 02 09 8A + 15 01 00 00 00 00 02 0A 13 + 15 01 00 00 00 00 02 0B 13 + 15 01 00 00 00 00 02 0C 15 + 15 01 00 00 00 00 02 0D 15 + 15 01 00 00 00 00 02 0E 17 + 15 01 00 00 00 00 02 0F 17 + 15 01 00 00 00 00 02 10 1C + 15 01 00 00 00 00 02 11 0B + 15 01 00 00 00 00 02 12 0C + 15 01 00 00 00 00 02 13 01 + 15 01 00 00 00 00 02 14 0F + 15 01 00 00 00 00 02 15 10 + 15 01 00 00 00 00 02 16 10 + 15 01 00 00 00 00 02 17 10 + 15 01 00 00 00 00 02 18 89 + 15 01 00 00 00 00 02 19 8A + 15 01 00 00 00 00 02 1A 13 + 15 01 00 00 00 00 02 1B 13 + 15 01 00 00 00 00 02 1C 15 + 15 01 00 00 00 00 02 1D 15 + 15 01 00 00 00 00 02 1E 17 + 15 01 00 00 00 00 02 1F 17 + /* STV */ + 15 01 00 00 00 00 02 20 40 + 15 01 00 00 00 00 02 21 01 + 15 01 00 00 00 00 02 22 00 + 15 01 00 00 00 00 02 23 40 + 15 01 00 00 00 00 02 24 40 + 15 01 00 00 00 00 02 25 6D + 15 01 00 00 00 00 02 26 40 + 15 01 00 00 00 00 02 27 40 + /* Vend */ + 15 01 00 00 00 00 02 E0 00 + 15 01 00 00 00 00 02 DC 21 + 15 01 00 00 00 00 02 DD 22 + 15 01 00 00 00 00 02 DE 07 + 15 01 00 00 00 00 02 DF 07 + 15 01 00 00 00 00 02 E3 6D + 15 01 00 00 00 00 02 E1 07 + 15 01 00 00 00 00 02 E2 07 + /* UD */ + 15 01 00 00 00 00 02 29 D8 + 15 01 00 00 00 00 02 2A 2A + /* CLK */ + 15 01 00 00 00 00 02 4B 03 + 15 01 00 00 00 00 02 4C 11 + 15 01 00 00 00 00 02 4D 10 + 15 01 00 00 00 00 02 4E 01 + 15 01 00 00 00 00 02 4F 01 + 15 01 00 00 00 00 02 50 10 + 15 01 00 00 00 00 02 51 00 + 15 01 00 00 00 00 02 52 80 + 15 01 00 00 00 00 02 53 00 + 15 01 00 00 00 00 02 56 00 + 15 01 00 00 00 00 02 54 07 + 15 01 00 00 00 00 02 58 07 + 15 01 00 00 00 00 02 55 25 + /* Reset XDONB */ + 15 01 00 00 00 00 02 5B 43 + 15 01 00 00 00 00 02 5C 00 + 15 01 00 00 00 00 02 5F 73 + 15 01 00 00 00 00 02 60 73 + 15 01 00 00 00 00 02 63 22 + 15 01 00 00 00 00 02 64 00 + 15 01 00 00 00 00 02 67 08 + 15 01 00 00 00 00 02 68 04 + /* Resolution:1440x2560*/ + 15 01 00 00 00 00 02 72 02 + /* mux */ + 15 01 00 00 00 00 02 7A 80 + 15 01 00 00 00 00 02 7B 91 + 15 01 00 00 00 00 02 7C D8 + 15 01 00 00 00 00 02 7D 60 + 15 01 00 00 00 00 02 7F 15 + 15 01 00 00 00 00 02 75 15 + /* ABOFF */ + 15 01 00 00 00 00 02 B3 C0 + 15 01 00 00 00 00 02 B4 00 + 15 01 00 00 00 00 02 B5 00 + /* Source EQ */ + 15 01 00 00 00 00 02 78 00 + 15 01 00 00 00 00 02 79 00 + 15 01 00 00 00 00 02 80 00 + 15 01 00 00 00 00 02 83 00 + /* FP BP */ + 15 01 00 00 00 00 02 93 0A + 15 01 00 00 00 00 02 94 0A + /* Inversion Type */ + 15 01 00 00 00 00 02 8A 00 + 15 01 00 00 00 00 02 9B FF + /* IMGSWAP =1 @PortSwap=1 */ + 15 01 00 00 00 00 02 9D B0 + 15 01 00 00 00 00 02 9F 63 + 15 01 00 00 00 00 02 98 10 + /* FRM */ + 15 01 00 00 00 00 02 EC 00 + /* CMD1 */ + 15 01 00 00 00 00 02 ff 10 + /* VBP+VSA=,VFP = 10H */ + 15 01 00 00 00 00 04 3B 03 0A 0A + /* FTE on */ + 15 01 00 00 00 00 02 35 00 + /* EN_BK =1(auto black) */ + 15 01 00 00 00 00 02 E5 01 + /* CMD mode(10) VDO mode(03) */ + 15 01 00 00 00 00 02 BB 10 + /* Non Reload MTP */ + 15 01 00 00 00 00 02 FB 01 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 78 00 + 02 28 00 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@11 { + cell-index = <12>; + qcom,mdss-dsi-panel-width = <2520>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <1080>; + qcom,mdss-dsc-slice-width = <1260>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@12 { + cell-index = <13>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <30>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@13 { + cell-index = <14>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@14 { + cell-index = <15>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@15 { + cell-index = <16>; + qcom,mdss-dsi-panel-width = <360>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <360>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@16 { + cell-index = <17>; + qcom,mdss-dsi-panel-width = <540>; + qcom,mdss-dsi-panel-height = <1920>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <32>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@17 { + cell-index = <18>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <30>; + qcom,mdss-dsi-h-back-porch = <100>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <7>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <1>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 11 91 09 20 00 20 02 + 00 03 1c 04 21 00 + 0f 03 19 01 97 + 39 01 00 00 00 00 03 92 10 f0 + 15 01 00 00 00 00 02 90 03 + 15 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 04 + 15 01 00 00 00 00 02 c0 03 + 39 01 00 00 00 00 06 f0 55 aa 52 08 07 + 15 01 00 00 00 00 02 ef 01 + 39 01 00 00 00 00 06 f0 55 aa 52 08 00 + 15 01 00 00 00 00 02 b4 01 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 06 f0 55 aa 52 08 01 + 39 01 00 00 00 00 05 ff aa 55 a5 80 + 15 01 00 00 00 00 02 6f 01 + 15 01 00 00 00 00 02 f3 10 + 39 01 00 00 00 00 05 ff aa 55 a5 00 + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <16>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <10>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-dualmipi-video.dtsi b/qcom/display/display/dsi-panel-sim-dualmipi-video.dtsi new file mode 100644 index 00000000..e977a78b --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-dualmipi-video.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video { + qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-panel-broadcast-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>; + qcom,panel-ack-disabled; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <45>; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <1280>; + qcom,mdss-dsi-panel-height = <1440>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <44>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <4>; + qcom,mdss-dsi-v-front-porch = <8>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command = + [05 01 00 00 32 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = + [15 01 00 00 00 00 02 51 00]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-sec-hd-cmd.dtsi b/qcom/display/display/dsi-panel-sim-sec-hd-cmd.dtsi new file mode 100644 index 00000000..3172af60 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-sec-hd-cmd.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-panel-name = + "sim hd command mode secondary dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,panel-ack-disabled; + qcom,mdss-dsi-te-using-wd; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-width = <720>; + qcom,mdss-dsi-panel-height = <1280>; + qcom,mdss-dsi-h-front-porch = <120>; + qcom,mdss-dsi-h-back-porch = <60>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 f0 00 01 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 78 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-sim-video.dtsi b/qcom/display/display/dsi-panel-sim-video.dtsi new file mode 100644 index 00000000..02fd6ca9 --- /dev/null +++ b/qcom/display/display/dsi-panel-sim-video.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_sim_vid: qcom,mdss_dsi_sim_video { + qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-t-clk-post = <0x04>; + qcom,mdss-dsi-t-clk-pre = <0x1b>; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>; + qcom,panel-ack-disabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <2560>; + qcom,mdss-dsi-h-front-porch = <8>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <6>; + qcom,mdss-dsi-v-front-porch = <6>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-on-command = + [32 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-off-command = + [22 01 00 00 00 00 02 00 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; + + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi new file mode 100644 index 00000000..30dfc315 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode 120hz dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <683100000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi new file mode 100644 index 00000000..bd6bbec8 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode 120hz dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi new file mode 100644 index 00000000..17c9b05f --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <353116800>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi new file mode 100644 index 00000000..806b30eb --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_60hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_60hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi new file mode 100644 index 00000000..d465d706 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <529675200>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi new file mode 100644 index 00000000..286080d3 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 00 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 03 EB 00 00 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi new file mode 100644 index 00000000..45850567 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi @@ -0,0 +1,557 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-panel-mode-switch; + + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-cmd-mode; + qcom,mdss-dsi-video-mode; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <10>; + qcom,mdss-dsi-h-back-porch = <16>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <18>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + ]; + + qcom,cmd-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,vid-on-commands = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + + qcom,cmd-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 07 + ]; + qcom,cmd-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-in-commands = [ + 39 01 00 00 00 00 02 6f 01 + ]; + qcom,video-mode-switch-in-commands-state = + "dsi_lp_mode"; + + qcom,video-mode-switch-out-commands = [ + 39 01 00 00 00 00 02 6f 03 + 39 01 00 00 00 00 02 6f 02 + ]; + qcom,video-mode-switch-out-commands-state = + "dsi_lp_mode"; + + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1 { + cell-index = <1>; + qcom,mdss-dsi-panel-framerate = <120>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 0a e1 0a e1 0a + 81 09 92 06 c5 00 48 00 3e 00 2b 00 + 0c 00 0c 05 00 3f + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2 { + cell-index = <2>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 0e 81 0e 81 0e + 01 0c c3 09 06 00 60 00 53 00 3a 00 + 0c 00 0c 07 00 54 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3 { + cell-index = <3>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <813936000>; + + qcom,mdss-dsi-timing-switch-command = [ + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + ]; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 02 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 01 fc 00 01 66 00 + 14 0d 6c 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 d3 15 c2 15 c2 15 + 02 13 25 0d 8a 00 90 00 7d 00 57 00 + 0c 00 0c 0b 00 7e + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi new file mode 100644 index 00000000..4c4886f9 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_video: qcom,mdss_dsi_vtdr6130_fhd_plus_vid { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-sec-ctrl-num = <1>; + qcom,dsi-sec-phy-num = <1>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,spr-pack-type = "pentile"; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6C 01 + 39 01 00 00 00 00 02 6D 00 + 39 01 00 00 00 00 02 6F 01 + 39 01 00 00 00 00 5F 70 12 00 00 AB 30 + 80 09 60 04 38 00 28 02 1C 02 1C 02 + 00 02 0E 00 20 03 DD 00 07 00 0C 02 + 77 02 8B 18 00 10 F0 07 10 20 00 06 + 0F 0F 33 0E 1C 2A 38 46 54 62 69 70 + 77 79 7B 7D 7E 02 02 22 00 2A 40 2A + BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B + B6 4B B6 4B F4 4B F4 6C 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 F0 AA 10 + 39 01 00 00 00 00 16 B1 01 38 00 14 00 + 1C 00 01 66 00 14 00 14 00 01 66 00 + 14 05 CC 00 + 39 01 00 00 00 00 03 F0 AA 13 + 39 01 00 00 00 00 18 CE 09 11 09 11 08 + C1 07 FA 05 A4 00 3C 00 34 00 24 00 + 0C 00 0C 04 00 35 + 39 01 00 00 00 00 03 F0 AA 14 + 39 01 00 00 00 00 03 B2 03 33 + 39 01 00 00 00 00 0D B4 00 33 00 00 00 + 3E 00 00 00 3E 00 00 + 39 01 00 00 00 00 0A B5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 B9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0D BC 10 00 00 06 11 + 09 3B 09 47 09 47 00 + 39 01 00 00 00 00 0D BE 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 FA 08 08 08 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F3 0F + 39 01 00 00 00 00 03 F0 AA 00 + 39 01 00 00 00 00 03 FF 5A 82 + 39 01 00 00 00 00 02 F9 00 + 39 01 00 00 00 00 03 FF 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 F8 00 + 39 01 00 00 00 00 03 FF 5A 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 F4 9A + 39 01 00 00 00 00 03 FF 5A 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi b/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi new file mode 100644 index 00000000..5143cf11 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_qsync_144hz_cmd: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_cmd { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled qsync cmd mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <95>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 02 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-qsync-on-commands = [ + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 3c 00 3c 00 + 0c 00 0c 04 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 0c bb 00 4c 00 01 00 + 01 32 01 6e 01 6e + 39 01 00 00 00 00 02 bb 01 + ]; + qcom,mdss-dsi-qsync-on-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-qsync-off-commands = [ + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 02 bb 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + ]; + qcom,mdss-dsi-qsync-off-commands-state = + "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi b/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi new file mode 100644 index 00000000..baa8e311 --- /dev/null +++ b/qcom/display/display/dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + dsi_vtdr6130_amoled_qsync_144hz_video: qcom,mdss_dsi_vtdr6130_qsync_fhd_plus_144hz_video { + qcom,mdss-dsi-panel-name = + "vtdr6130 amoled qsync video mode dsi visionox panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-panel-physical-type = "oled"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>; + + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; + + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,qsync-enable; + qcom,mdss-dsi-qsync-min-refresh-rate = <80>; + qcom,mdss-dsi-display-timings { + timing@0 { + cell-index = <0>; + qcom,mdss-dsi-panel-framerate = <144>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2400>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <2>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <20>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 51 00 00 + 39 01 00 00 00 00 02 59 09 + 39 01 00 00 00 00 02 6c 01 + 39 01 00 00 00 00 02 6d 00 + 39 01 00 00 00 00 02 6f 01 + 39 01 00 00 00 00 5f 70 12 00 00 ab 30 + 80 09 60 04 38 00 28 02 1c 02 1c 02 + 00 02 0e 00 20 03 dd 00 07 00 0c 02 + 77 02 8b 18 00 10 f0 07 10 20 00 06 + 0f 0f 33 0e 1c 2a 38 46 54 62 69 70 + 77 79 7b 7d 7e 02 02 22 00 2a 40 2a + be 3a fc 3a fa 3a f8 3b 38 3b 78 3b + b6 4b b6 4b f4 4b f4 6c 34 84 74 00 + 00 00 00 00 00 + 39 01 00 00 00 00 03 f0 aa 10 + 39 01 00 00 00 00 16 b1 01 38 00 14 00 + 1c 00 01 66 00 14 00 14 00 01 66 00 + 14 05 cc 00 + 39 01 00 00 00 00 03 f0 aa 13 + 39 01 00 00 00 00 18 ce 09 11 09 11 08 + c1 07 fa 05 a4 00 3c 00 34 00 24 00 + 0c 00 0c 04 00 35 + 39 01 00 00 00 00 03 f0 aa 14 + 39 01 00 00 00 00 03 b2 03 33 + 39 01 00 00 00 00 0d b4 00 33 00 00 00 + 3e 00 00 00 3e 00 00 + 39 01 00 00 00 00 0a b5 00 09 09 09 09 + 09 09 06 01 + 39 01 00 00 00 00 07 b9 00 00 08 09 09 + 09 + 39 01 00 00 00 00 0d bc 10 00 00 06 11 + 09 3b 09 47 09 47 00 + 39 01 00 00 00 00 0d be 10 10 00 08 22 + 09 19 09 25 09 25 00 + 39 01 00 00 00 00 03 ff 5a 80 + 39 01 00 00 00 00 02 65 14 + 39 01 00 00 00 00 04 fa 08 08 08 + 39 01 00 00 00 00 03 ff 5a 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 f3 0f + 39 01 00 00 00 00 03 f0 aa 00 + 39 01 00 00 00 00 03 ff 5a 82 + 39 01 00 00 00 00 02 f9 00 + 39 01 00 00 00 00 03 ff 51 83 + 39 01 00 00 00 00 02 65 04 + 39 01 00 00 00 00 02 f8 00 + 39 01 00 00 00 00 03 ff 5a 00 + 39 01 00 00 00 00 02 65 01 + 39 01 00 00 00 00 02 f4 9a + 39 01 00 00 00 00 03 ff 5a 00 + 05 01 00 00 78 00 01 11 + 05 01 00 00 14 00 01 29 + ]; + + qcom,mdss-dsi-off-command = [ + 05 01 00 00 14 00 02 28 00 + 05 01 00 00 78 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <40>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/display/display/kera-sde-common.dtsi b/qcom/display/display/kera-sde-common.dtsi new file mode 100644 index 00000000..94e9cdb8 --- /dev/null +++ b/qcom/display/display/kera-sde-common.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>, + <0x0af50000 0x140>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg", + "swfuse_phys"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-hyp-off = <0x15000>; + qcom,sde-ctl-hyp-size = <0xc00>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <6>; + qcom,sde-wb-id = <2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <5 6 1 2 3 4>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <4300000 4300000 + 4300000 4300000 + 4300000 4300000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x2>, + <0x7 0x1>; + qcom,sde-ubwc-version = <0x40000000>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <6800000>; + qcom,sde-max-bw-high-kbps = <14200000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <1600000>; + qcom,sde-dram-channels = <2>; + qcom,sde-num-nrt-paths = <0>; + qcom,sde-num-ddr-channels = <2>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x7>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/qcom/display/display/kera-sde-display-atp-overlay.dts b/qcom/display/display/kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..055789c5 --- /dev/null +++ b/qcom/display/display/kera-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/display/display/kera-sde-display-cdp-overlay.dts b/qcom/display/display/kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..52f5b3d9 --- /dev/null +++ b/qcom/display/display/kera-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/qcom/display/display/kera-sde-display-cdp.dtsi b/qcom/display/display/kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..faa2551e --- /dev/null +++ b/qcom/display/display/kera-sde-display-cdp.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&pmxr2230_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio2"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550vs_g_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio5"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550vs_g_gpios 5 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-bklight-en-gpio = <&pmxr2230_gpios 2 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + avdd-supply = <&display_panel_avdd>; + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/kera-sde-display-common.dtsi b/qcom/display/display/kera-sde-display-common.dtsi new file mode 100644 index 00000000..bd95e2e8 --- /dev/null +++ b/qcom/display/display/kera-sde-display-common.dtsi @@ -0,0 +1,1005 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" + +#include "kera-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3544000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <1>; + qcom,supply-post-off-sleep = <2>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1250000>; + qcom,supply-enable-load = <200000>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <0>; + qcom,supply-post-off-sleep = <2>; + }; + }; + + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 17 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 121 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ + +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/qcom/display/display/kera-sde-display-mtp-overlay.dts b/qcom/display/display/kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..1eb193fa --- /dev/null +++ b/qcom/display/display/kera-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/qcom/display/display/kera-sde-display-mtp.dtsi b/qcom/display/display/kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..efb7d0d3 --- /dev/null +++ b/qcom/display/display/kera-sde-display-mtp.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/kera-sde-display-pinctrl.dtsi b/qcom/display/display/kera-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..0a7180d8 --- /dev/null +++ b/qcom/display/display/kera-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio17"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio121"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio121"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/qcom/display/display/kera-sde-display-qrd-overlay.dts b/qcom/display/display/kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..04a7ea38 --- /dev/null +++ b/qcom/display/display/kera-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/qcom/display/display/kera-sde-display-qrd.dtsi b/qcom/display/display/kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..4d959c52 --- /dev/null +++ b/qcom/display/display/kera-sde-display-qrd.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dp { + qcom,dp-aux-switch = <&fsa4480>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/kera-sde-display-rcm-overlay.dts b/qcom/display/display/kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..24277d00 --- /dev/null +++ b/qcom/display/display/kera-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/qcom/display/display/kera-sde-display-rumi-overlay.dts b/qcom/display/display/kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..8c8643b2 --- /dev/null +++ b/qcom/display/display/kera-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/display/display/kera-sde-display-rumi.dtsi b/qcom/display/display/kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..177e852b --- /dev/null +++ b/qcom/display/display/kera-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/qcom/display/display/kera-sde-display.dtsi b/qcom/display/display/kera-sde-display.dtsi new file mode 100644 index 00000000..5bf58b4f --- /dev/null +++ b/qcom/display/display/kera-sde-display.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "kera-sde-display-common.dtsi" + +&soc { + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L1G>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb2 &sde_dp + &sde_cesta>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/qcom/display/display/kera-sde.dts b/qcom/display/display/kera-sde.dts new file mode 100644 index 00000000..f6c6ae21 --- /dev/null +++ b/qcom/display/display/kera-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "kera-sde.dtsi" + +/ { + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/display/display/kera-sde.dtsi b/qcom/display/display/kera-sde.dtsi new file mode 100644 index 00000000..e08b2156 --- /dev/null +++ b/qcom/display/display/kera-sde.dtsi @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "kera-sde-common.dtsi" +#include +#include + +&soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "ok"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L7K>; + vdda_usb-0p9-supply = <&L7K>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1320000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", + "disp_cc"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; + + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; + + qcom,hw-fence-sw-version = <0x1>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 1600000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; diff --git a/qcom/display/display/sun-sde-common.dtsi b/qcom/display/display/sun-sde-common.dtsi new file mode 100644 index 00000000..0b0c405c --- /dev/null +++ b/qcom/display/display/sun-sde-common.dtsi @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>, + <0x0af50000 0x128>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg", + "swfuse_phys"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 + 0x19000 0x1a000 0x1b000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", + "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x49000 0x4a000 + 0x4b000 0x4c000 0x0f0f + 0x0f0f 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none", + "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800 0x12800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000 0x3000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x65000 0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0xa 6>; + qcom,sde-wb-id = <1 2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x6e000 0x6f000 0x70000 0x71000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3 0x4 0x4 0x5 0x5>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000 0x52000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000 0x83000 0x83000 0x84000 0x84000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 4 3 6 5 8 7>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200 0x100 0x200 0x100 0x200>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80 0xF00 0xF80 0xF00 0xF80>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1 1 1 1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 + 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", "vig", "vig", + "dma", "dma", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000 + 0x25000 0x27000 0x29000 0x2b000 0x2d000 0x2f000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 8 12 1 5 9 13 14 15>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <7 8 9 10 1 2 3 4 5 6>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7 10 9 12 11>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 + 4500000 4500000 + 4500000 4500000 + 4500000 4500000 + 4500000 4500000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5700000 5700000 + 5700000 5700000 + 5700000 5700000 + 5700000 5700000 + 5700000 5700000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, <0x8330 0>, <0xa330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>, + <0x2c330 0>, <0x2e330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, <0x8334 0>, <0xa334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>, + <0x2c334 0>, <0x2e334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x3>, + <0x7 0x2>; + qcom,sde-ubwc-version = <0x50000001>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <18900000>; + qcom,sde-max-bw-high-kbps = <28500000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <4>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400 0x12400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600 0x12600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-dspp-aiqe-off = <0x39000 0xffffffff 0x3a000 0xffffffff>; + qcom,sde-dspp-aiqe-version = <0x00010000>; + qcom,sde-dspp-aiqe-size = <0x3fc>; + + qcom,sde-dspp-aiqe-dither-off = <0x39700 0xffffffff 0x3a700 0xffffffff>; + qcom,sde-dspp-aiqe-dither-version = <0x00010000>; + qcom,sde-dspp-aiqe-dither-size = <0x20>; + + qcom,sde-dspp-aiqe-wrapper-off = <0x39780 0xffffffff 0x3a780 0xffffffff>; + qcom,sde-dspp-aiqe-wrapper-version = <0x00010000>; + qcom,sde-dspp-aiqe-wrapper-size = <0x1c>; + + qcom,sde-dspp-aiqe-aiscaler-off = <0x30000 0xffffffff>; + qcom,sde-dspp-aiqe-aiscaler-version = <0x00010000>; + qcom,sde-dspp-aiqe-aiscaler-size = <0x7d0>; + + qcom,sde-aiqe-has-feature-mdnie; + qcom,sde-aiqe-has-feature-abc; + qcom,sde-aiqe-has-feature-ssrc; + qcom,sde-aiqe-has-feature-copr; + qcom,sde-aiqe-has-feature-aiscaler; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x0002801 0x0002c01>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v7.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_3nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v7.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_3nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/qcom/display/display/sun-sde-display-atp-overlay.dts b/qcom/display/display/sun-sde-display-atp-overlay.dts new file mode 100644 index 00000000..374a8b41 --- /dev/null +++ b/qcom/display/display/sun-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun ATP"; + compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp", "qcom,atp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x10021 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-kiwi-overlay.dts b/qcom/display/display/sun-sde-display-cdp-kiwi-overlay.dts new file mode 100644 index 00000000..0cb09597 --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x20001 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-kiwi-v8-overlay.dts b/qcom/display/display/sun-sde-display-cdp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..d65e13c6 --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-kiwi-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x60001 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-nfc-overlay.dts b/qcom/display/display/sun-sde-display-cdp-nfc-overlay.dts new file mode 100644 index 00000000..2dc93aca --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-nfc-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP SN300 NFC"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x40001 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-no-display-overlay.dts b/qcom/display/display/sun-sde-display-cdp-no-display-overlay.dts new file mode 100644 index 00000000..59087574 --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-no-display-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp-no-display.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP No Display"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x30001 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-no-display.dtsi b/qcom/display/display/sun-sde-display-cdp-no-display.dtsi new file mode 100644 index 00000000..c9bc5c6d --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-no-display.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_sim_vid>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-overlay.dts b/qcom/display/display/sun-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..790386a1 --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp-v8-overlay.dts b/qcom/display/display/sun-sde-display-cdp-v8-overlay.dts new file mode 100644 index 00000000..36812b46 --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP V8 Power Grid"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", + "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x50001 0>; +}; diff --git a/qcom/display/display/sun-sde-display-cdp.dtsi b/qcom/display/display/sun-sde-display-cdp.dtsi new file mode 100644 index 00000000..9ec15fff --- /dev/null +++ b/qcom/display/display/sun-sde-display-cdp.dtsi @@ -0,0 +1,341 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + avdd-supply = <&display_panel_avdd>; + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; + }; +}; + +&qupv3_se15_i2c { + status = "disabled"; + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr + &dsi_sharp_qhd_plus_dsc_cmd + &dsi_sharp_qhd_plus_dsc_video>; + }; +}; diff --git a/qcom/display/display/sun-sde-display-common.dtsi b/qcom/display/display/sun-sde-display-common.dtsi new file mode 100644 index 00000000..fffb51e2 --- /dev/null +++ b/qcom/display/display/sun-sde-display-common.dtsi @@ -0,0 +1,1348 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +#include "sun-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <154000>; + qcom,supply-disable-load = <45000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1000000>; + qcom,supply-max-voltage = <1100000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <471>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3000000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@3 { + reg = <3>; + qcom,supply-name = "tvdd"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &sde_esync0_suspend>; + pinctrl-1 = <&sde_dsi_active &sde_te_active &sde_esync0_active>; + pinctrl-2 = <&sde_dsi_suspend &sde_te_suspend &sde_esync0_suspend>; + + qcom,platform-te-gpio = <&tlmm 86 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_active_with_esync", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active &sde_esync1_suspend>; + pinctrl-1 = <&sde_dsi1_active &sde_te1_active &sde_esync1_active>; + pinctrl-2 = <&sde_dsi1_suspend &sde_te1_suspend &sde_esync1_suspend>; + + qcom,platform-te-gpio = <&tlmm 87 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YL with reduced margins */ +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_sim_panel_au { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 1a 0c 00]; + qcom,display-topology = <1 0 1>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>, + <4 3 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>, + <4 3 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x07>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x1c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <4 4 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,poms-align-panel-vsync; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a + 0b 0a 02 04 00 21 10]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b + 1d 18 02 04 00 51 21]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 89 26 27 42 39 25 + 27 1f 02 04 00 69 2a]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12 + 14 11 02 04 00 39 18]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 17 14 0e + 0e 0d 02 04 00 2b 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e + 0f 0d 02 04 00 2d 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/qcom/display/display/sun-sde-display-emulated.dtsi b/qcom/display/display/sun-sde-display-emulated.dtsi new file mode 100644 index 00000000..28b440bf --- /dev/null +++ b/qcom/display/display/sun-sde-display-emulated.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/qcom/display/display/sun-sde-display-hdk-overlay.dts b/qcom/display/display/sun-sde-display-hdk-overlay.dts new file mode 100644 index 00000000..85200310 --- /dev/null +++ b/qcom/display/display/sun-sde-display-hdk-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-hdk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SunP QRD HDK"; + compatible = "qcom,sunp-hdk", "qcom,sunp", "qcom,hdk"; + qcom,msm-id = <639 0x10000>, <639 0x20000>, <618 0x10000>, <618 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x1001f 0>; +}; diff --git a/qcom/display/display/sun-sde-display-hdk.dtsi b/qcom/display/display/sun-sde-display-hdk.dtsi new file mode 100644 index 00000000..fd5bca06 --- /dev/null +++ b/qcom/display/display/sun-sde-display-hdk.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&tlmm { + lt9611_pins: lt9611_pins { + mux { + pins = "gpio69", "gpio60", "gpio214", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio60", "gpio214", "gpio83"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; +}; + +&qupv3_se5_i2c { + status = "ok"; + + lt9611: lt,lt9611@2b { + compatible = "lt,lt9611uxc"; + reg = <0x2b>; + interrupt-parent = <&tlmm>; + interrupts = <44 0>; + interrupt-names = "lt_irq"; + lt,irq-gpio = <&tlmm 69 0x0>; + lt,reset-gpio = <&tlmm 60 0x0>; + lt,hdmi-3p3-en = <&tlmm 214 0x0>; + lt,hdmi-1p2-en = <&tlmm 83 0x0>; + lt,non-pluggable; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_pins>; + + lt,preferred-mode = "1920x1080"; + + lt,customize-modes { + lt,customize-mode-id@0 { + lt,mode-h-active = <1920>; + lt,mode-h-front-porch = <88>; + lt,mode-h-pulse-width = <44>; + lt,mode-h-back-porch = <148>; + lt,mode-h-active-high; + lt,mode-v-active = <1080>; + lt,mode-v-front-porch = <4>; + lt,mode-v-pulse-width = <5>; + lt,mode-v-back-porch = <36>; + lt,mode-v-active-high; + lt,mode-clock-in-khz = <148500>; + }; + + lt,customize-mode-id@1 { + lt,mode-h-active = <3840>; + lt,mode-h-front-porch = <176>; + lt,mode-h-pulse-width = <88>; + lt,mode-h-back-porch = <400>; + lt,mode-h-active-high; + lt,mode-v-active = <2160>; + lt,mode-v-front-porch = <8>; + lt,mode-v-pulse-width = <10>; + lt,mode-v-back-porch = <72>; + lt,mode-v-active-high; + lt,mode-clock-in-khz = <608040>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lt9611_in_0: endpoint { + remote-endpoint = <&ext_dsi_0_out>; + }; + }; + }; + }; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ext_dsi_0_out: endpoint { + remote-endpoint = <<9611_in_0>; + }; + }; + }; +}; + +&battery_charger { + qcom,display-panels = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_ext_bridge_1080p>; +}; + +&qupv3_se4_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_ext_bridge_1080p>; + }; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-3-5mm-overlay.dts b/qcom/display/display/sun-sde-display-mtp-3-5mm-overlay.dts new file mode 100644 index 00000000..8b6c2343 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-3-5mm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP with 3.5mm"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x60008 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-kiwi-overlay.dts b/qcom/display/display/sun-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..3d8cdcab --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-kiwi-v8-overlay.dts b/qcom/display/display/sun-sde-display-mtp-kiwi-v8-overlay.dts new file mode 100644 index 00000000..102879d4 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-kiwi-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x50008 0>, <0x60108 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-nfc-overlay.dts b/qcom/display/display/sun-sde-display-mtp-nfc-overlay.dts new file mode 100644 index 00000000..8792479e --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-nfc-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP SN300 NFC"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x30008 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-overlay.dts b/qcom/display/display/sun-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..ea229825 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <8 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-qmp1000-overlay.dts b/qcom/display/display/sun-sde-display-mtp-qmp1000-overlay.dts new file mode 100644 index 00000000..da5a314a --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-qmp1000-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x108 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts b/qcom/display/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts new file mode 100644 index 00000000..52432f90 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-qmp1000-v8-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP QMP1000 V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x40108 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp-v8-overlay.dts b/qcom/display/display/sun-sde-display-mtp-v8-overlay.dts new file mode 100644 index 00000000..6efc5290 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP V8 Power Grid"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", + "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x40008 0>; +}; diff --git a/qcom/display/display/sun-sde-display-mtp.dtsi b/qcom/display/display/sun-sde-display-mtp.dtsi new file mode 100644 index 00000000..b62cf120 --- /dev/null +++ b/qcom/display/display/sun-sde-display-mtp.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; + +&battery_charger { + qcom,display-panels = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; +}; diff --git a/qcom/display/display/sun-sde-display-pinctrl.dtsi b/qcom/display/display/sun-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..8b9d0ff8 --- /dev/null +++ b/qcom/display/display/sun-sde-display-pinctrl.dtsi @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio98"; + function = "gpio"; + }; + + config { + pins = "gpio98"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio97"; + function = "gpio"; + }; + + config { + pins = "gpio97"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio86"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio86"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio87"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio87"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio87"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_esync: pmx_sde_esync { + sde_esync0_active: sde_esync0_active { + mux { + pins = "gpio88"; + function = "mdp_esync0_out"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync0_suspend: sde_esync0_suspend { + mux { + pins = "gpio88"; + function = "mdp_esync0_out"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync1_active: sde_esync1_active { + mux { + pins = "gpio100"; + function = "mdp_esync1_out"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_esync1_suspend: sde_esync1_suspend { + mux { + pins = "gpio100"; + function = "mdp_esync1_out"; + }; + + config { + pins = "gpio100"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/qcom/display/display/sun-sde-display-qrd-sku1-overlay.dts b/qcom/display/display/sun-sde-display-qrd-sku1-overlay.dts new file mode 100644 index 00000000..c82f0229 --- /dev/null +++ b/qcom/display/display/sun-sde-display-qrd-sku1-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/display/display/sun-sde-display-qrd-sku1-v8-overlay.dts b/qcom/display/display/sun-sde-display-qrd-sku1-v8-overlay.dts new file mode 100644 index 00000000..5b98bf36 --- /dev/null +++ b/qcom/display/display/sun-sde-display-qrd-sku1-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x3000B 0>; +}; diff --git a/qcom/display/display/sun-sde-display-qrd-sku2-v8-overlay.dts b/qcom/display/display/sun-sde-display-qrd-sku2-v8-overlay.dts new file mode 100644 index 00000000..e38db838 --- /dev/null +++ b/qcom/display/display/sun-sde-display-qrd-sku2-v8-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x2000B 0>; +}; diff --git a/qcom/display/display/sun-sde-display-qrd.dtsi b/qcom/display/display/sun-sde-display-qrd.dtsi new file mode 100644 index 00000000..2e91032c --- /dev/null +++ b/qcom/display/display/sun-sde-display-qrd.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; + }; +}; + +&battery_charger { + qcom,display-panels = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; +}; diff --git a/qcom/display/display/sun-sde-display-rcm-kiwi-overlay.dts b/qcom/display/display/sun-sde-display-rcm-kiwi-overlay.dts new file mode 100644 index 00000000..28228c2e --- /dev/null +++ b/qcom/display/display/sun-sde-display-rcm-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x40015 0>; +}; diff --git a/qcom/display/display/sun-sde-display-rcm-kiwi-v8-overlay.dts b/qcom/display/display/sun-sde-display-rcm-kiwi-v8-overlay.dts new file mode 100644 index 00000000..3e7c2ff6 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rcm-kiwi-v8-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM Kiwi WLAN V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x20015 0>; +}; diff --git a/qcom/display/display/sun-sde-display-rcm-overlay.dts b/qcom/display/display/sun-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..c0c75af3 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x15 0>; +}; diff --git a/qcom/display/display/sun-sde-display-rcm-v8-overlay.dts b/qcom/display/display/sun-sde-display-rcm-v8-overlay.dts new file mode 100644 index 00000000..86e99543 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rcm-v8-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rcm.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RCM V8 Power Grid"; + compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp-rcm", "qcom,sunp", "qcom,rcm"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <0x30015 0>; +}; diff --git a/qcom/display/display/sun-sde-display-rcm.dtsi b/qcom/display/display/sun-sde-display-rcm.dtsi new file mode 100644 index 00000000..4566cd46 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rcm.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display-cdp.dtsi" diff --git a/qcom/display/display/sun-sde-display-rumi-overlay.dts b/qcom/display/display/sun-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..ce4c64c0 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun RUMI"; + compatible = "qcom,sun-rumi", "qcom,sun", "qcom,rumi"; + qcom,msm-id = <618 0x10000>; + qcom,board-id = <15 0>; +}; + diff --git a/qcom/display/display/sun-sde-display-rumi.dtsi b/qcom/display/display/sun-sde-display-rumi.dtsi new file mode 100644 index 00000000..b5cf1f78 --- /dev/null +++ b/qcom/display/display/sun-sde-display-rumi.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display.dtsi" +#include "sun-sde-display-emulated.dtsi" + diff --git a/qcom/display/display/sun-sde-display.dtsi b/qcom/display/display/sun-sde-display.dtsi new file mode 100644 index 00000000..a1a671ef --- /dev/null +++ b/qcom/display/display/sun-sde-display.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde.dtsi" +#include "sun-sde-display-common.dtsi" +#include + +&pm8550_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio11"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + sde_wb1: qcom,wb-display@1 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display1"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <1>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550_gpios 11 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + }; + + disp_rdump_memory: disp_rdump_region@0xd5500000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xfc800000 0x0 0x02b00000>; + label = "cont_splash_region"; + }; + /* + * Demura memory regions are to be commented out if + * feature not in use. + */ + demura_memory_0: demura_region_0 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 0"; + }; + + demura_memory_1: demura_region_1 { + reg = <0x0 0x0 0x0 0x0>; + label = "demura hfc region 1"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC0_CLK_SRC>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk", "esync_clk_rcg"; + vddio-supply = <&L12B>; + vci-supply = <&L13B>; + vdd-supply = <&L11B>; + tvdd-supply = <&L4B>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>, + /* + * The esync clk RCG is only necessary here to set its parent + * to the pll dsi clk, which also needs to be available at the + * point that its known whether the clock will be used. After + * updating the parent, this clock handle is no longer needed. + */ + <&dispcc DISP_CC_ESYNC1_CLK_SRC>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk", "esync_clk_rcg"; + vddio-supply = <&L12B>; + vci-supply = <&L13B>; + vdd-supply = <&L11B>; + tvdd-supply = <&L4B>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_dp &sde_cesta>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/qcom/display/display/sun-sde.dts b/qcom/display/display/sun-sde.dts new file mode 100644 index 00000000..36b0c926 --- /dev/null +++ b/qcom/display/display/sun-sde.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "sun-sde.dtsi" + +/ { + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>, + <0x100026a 0x10000>, <0x100026a 0x20000>, + <0x100027f 0x10000>, <0x100027f 0x20000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/display/display/sun-sde.dtsi b/qcom/display/display/sun-sde.dtsi new file mode 100644 index 00000000..ebb9dbbd --- /dev/null +++ b/qcom/display/display/sun-sde.dtsi @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "sun-sde-common.dtsi" + +&soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88eb000 { + compatible = "qcom,dp-pll-3nm-v1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88ebc00 0x200>, + <0x88eb400 0x200>, + <0x88eb800 0x200>, + <0x88eb000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x800>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,4ppc-enable; + qcom,mst-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L3G>; + vdda-0p9-supply = <&L2D>; + vdda_usb-0p9-supply = <&L2D>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x27 0x2f 0x36 0x3f>, + <0x31 0x3e 0x3f 0xff>, + <0x36 0x3f 0xff 0xff>, + <0x3f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x20 0x2d 0x34 0x3a>, + <0x20 0x2e 0x35 0xff>, + <0x20 0x2e 0xff 0xff>, + <0x22 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x22 0x32 0x36 0x3a>, + <0x29 0x39 0x3f 0xff>, + <0x30 0x3f 0xff 0xff>, + <0x3f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x20 0x2c 0x35 0x3b>, + <0x22 0x2e 0x36 0xff>, + <0x22 0x31 0xff 0xff>, + <0x24 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <912000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <880000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xd4e23000 0x002dd000>, + <&smmu_sde_unsec 0xd2880000 0x05780000>, + <&smmu_sde_unsec 0xa3500000 0x02c80000>, + <&smmu_sde_unsec 0xfc800000 0x02b00000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", "disp_cc"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; + + clock-names = "branch_clk", "core_clk","xo"; + clock-rate = <575000000 575000000 19200000>; + clock-max-rate = <575000000 575000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 575000000>; + clock-max-rate = <0 0 19200000 575000000>; + + qcom,hw-fence-sw-version = <0x1>; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-soccp-controller = <&soccp_pas>; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300 0x12300>; + + nvmem-cells = <&ssip_config>; + nvmem-cell-names = "ssip_config"; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L3G>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_ESYNC0_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L3G>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_ESYNC1_CLK>, + <&dispcc DISP_CC_OSC_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esync_clk", "osc_clk", + "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L3I>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; + +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L3I>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-atp-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-atp-overlay.dts new file mode 100644 index 00000000..362e7d57 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM ATP"; + compatible = "qcom,kera-atp", "qcom,kera", "qcom,kerap-atp", "qcom,kerap", + "qcom,atp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-cdp-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..07e44da0 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM CDP"; + compatible = "qcom,kera-cdp", "qcom,kera", "qcom,kerap-cdp", "qcom,kerap", + "qcom,cdp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10001 0>, <0x20001 0>, <0x30001 0>, <0x40001 0>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-cdp.dtsi b/qcom/display/display/trustedvm-kera-sde-display-cdp.dtsi new file mode 100644 index 00000000..fc746e20 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-cdp.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@3 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@2 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + + timing@1 { + /delete-property/ qcom,mdss-dsi-panel-clockrate; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-mtp-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..073f3342 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-mtp-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM MTP"; + compatible = "qcom,kera-mtp", "qcom,kera", "qcom,kerap-mtp", "qcom,kerap", + "qcom,mtp"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10008 0>, <0x10008 1>, <0x20008 0>, <0x20008 1>, <0x30008 0>, + <0x30008 1>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-mtp.dtsi b/qcom/display/display/trustedvm-kera-sde-display-mtp.dtsi new file mode 100644 index 00000000..c42cf3a7 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-mtp.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-qrd-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..e2f6b39c --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM QRD"; + compatible = "qcom,kera-qrd", "qcom,kera", "qcom,kerap-qrd", "qcom,kerap", + "qcom,qrd"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-qrd.dtsi b/qcom/display/display/trustedvm-kera-sde-display-qrd.dtsi new file mode 100644 index 00000000..c42cf3a7 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-qrd.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 12 0>; + qcom,platform-sec-reset-gpio = <&tlmm 127 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>; +}; + +&qupv3_se8_spi { + goodix-berlin@0 { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_qsync_144hz_cmd + &dsi_vtdr6130_amoled_qsync_144hz_video>; + }; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-rcm-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..20c01be8 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-rcm-overlay.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RCM"; + compatible = "qcom,kera-rcm", "qcom,kera", "qcom,kerap-rcm", "qcom,kerap", + "qcom,rcm"; + qcom,msm-id = <686 0x10000>, <659 0x10000>; + qcom,board-id = <0x10015 0>, <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, + <0x30015 1>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-rumi-overlay.dts b/qcom/display/display/trustedvm-kera-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..0374cc20 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-kera-sde.dtsi" +#include "trustedvm-kera-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kera SVM RUMI"; + compatible = "qcom,kera-rumi", "qcom,kera", "qcom,rumi"; + qcom,msm-id = <659 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display-rumi.dtsi b/qcom/display/display/trustedvm-kera-sde-display-rumi.dtsi new file mode 100644 index 00000000..6bf94fae --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-kera-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/qcom/display/display/trustedvm-kera-sde-display.dtsi b/qcom/display/display/trustedvm-kera-sde-display.dtsi new file mode 100644 index 00000000..8ec7d0f1 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "kera-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; +}; diff --git a/qcom/display/display/trustedvm-kera-sde.dtsi b/qcom/display/display/trustedvm-kera-sde.dtsi new file mode 100644 index 00000000..05d3d958 --- /dev/null +++ b/qcom/display/display/trustedvm-kera-sde.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "kera-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + qcom,sde-hw-version = <0xC0040000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-cdp-overlay.dts b/qcom/display/display/trustedvm-sun-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..757c0dc7 --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun CDP - TrustedVM"; + compatible = "qcom,sun-cdp", "qcom,sun", "qcom,cdp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-cdp.dtsi b/qcom/display/display/trustedvm-sun-sde-display-cdp.dtsi new file mode 100644 index 00000000..cc339fca --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-cdp.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-sec-reset-gpio = <&tlmm 97 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 98 0>; + qcom,platform-bklight-en-gpio = <&tlmm 100 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; + }; +}; + +&qupv3_se15_i2c { + status = "disabled"; + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; + }; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-mtp-overlay.dts b/qcom/display/display/trustedvm-sun-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..0871ba20 --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun MTP - TrustedVM"; + compatible = "qcom,sun-mtp", "qcom,sun", "qcom,mtp"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <8 0>, <0x40008 0>; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-mtp.dtsi b/qcom/display/display/trustedvm-sun-sde-display-mtp.dtsi new file mode 100644 index 00000000..ea7d79ce --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-mtp.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_panel_au { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr>; + }; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-qrd-overlay.dts b/qcom/display/display/trustedvm-sun-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..8fac6d6e --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-sun-sde.dtsi" +#include "trustedvm-sun-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Sun QRD SKU1"; + compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", + "qcom,qrd"; + qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>; + qcom,board-id = <0x1000B 0>, <0x2000B 0>, <0x3000B 0>; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display-qrd.dtsi b/qcom/display/display/trustedvm-sun-sde-display-qrd.dtsi new file mode 100644 index 00000000..cac8c524 --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display-qrd.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-sun-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 98 0>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video>; + }; +}; diff --git a/qcom/display/display/trustedvm-sun-sde-display.dtsi b/qcom/display/display/trustedvm-sun-sde-display.dtsi new file mode 100644 index 00000000..995d7758 --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "sun-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; +}; diff --git a/qcom/display/display/trustedvm-sun-sde.dtsi b/qcom/display/display/trustedvm-sun-sde.dtsi new file mode 100644 index 00000000..fd827da3 --- /dev/null +++ b/qcom/display/display/trustedvm-sun-sde.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "sun-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + + qcom,sde-hw-version =<0xC0000000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-atp-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..0768b294 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..191aa7e0 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-cdp.dtsi b/qcom/display/display/trustedvm-tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..13c0c9d9 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_vtdr6130_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts new file mode 100644 index 00000000..9b5b7dab --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN + Harmonium"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <8 3>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi b/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi new file mode 100644 index 00000000..e9428826 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display-mtp.dtsi" diff --git a/qcom/display/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..f1dfe65f --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-mtp.dtsi b/qcom/display/display/trustedvm-tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..86d21c3f --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-mtp.dtsi @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..40d830d8 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-qrd.dtsi b/qcom/display/display/trustedvm-tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..f456854a --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-qrd.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..c357378d --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/qcom/display/display/trustedvm-tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..80b32374 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>, <694 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display-rumi.dtsi b/qcom/display/display/trustedvm-tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..e9c1e520 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde-display.dtsi b/qcom/display/display/trustedvm-tuna-sde-display.dtsi new file mode 100644 index 00000000..56e90443 --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec>; +}; diff --git a/qcom/display/display/trustedvm-tuna-sde.dtsi b/qcom/display/display/trustedvm-tuna-sde.dtsi new file mode 100644 index 00000000..e07423fe --- /dev/null +++ b/qcom/display/display/trustedvm-tuna-sde.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { + /* dummy display clock provider */ + clock_cpucc: qcom,cpucc { + compatible = "qcom,dummycc"; + clock-output-names = "cpucc_clocks"; + #clock-cells = <1>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x804 0x2>; + qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>; + qcom,iommu-faults = "non-fatal"; + dma-coherent; + }; +}; + +&mdss_mdp { + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x0ae44000 0x02c>; + + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "sid_phys"; + + qcom,sde-vm-exclude-reg-names = "sid_phys"; + + qcom,tvm-include-reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>; + qcom,sde-hw-version =<0xC0000000>; + + clocks = <&clock_cpucc GCC_DISP_AHB_CLK>, + <&clock_cpucc GCC_DISP_HF_AXI_CLK>, + <&clock_cpucc DISP_CC_MDSS_AHB_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>, + <&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "gcc_iface", "gcc_bus", "iface_clk", "branch_clk", + "core_clk", "vsync_clk", "lut_clk"; + qcom,sde-trusted-vm-env; +}; + +&mdss_dsi0 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC0_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi1 { + clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>, + <&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&clock_cpucc DISP_CC_MDSS_ESC1_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk"; +}; + +&mdss_dsi_phy0 { + qcom,dsi-pll-in-trusted-vm; +}; + +&mdss_dsi_phy1 { + qcom,dsi-pll-in-trusted-vm; +}; diff --git a/qcom/display/display/tuna-sde-common.dtsi b/qcom/display/display/tuna-sde-common.dtsi new file mode 100644 index 00000000..e3030150 --- /dev/null +++ b/qcom/display/display/tuna-sde-common.dtsi @@ -0,0 +1,474 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +&soc { + mdss_mdp: qcom,mdss_mdp@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sde-kms"; + reg = <0x0ae00000 0x93800>, + <0x0aeb0000 0x2008>, + <0x0af80000 0x7000>, + <0x400000 0x2000>, + <0x0af50000 0x140>; + reg-names = "mdp_phys", + "vbif_phys", + "regdma_phys", + "ipcc_reg", + "swfuse_phys"; + + /* interrupt config */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + #cooling-cells = <2>; + + /* hw blocks */ + qcom,sde-off = <0x1000>; + qcom,sde-len = <0x488>; + + qcom,sde-ctl-hyp-off = <0x15000>; + qcom,sde-ctl-hyp-size = <0xc00>; + + qcom,sde-ctl-off = <0x16000 0x17000 0x18000 0x19000>; + qcom,sde-ctl-size = <0x1000>; + qcom,sde-ctl-display-pref = "primary", "none", "none", "none"; + + qcom,sde-mixer-off = <0x45000 0x46000 0x47000 + 0x48000 0x0f0f 0x0f0f + 0x0f0f 0x0f0f>; + qcom,sde-mixer-size = <0x400>; + qcom,sde-mixer-display-pref = "primary", "primary", "none", + "none", "none", "none", "none", "none"; + + qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none", + "dcwb", "dcwb", "dcwb", "dcwb"; + + qcom,sde-dspp-top-off = <0x1300>; + qcom,sde-dspp-top-size = <0x8c>; + + qcom,sde-dspp-off = <0x55000 0x57000 0x59000>; + qcom,sde-dspp-size = <0x1800>; + + qcom,sde-dspp-rc-version = <0x00010001>; + qcom,sde-dspp-rc-off = <0x15800 0x14800 0x13800>; + qcom,sde-dspp-rc-size = <0x100>; + qcom,sde-dspp-rc-mem-size = <2720>; + qcom,sde-dspp-rc-min-region-width = <20>; + + qcom,sde-dnsc-blur-version = <0x100>; + qcom,sde-dnsc-blur-off = <0x7D000>; + qcom,sde-dnsc-blur-size = <0x40>; + qcom,sde-dnsc-blur-gaus-lut-off = <0x100>; + qcom,sde-dnsc-blur-gaus-lut-size = <0x400>; + qcom,sde-dnsc-blur-dither-off = <0x5E0>; + qcom,sde-dnsc-blur-dither-size = <0x20>; + + qcom,sde-dest-scaler-top-off = <0x0008F000>; + qcom,sde-dest-scaler-top-size = <0x1C>; + qcom,sde-dest-scaler-off = <0x0 0x1000 0x2000>; + qcom,sde-dest-scaler-size = <0x800>; + + qcom,sde-wb-off = <0x65000 0x66000>; + qcom,sde-wb-size = <0x2c8>; + qcom,sde-wb-xin-id = <0xa 6>; + qcom,sde-wb-id = <1 2>; + + qcom,sde-intf-off = <0x35000 0x36000 0x37000 0x38000>; + qcom,sde-intf-size = <0x4BC>; + qcom,sde-intf-type = "dp", "dsi", "dsi", "dp"; + qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>; + + qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000 + 0x67000 0x67400 0x7f000 0x7f400>; + qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + qcom,sde-pp-size = <0x2c>; + qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2 0x3 0x3>; + + qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700 0x7f700>; + qcom,sde-merge-3d-size = <0x1c>; + qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + + qcom,sde-cdm-off = <0x7a200>; + qcom,sde-cdm-size = <0x240>; + + qcom,sde-dsc-off = <0x81000 0x81000 0x82000>; + qcom,sde-dsc-size = <0x8>; + qcom,sde-dsc-pair-mask = <2 1 0>; + qcom,sde-dsc-hw-rev = "dsc_1_2"; + qcom,sde-dsc-enc = <0x100 0x200 0x100>; + qcom,sde-dsc-enc-size = <0x100>; + qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00>; + qcom,sde-dsc-ctl-size = <0x24>; + qcom,sde-dsc-native422-supp = <1 1 1>; + + qcom,sde-dither-off = <0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0 0xe0>; + qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1>; + qcom,sde-dither-version = <0x00020000>; + qcom,sde-dither-size = <0x20>; + + qcom,sde-sspp-type = "vig", "vig", + "dma", "dma", "dma", "dma", "dma"; + qcom,sde-sspp-off = <0x5000 0x7000 + 0x25000 0x27000 0x29000 0x2b000 0x2d000>; + qcom,sde-sspp-src-size = <0x344>; + + qcom,sde-sspp-xin-id = <0 4 1 5 9 13 14>; + qcom,sde-sspp-excl-rect = <1 1 1 1 1 1 1>; + qcom,sde-sspp-smart-dma-priority = <6 7 1 2 3 4 5>; + qcom,sde-smart-dma-rev = "smart_dma_v2p5"; + + qcom,sde-mixer-pair-mask = <2 1 4 3 6 5 8 7>; + + qcom,sde-mixer-blend-op-off = <0x40 0x70 0xa0 0xd0 0x100 0x130 + 0x160 0x190 0x1c0 0x1f0 0x220>; + + qcom,sde-max-per-pipe-bw-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + qcom,sde-max-per-pipe-bw-high-kbps = <5100000 5100000 + 5100000 5100000 + 5100000 5100000 + 5100000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-sspp-clk-ctrl = + <0x4330 0>, <0x6330 0>, + <0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>, + <0x2c330 0>; + qcom,sde-sspp-clk-status = + <0x4334 0>, <0x6334 0>, + <0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>, + <0x2c334 0>; + qcom,sde-sspp-csc-off = <0x1a00>; + qcom,sde-csc-type = "csc-10bit"; + qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; + qcom,sde-qseed-scalar-version = <0x3004>; + qcom,sde-sspp-qseed-off = <0xa00>; + qcom,sde-mixer-linewidth = <2560>; + qcom,sde-sspp-linewidth = <5120>; + qcom,sde-wb-linewidth = <4096>; + qcom,sde-dsc-linewidth = <2560>; + qcom,sde-max-dest-scaler-input-linewidth = <2048>; + qcom,sde-max-dest-scaler-output-linewidth = <2560>; + qcom,sde-wb-linewidth-linear = <8192>; + qcom,sde-mixer-blendstages = <0xb>; + qcom,sde-highest-bank-bit = <0x8 0x3>; + qcom,sde-ubwc-version = <0x50000001>; + qcom,sde-ubwc-swizzle = <0x6>; + qcom,sde-ubwc-bw-calc-version = <0x1>; + qcom,sde-ubwc-static = <0x1>; + qcom,sde-macrotile-mode = <0x1>; + qcom,sde-smart-panel-align-mode = <0xc>; + qcom,sde-panic-per-pipe; + qcom,sde-has-cdp; + qcom,sde-has-src-split; + qcom,sde-pipe-order-version = <0x1>; + qcom,sde-has-dim-layer; + qcom,sde-has-dest-scaler; + qcom,sde-max-trusted-vm-displays = <1>; + + qcom,sde-max-bw-low-kbps = <23600000>; + qcom,sde-max-bw-high-kbps = <27800000>; + qcom,sde-min-core-ib-kbps = <2500000>; + qcom,sde-min-llcc-ib-kbps = <0>; + qcom,sde-min-dram-ib-kbps = <800000>; + qcom,sde-dram-channels = <4>; + qcom,sde-num-nrt-paths = <0>; + + qcom,sde-dspp-spr-off = <0x15400 0x14400 0x13400>; + qcom,sde-dspp-spr-size = <0x200>; + qcom,sde-dspp-spr-version = <0x00020000>; + + qcom,sde-dspp-demura-off = <0x15600 0x14600 0x13600>; + qcom,sde-dspp-demura-size = <0x150>; + qcom,sde-dspp-demura-version = <0x00030000>; + + qcom,sde-lm-noise-off = <0x320>; + qcom,sde-lm-noise-version = <0x00010000>; + + qcom,sde-uidle-off = <0x80000>; + qcom,sde-uidle-size = <0x80>; + + qcom,sde-vbif-off = <0>; + qcom,sde-vbif-size = <0x1074>; + qcom,sde-vbif-id = <0>; + qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; + qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>; + + qcom,sde-vbif-default-ot-rd-limit = <40>; + qcom,sde-vbif-default-ot-wr-limit = <32>; + qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>; + + qcom,sde-vbif-qos-rt-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>; + qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + qcom,sde-vbif-qos-lutdma-remap = <4 4 4 4 5 5 5 5 4 4 4 4 5 5 5 5>; + qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; + qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 4 4 5 5 5 5>; + qcom,sde-vbif-qos-wb-rot-remap = <4 4 5 5 5 5 5 6 4 4 5 5 5 5 5 6>; + + qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 + 0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0 0xffff0000 0xffff0000>; + + qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001 + 0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0xff 0xff>; + + qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x77776666 0x66666540 0x77776666 0x66666540 + 0x77776541 0x0 0x77776541 0x0 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x00112233 0x44556666 0x00112233 0x66666666 + 0x0 0x0 0x0 0x0 + 0x55555544 0x33221100 0x55555544 0x33221100>; + + qcom,sde-cdp-setting = <1 1>, <1 0>; + + qcom,sde-qos-cpu-mask = <0x3>; + qcom,sde-qos-cpu-mask-performance = <0x3>; + qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; + + qcom,sde-ipcc-protocol-id = <0x4>; + qcom,sde-ipcc-client-dpu-phys-id = <0x14>; + qcom,sde-hw-fence-mdp-ctl-offset = <0x20000>; + + /* offsets are relative to "mdp_phys + qcom,sde-off */ + qcom,sde-reg-dma-off = <0 0x800>; + qcom,sde-reg-dma-id = <0 1>; + qcom,sde-reg-dma-version = <0x00030000>; + qcom,sde-reg-dma-trigger-off = <0x119c>; + qcom,sde-reg-dma-xin-id = <7>; + qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>; + + qcom,sde-secure-sid-mask = <0x801>; + + qcom,sde-reg-bus,vectors-KBps = <0 0>, + <0 14000>, + <0 140000>, + <0 310000>; + + qcom,sde-sspp-vig-blocks { + vcm@0 { + cell-index = <0>; + qcom,sde-vig-top-off = <0x700>; + qcom,sde-vig-csc-off = <0x1a00>; + qcom,sde-vig-qseed-off = <0xa00>; + qcom,sde-vig-qseed-size = <0xe0>; + qcom,sde-vig-gamut = <0x1d00 0x00060001>; + qcom,sde-vig-igc = <0x1d00 0x00060000>; + qcom,sde-vig-inverse-pma; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + vcm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x280 0x00010000>; + qcom,sde-fp16-unmult = <0x280 0x00010000>; + qcom,sde-fp16-gc = <0x280 0x00010000>; + qcom,sde-fp16-csc = <0x280 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-sspp-dma-blocks { + dgm@0 { + cell-index = <0>; + qcom,sde-dma-top-off = <0x700>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x700 0x00010001>; + qcom,sde-ucsc-unmult = <0x700 0x00010001>; + qcom,sde-ucsc-gc = <0x700 0x00010001>; + qcom,sde-ucsc-csc = <0x700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x700 0x00010000>; + }; + + dgm@1 { + cell-index = <1>; + qcom,sde-fp16-igc = <0x200 0x00010000>; + qcom,sde-fp16-unmult = <0x200 0x00010000>; + qcom,sde-fp16-gc = <0x200 0x00010000>; + qcom,sde-fp16-csc = <0x200 0x00010000>; + qcom,sde-ucsc-igc = <0x1700 0x00010001>; + qcom,sde-ucsc-unmult = <0x1700 0x00010001>; + qcom,sde-ucsc-gc = <0x1700 0x00010001>; + qcom,sde-ucsc-csc = <0x1700 0x00010001>; + qcom,sde-ucsc-alpha-dither = <0x1700 0x00010000>; + }; + }; + + qcom,sde-dspp-blocks { + qcom,sde-dspp-igc = <0x1260 0x00050000>; + qcom,sde-dspp-hsic = <0x800 0x00010007>; + qcom,sde-dspp-memcolor = <0x880 0x00010007>; + qcom,sde-dspp-hist = <0x800 0x00010007>; + qcom,sde-dspp-sixzone = <0x900 0x00020000>; + qcom,sde-dspp-vlut = <0xa00 0x00010008>; + qcom,sde-dspp-gamut = <0x1000 0x00040003>; + qcom,sde-dspp-pcc = <0x1700 0x00060000>; + qcom,sde-dspp-gc = <0x17c0 0x00020000>; + qcom,sde-dspp-dither = <0x82c 0x00010007>; + }; + }; + + mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-0"; + cell-index = <0>; + frame-threshold-time-us = <800>; + reg = <0xae94000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae36000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <4 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 { + compatible = "qcom,dsi-ctrl-hw-v2.9"; + label = "dsi-ctrl-1"; + cell-index = <1>; + frame-threshold-time-us = <800>; + reg = <0xae96000 0x1000>, + <0xaf0f000 0x4>, + <0x0ae37000 0x300>; + reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; + interrupt-parent = <&mdss_mdp>; + interrupts = <5 0>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <16600>; + qcom,supply-disable-load = <0>; + }; + }; + }; + + mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-0"; + cell-index = <0>; + #clock-cells = <1>; + reg = <0xae95000 0xa00>, + <0xae95500 0x400>, + <0xae94200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae97500 { + compatible = "qcom,dsi-phy-v5.2"; + label = "dsi-phy-1"; + cell-index = <1>; + #clock-cells = <1>; + reg = <0xae97000 0xa00>, + <0xae97500 0x400>, + <0xae96200 0xa0>; + reg-names = "dsi_phy", "pll_base", "dyn_refresh_base"; + pll-label = "dsi_pll_4nm"; + + qcom,platform-strength-ctrl = [55 03 + 55 03 + 55 03 + 55 03 + 55 00]; + qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; + qcom,platform-lane-config = [00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 0a 0a + 00 00 8a 8a]; + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <98000>; + qcom,supply-disable-load = <96>; + }; + }; + }; + + dsi_pll_codes_data:dsi_pll_codes { + reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 + 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + label = "dsi_pll_codes"; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-atp-overlay.dts b/qcom/display/display/tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..99135b48 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-atp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/qcom/display/display/tuna-sde-display-cdp-overlay.dts b/qcom/display/display/tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..03f5795b --- /dev/null +++ b/qcom/display/display/tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/qcom/display/display/tuna-sde-display-cdp.dtsi b/qcom/display/display/tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..35f2ef16 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-cdp.dtsi @@ -0,0 +1,444 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + +&pm8550vs_d_gpios { + lcd_backlight_ctrl { + lcd_backlight_en_default: lcd_backlight_en_default { + pins = "gpio4"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; + }; +}; + +&pm8550ve_f_gpios { + display_panel_avdd_default: display_panel_avdd_default { + pins = "gpio8"; + function = "normal"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; + qcom,drive-strength = <3>; + }; +}; + +&soc { + display_panel_avdd: display_gpio_regulator@1 { + compatible = "qti-regulator-fixed"; + regulator-name = "display_panel_avdd"; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + regulator-enable-ramp-delay = <233>; + gpio = <&pm8550ve_f_gpios 8 0>; + enable-active-high; + regulator-boot-on; + proxy-supply = <&display_panel_avdd>; + qcom,proxy-consumer-enable; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_avdd_default>; + }; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sharp_4k_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lcd>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-bklight-en-gpio = <&pm8550vs_d_gpios 4 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + avdd-supply = <&display_panel_avdd>; + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; + + goodix-berlin@5d { + panel = <&dsi_vtdr6130_amoled_cmd + &dsi_vtdr6130_amoled_video + &dsi_vtdr6130_amoled_60hz_cmd + &dsi_vtdr6130_amoled_60hz_video + &dsi_vtdr6130_amoled_90hz_cmd + &dsi_vtdr6130_amoled_90hz_video + &dsi_vtdr6130_amoled_120hz_cmd + &dsi_vtdr6130_amoled_120hz_video>; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-common.dtsi b/qcom/display/display/tuna-sde-display-common.dtsi new file mode 100644 index 00000000..093f5ca4 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-common.dtsi @@ -0,0 +1,1445 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-10bit-video.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-spr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-spr.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-cmd-cphy.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video.dtsi" +#include "dsi-panel-nt37801-qsync-dsc-wqhd-plus-video-cphy.dtsi" +#include "dsi-panel-nt37801-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-cmd-ddicspr.dtsi" +#include "dsi-panel-nt37801-dsc-wqhd-plus-video-ddicspr.dtsi" +#include "dsi-panel-sharp-dsc-4k-cmd.dtsi" +#include "dsi-panel-sharp-dsc-4k-video.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-cmd.dtsi" +#include "dsi-panel-sharp-dsc-qhd-plus-video.dtsi" +#include "dsi-panel-sim-cmd-au.dtsi" +#include "dsi-panel-sim-cmd.dtsi" +#include "dsi-panel-sim-dsc-10bit-cmd.dtsi" +#include "dsi-panel-sim-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" +#include "dsi-panel-sim-dualmipi-video.dtsi" +#include "dsi-panel-sim-sec-hd-cmd.dtsi" +#include "dsi-panel-sim-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi" +#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi" +#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi" +#include "dsi-panel-ext-bridge-1080p.dtsi" + +#include "tuna-sde-display-pinctrl.dtsi" + +&soc { + dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "dummy"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + }; + + dsi_panel_pwr_supply: dsi_panel_pwr_supply { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <154000>; + qcom,supply-disable-load = <45000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdd"; + qcom,supply-min-voltage = <1030000>; + qcom,supply-max-voltage = <1100000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <471>; + qcom,supply-post-on-sleep = <0>; + }; + + qcom,panel-supply-entry@2 { + reg = <2>; + qcom,supply-name = "vci"; + qcom,supply-min-voltage = <3000000>; + qcom,supply-max-voltage = <3544000>; + qcom,supply-enable-load = <10000>; + qcom,supply-disable-load = <300>; + qcom,supply-post-on-sleep = <0>; + }; + }; + + dsi_panel_pwr_supply_lcd: dsi_panel_pwr_supply_lcd { + #address-cells = <1>; + #size-cells = <0>; + + qcom,panel-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vddio"; + qcom,supply-min-voltage = <1800000>; + qcom,supply-max-voltage = <1800000>; + qcom,supply-enable-load = <220000>; + qcom,supply-disable-load = <8000>; + qcom,supply-post-on-sleep = <20>; + }; + + qcom,panel-supply-entry@1 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <260000>; + qcom,supply-disable-load = <100>; + }; + }; + + sde_dsi: qcom,dsi-display-primary { + compatible = "qcom,dsi-display"; + label = "primary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + qcom,platform-te-gpio = <&tlmm 77 0>; + qcom,panel-te-source = <0>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0122e700 0x00000471>; + }; + + sde_dsi1: qcom,dsi-display-secondary { + compatible = "qcom,dsi-display"; + label = "secondary"; + + qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; + qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; + + pinctrl-names = "panel_active", "panel_suspend"; + pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; + pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>; + + qcom,platform-te-gpio = <&tlmm 78 0>; + qcom,panel-te-source = <1>; + + qcom,mdp = <&mdss_mdp>; + qcom,demura-panel-id = <0x0 0x0>; + }; +}; + +/* PHY TIMINGS REVISION YYG with reduced margins */ + +&dsi_vtdr6130_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-dyn-clk-enable; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>; + }; + }; +}; + +&dsi_vtdr6130_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + qcom,dsi-supported-dfps-list = <144 120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_120hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-supported-dfps-list = <120 90 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_90hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_60hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 1>, + <1 1 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-panel-hdr-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 08 02 04 1a 0d]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 20 1c 06 + 19 06 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 35 0d 0d 1f 1c 0d + 0e 0e 0c 02 04 2a 12]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <120 110 100 90 80>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 23 22 08 + 19 08 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 00 00 00 25 25 08 + 19 09 02 04 00 00 00]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@2 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@3 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 06 07 02 04 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 28 0a 0b 1b 1a 0a + 0b 0a 02 04 00 21 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 2f 0c 0c 1e 1b 0c + 0d 0c 02 04 00 26 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_ext_bridge_1080p { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 18 22 08 + 08 08 02 04 1a 0c 00]; + qcom,display-topology = <1 0 1>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_4k_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x77>; + qcom,mdss-dsi-panel-on-check-value = <0x77>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,esd-check-enabled; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sharp_qhd_plus_dsc_video { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 15 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,poms-align-panel-vsync; + + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd-vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@1 { /* WQHD 60FPS vid mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 07 07 02 04 00 16 0c]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <50>; + }; + + timing@2 { /* FHD+ 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 22 08 + 08 08 02 04 00 1a 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@3 { /* HD 60FPS cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <48>; + }; + + timing@4 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 26 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@5 { /* FHD+ 180 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 28 16 + 17 14 02 04 00 43 1b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <96>; + }; + + timing@6 { /* FHD+ 240 FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 6f 1f 1f 38 31 1d + 1f 19 02 04 00 55 23]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <110>; + }; + + timing@7 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3e 0f 0f 22 1f 0f + 10 0e 02 04 00 30 14]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <40>; + }; + + timing@8 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 47 12 13 27 22 12 + 13 10 02 04 00 37 17]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <60>; + }; + + timing@9 { /* WQHD 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0D 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@10 { /* WQHD 5FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1D 1A 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@11 { /* WQHD 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@12 { /* WQHD 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 10 1d 03 + 03 02 02 04 00 0b 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <15>; + }; + + timing@13 { /* WQHD 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <22>; + }; + + timing@14 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + + timing@15 { /* WQHD 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + qcom,qsync-mode-min-refresh-rate = <10>; + }; + + timing@16 { /* WQHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 1d 27 0c + 0c 0b 02 04 00 24 11]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <1>; + }; + + timing@17 { /* WQHD 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 38 0e 0e 20 1d 0e + 0e 0d 02 04 00 2c 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <5>; + }; + + timing@18 { /* WQHD 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3d 0f 0f 19 15 0f + 10 0e 02 04 00 2f 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + qcom,qsync-mode-min-refresh-rate = <30>; + }; + }; +}; + +&dsi_sim_vid { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,dsi-supported-dfps-list = <144 120 90 60 30 10 1>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; + + qcom,qsync-enable; + qcom,dsi-supported-qsync-min-fps-list = <1 1 1 1 1 1 1>; + qcom,dsi-qsync-avr-step-list = <288 240 180 120 60 20 0>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 24 0a 0a 1a 24 0a + 0a 09 02 04 00 1e 0f]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 1080p */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* qhd */ + qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03 + 03 02 02 04 00 0b 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* QHD 60fps */ + qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05 + 05 06 02 04 00 13 0a]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@1 { /* FHD+ 60fps cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03 + 03 02 02 04 00 0c 08]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@2 { /* QHD 90fps */ + qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08 + 08 08 02 04 00 19 0d]; + qcom,display-topology = <1 1 1>, + <2 2 1>, /* dsc merge */ + <2 1 1>; /* 3d mux */ + qcom,default-topology-index = <1>; + }; + + timing@3 { /* FHD+ 180FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 2a 0b 0b 1c 1a 0b + 0c 0b 02 04 00 23 10]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* FHD+ 240FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0e 21 1d 0f + 0f 0d 02 04 00 2e 13]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD+ 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06 + 06 06 02 04 00 13 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD+ 1FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01 + 00 01 02 04 00 05 05]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@7 { /* FHD+ 10FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@8 { /* FHD+ 24FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02 + 01 01 02 04 00 08 06]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@9 { /* FHD+ 30FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02 + 02 01 02 04 00 09 07]; + qcom,display-topology = <1 1 1>, + <2 2 1>; + qcom,default-topology-index = <1>; + }; + + timing@10 { /* FHD+ 90FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 12 1e 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* FHD+ 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 5K 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 44 11 12 25 2d 11 + 12 0f 02 04 00 35 16]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* FHD 120FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 17 15 07 + 07 08 02 04 00 18 0c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* WQHD 60FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 0 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 4K 40FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a + 0a 0a 02 04 00 1f 0f]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 5K 80FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 57 17 17 2e 33 17 + 18 14 02 04 00 43 1c]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* FHD 60FPS 24bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* FHD 60FPS 30bpp cmd mode */ + qcom,mdss-dsi-panel-phy-timings = [00 17 06 05 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0"; + + qcom,mdss-dsi-display-timings { + timing@0 { /* 4k 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@1 { /* 4k 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 15 20 06 + 06 07 02 04 00 15 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@2 { /* 4k 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 23 09 + 09 09 02 04 00 1d 0e]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@3 { /* 1080 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@4 { /* 1080 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 1c 03 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@5 { /* 1080 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 11 1d 04 + 03 03 02 04 00 0d 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@6 { /* 1080 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 12 04 + 04 03 02 04 00 0f 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@7 { /* qhd 30 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@8 { /* qhd 60 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 11 1d 04 + 04 03 02 04 00 0d 09]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@9 { /* qhd 90 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 13 1f 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@10 { /* qhd 120 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07 + 06 07 02 04 00 16 0b]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@11 { /* 5k */ + qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07 + 07 07 02 04 00 17 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@12 { /* 720p 30 FPS */ + qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01 + 01 01 02 04 00 07 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@13 { /* 720p 60 FPS */ + qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 0e 1b 01 + 01 02 02 04 00 08 06]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@14 { /* 720p 90 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 0f 1c 02 + 02 02 02 04 00 0a 07]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@15 { /* 720 120 FPS */ + qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 0f 0f 03 + 03 02 02 04 00 0a 08]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@16 { /* 1080 144FPS cmd mode*/ + qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 12 05 + 05 06 02 04 00 12 0a]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + + timing@17 { /* WQHD 144 FPS*/ + qcom,mdss-dsi-panel-phy-timings = [00 1d 07 07 17 16 07 + 07 08 02 04 00 19 0c]; + qcom,display-topology = <2 2 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_sim_sec_hd_cmd { + qcom,dsi-select-sec-clocks = "pll_byte_clk1", "pll_dsi_clk1"; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 12 1e + 04 04 03 02 04 00 0e 09]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts b/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts new file mode 100644 index 00000000..d33cda40 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp-kiwi-harmonium.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP + kiwi WLAN + Harmonium"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <8 3>; +}; diff --git a/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi b/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi new file mode 100644 index 00000000..17dad919 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-mtp-kiwi-harmonium.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display-mtp.dtsi" + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; +}; diff --git a/qcom/display/display/tuna-sde-display-mtp-overlay.dts b/qcom/display/display/tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..46106183 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <8 0>, <8 1>, <8 2>, <8 4>; +}; diff --git a/qcom/display/display/tuna-sde-display-mtp.dtsi b/qcom/display/display/tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..237c7780 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-mtp.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; + +&qupv3_se4_i2c { + st_fts@49 { + panel = <&dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_dsc_10b_cmd + &dsi_nt37801_amoled_dsc_10b_video + &dsi_nt37801_amoled_cmd_spr + &dsi_nt37801_amoled_vid_spr + &dsi_nt37801_amoled_qsync_cmd + &dsi_nt37801_amoled_qsync_video + &dsi_nt37801_amoled_fhd_plus_cmd + &dsi_nt37801_amoled_cmd_ddicspr + &dsi_nt37801_amoled_video_ddicspr>; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-pinctrl.dtsi b/qcom/display/display/tuna-sde-display-pinctrl.dtsi new file mode 100644 index 00000000..dafc8eb9 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-pinctrl.dtsi @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_dsi1_active: sde_dsi1_active { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <8>; /* 8 mA */ + bias-disable = <0>; /* no pull */ + }; + }; + + sde_dsi1_suspend: sde_dsi1_suspend { + mux { + pins = "gpio126"; + function = "gpio"; + }; + + config { + pins = "gpio126"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; + + pmx_sde_te: pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio77"; + function = "mdp_vsync_p"; + }; + + config { + pins = "gpio77"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_active: sde_te1_active { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + sde_te1_suspend: sde_te1_suspend { + mux { + pins = "gpio78"; + function = "mdp_vsync_s"; + }; + + config { + pins = "gpio78"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-qrd-overlay.dts b/qcom/display/display/tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..c650759d --- /dev/null +++ b/qcom/display/display/tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/qcom/display/display/tuna-sde-display-qrd.dtsi b/qcom/display/display/tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..312952ed --- /dev/null +++ b/qcom/display/display/tuna-sde-display-qrd.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&L3D { + qcom,init-voltage = <1090000>; +}; + +&dsi_panel_pwr_supply { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <1090000>; + qcom,supply-max-voltage = <1100000>; + }; +}; + +&dsi_nt37801_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_sim>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; + +&sde_dp { + status = "ok"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 &sde_dp + &sde_cesta>; + +}; + +&qupv3_se4_spi { + st_fts@0 { + panel = <&dsi_nt37801_amoled_cmd_cphy + &dsi_nt37801_amoled_video_cphy + &dsi_nt37801_amoled_cmd + &dsi_nt37801_amoled_video + &dsi_nt37801_amoled_qsync_cmd_cphy + &dsi_nt37801_amoled_qsync_video_cphy>; + }; +}; diff --git a/qcom/display/display/tuna-sde-display-rcm-overlay.dts b/qcom/display/display/tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..a3d546fe --- /dev/null +++ b/qcom/display/display/tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/qcom/display/display/tuna-sde-display-rumi-overlay.dts b/qcom/display/display/tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..d01e5b1d --- /dev/null +++ b/qcom/display/display/tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>, <694 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/display/display/tuna-sde-display-rumi.dtsi b/qcom/display/display/tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..9f4795a1 --- /dev/null +++ b/qcom/display/display/tuna-sde-display-rumi.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; + diff --git a/qcom/display/display/tuna-sde-display.dtsi b/qcom/display/display/tuna-sde-display.dtsi new file mode 100644 index 00000000..402b3d07 --- /dev/null +++ b/qcom/display/display/tuna-sde-display.dtsi @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "tuna-sde-display-common.dtsi" + +&soc { + sde_wb1: qcom,wb-display@1 { + compatible = "qcom,wb-display"; + cell-index = <0>; + label = "wb_display1"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_wb2: qcom,wb-display@2 { + compatible = "qcom,wb-display"; + cell-index = <1>; + label = "wb_display2"; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + disp_rdump_memory: disp_rdump_region@0xfc800000 { + reg = <0xfc800000 0x00800000>; + label = "disp_rdump_region"; + }; +}; + +&reserved_memory { + splash_memory: splash_region { + reg = <0x0 0xFC800000 0x0 0x02B00000>; + label = "cont_splash_region"; + }; +}; + +&sde_dsi { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&sde_dsi1 { + clocks = <&mdss_dsi_phy0 0>, + <&mdss_dsi_phy0 1>, + <&mdss_dsi_phy1 0>, + <&mdss_dsi_phy1 1>, + /* + * Currently the dsi clock handles are under the dsi + * controller DT node. As soon as the controller probe + * finishes, the dispcc sync state can get called before + * the dsi_display probe potentially disturbing the clock + * votes for cont_splash use case. Hence we are no longer + * protected by the component model in this case against the + * disp cc sync state getting triggered after the dsi_ctrl + * probe. To protect against this incorrect sync state trigger + * add this dummy MDP clk vote handle to the dsi_display + * DT node. Since the dsi_display driver does not parse + * MDP clock nodes, no actual vote shall be added and this + * change is done just to satisfy sync state requirements. + */ + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1", + "mdp_core_clk"; + + vddio-supply = <&L8B>; + vci-supply = <&L19B>; + vdd-supply = <&L3D>; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb1 &sde_wb2 + &sde_cesta>; +}; + +&dsi_vtdr6130_amoled_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 40 40 1080 40>; + }; + }; +}; + +&dsi_vtdr6130_amoled_qsync_144hz_cmd { + qcom,ulps-enabled; +}; + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@1 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@2 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@3 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + + timing@4 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <540 40 540 40 1080 40>; + }; + }; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,partial-update-enabled = "single_roi"; + qcom,panel-roi-alignment = <720 40 720 40 1440 40>; + }; + }; +}; + +&dsi_sharp_4k_dsc_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { /* WQHD 60FPS cmd vid mode*/ + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@2 { /* FHD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <540 20 540 20 540 20>; + qcom,partial-update-enabled = "single_roi"; + }; + + timing@3 { /* HD 60FPS cmd mode*/ + qcom,panel-roi-alignment = <360 40 360 40 360 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; + +&dsi_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_cmd { + qcom,ulps-enabled; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,ulps-enabled; +}; + +&dsi_sim_sec_hd_cmd { + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,panel-roi-alignment = <720 40 720 40 720 40>; + qcom,partial-update-enabled = "single_roi"; + }; + }; +}; diff --git a/qcom/display/display/tuna-sde.dts b/qcom/display/display/tuna-sde.dts new file mode 100644 index 00000000..e45c8b27 --- /dev/null +++ b/qcom/display/display/tuna-sde.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "tuna-sde.dtsi" + +/ { + qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>; + qcom,board-id = <0 0>; +}; diff --git a/qcom/display/display/tuna-sde.dtsi b/qcom/display/display/tuna-sde.dtsi new file mode 100644 index 00000000..8dfa80e1 --- /dev/null +++ b/qcom/display/display/tuna-sde.dtsi @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include "tuna-sde-common.dtsi" + +&soc { + ext_disp: qcom,msm-ext-disp { + compatible = "qcom,msm-ext-disp"; + + ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { + compatible = "qcom,msm-ext-disp-audio-codec-rx"; + }; + }; + + qcom_msmhdcp: qcom,msm_hdcp { + compatible = "qcom,msm-hdcp"; + }; + + sde_dp_pll: qcom,dp_pll@88ea000 { + compatible = "qcom,dp-pll-4nm-v1.1"; + #clock-cells = <1>; + }; + + sde_dp: qcom,dp_display@af54000 { + cell-index = <0>; + compatible = "qcom,dp-display"; + status = "disabled"; + + usb-phy = <&usb_qmp_dp_phy>; + qcom,ext-disp = <&ext_disp>; + usb-controller = <&usb0>; + qcom,altmode-dev = <&altmode 0>; + qcom,dp-aux-switch = <&wcd_usbss>; + + reg = <0xaf54000 0x104>, + <0xaf54200 0x0c0>, + <0xaf55000 0x770>, + <0xaf56000 0x09c>, + <0x88eaa00 0x200>, + <0x88ea200 0x200>, + <0x88ea600 0x200>, + <0x88ea000 0x200>, + <0x88e8000 0x020>, + <0xaee1000 0x034>, + <0xaf57000 0x09c>, + <0xaf09000 0x014>; + reg-names = "dp_ahb", "dp_aux", "dp_link", + "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1", + "dp_pll", "usb3_dp_com", "hdcp_physical", + "dp_p1", "gdsc"; + + interrupt-parent = <&mdss_mdp>; + interrupts = <12 0>; + + #clock-cells = <1>; + clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, + <&sde_dp_pll 0>, + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&sde_dp_pll 1>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; + clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src", + "core_usb_pipe_clk", "link_clk", "link_clk_src", "link_parent", + "link_iface_clk", "pixel_clk_rcg", "pixel_parent", + "pixel1_clk_rcg", "strm0_pixel_clk", "strm1_pixel_clk"; + + qcom,dp-pll = <&sde_dp_pll>; + qcom,phy-version = <0x600>; + qcom,aux-cfg0-settings = [20 00]; + qcom,aux-cfg1-settings = [24 13]; + qcom,aux-cfg2-settings = [28 A4]; + qcom,aux-cfg3-settings = [2c 00]; + qcom,aux-cfg4-settings = [30 0a]; + qcom,aux-cfg5-settings = [34 26]; + qcom,aux-cfg6-settings = [38 0a]; + qcom,aux-cfg7-settings = [3c 03]; + qcom,aux-cfg8-settings = [40 b7]; + qcom,aux-cfg9-settings = [44 03]; + + qcom,max-pclk-frequency-khz = <675000>; + + qcom,widebus-enable; + qcom,dsc-feature-enable; + qcom,fec-feature-enable; + qcom,dsc-continuous-pps; + + qcom,qos-cpu-mask = <0xf>; + qcom,qos-cpu-latency-us = <300>; + + vdda-1p2-supply = <&L4B>; + vdda-0p9-supply = <&L3B>; + vdda_usb-0p9-supply = <&L3B>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + + qcom,hbr-rbr-voltage-swing = <0x07 0x0f 0x16 0x1f>, + <0x11 0x1e 0x1f 0xff>, + <0x16 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr-rbr-pre-emphasis = <0x00 0x0d 0x14 0x1a>, + <0x00 0x0e 0x15 0xff>, + <0x00 0x0e 0xff 0xff>, + <0x02 0xff 0xff 0xff>; + + qcom,hbr2-3-voltage-swing = <0x02 0x12 0x16 0x1a>, + <0x09 0x19 0x1f 0xff>, + <0x10 0x1f 0xff 0xff>, + <0x1f 0xff 0xff 0xff>; + qcom,hbr2-3-pre-emphasis = <0x00 0x0c 0x15 0x1b>, + <0x02 0x0e 0x16 0xff>, + <0x02 0x11 0xff 0xff>, + <0x04 0xff 0xff 0xff>; + + qcom,ctrl-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,ctrl-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-1p2"; + qcom,supply-min-voltage = <1200000>; + qcom,supply-max-voltage = <1200000>; + qcom,supply-enable-load = <30000>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,phy-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,phy-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdda-0p9"; + qcom,supply-min-voltage = <912000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <114000>; + qcom,supply-disable-load = <0>; + }; + + qcom,phy-supply-entry@1 { + reg = <1>; + qcom,supply-name = "vdda_usb-0p9"; + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <950000>; + qcom,supply-enable-load = <2500>; + qcom,supply-disable-load = <0>; + }; + }; + + qcom,pll-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,pll-supply-entry@0 { + reg = <0>; + qcom,supply-name = "vdd_mx"; + qcom,supply-min-voltage = + ; + qcom,supply-max-voltage = + ; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; + + }; + + smmu_sde_iommu_region_partition: smmu_sde_iommu_region_partition { + iommu-addresses = <&smmu_sde_unsec 0x0 0x00060000>, + <&smmu_sde_unsec 0xFC800000 0x02B00000>, + <&smmu_sde_sec 0x0 0x00020000>; + }; + + smmu_sde_unsec: qcom,smmu_sde_unsec_cb { + compatible = "qcom,smmu_sde_unsec"; + iommus = <&apps_smmu 0x800 0x2>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-earlymap; /* for cont-splash */ + dma-coherent; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + smmu_sde_sec: qcom,smmu_sde_sec_cb { + compatible = "qcom,smmu_sde_sec"; + iommus = <&apps_smmu 0x801 0x0>; + memory-region = <&smmu_sde_iommu_region_partition>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-vmid = <0xa>; + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "mdp_core_clk"; + }; + + sde_cesta: qcom,sde_cesta@0x0af30000 { + cell-index = <0>; + compatible = "qcom,sde-cesta"; + reg = <0x0af20000 0x850>, + <0xaf30000 0x60>, + <0xaf31000 0x30>, + <0xaf32000 0x30>, + <0xaf33000 0x30>, + <0xaf34000 0x30>, + <0xaf35000 0x30>, + <0xaf36000 0x30>, + <0xaf0f000 0x10>; + reg-names = "rscc", "wrapper", "scc_0", "scc_1", "scc_2", "scc_3", "scc_4", "scc_5", + "disp_cc"; + + clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK_SRC>, + <&dispcc DISP_CC_XO_CLK_SRC>; + + clock-names = "branch_clk", "core_clk", "xo"; + clock-rate = <660000000 660000000 19200000>; + clock-max-rate = <660000000 660000000 19200000>; + clock-mmrm = <0 DISP_CC_MDSS_MDP_CLK_SRC 0>; + + interconnects = <&mmss_noc MASTER_MDP_DISP_CRM_HW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_0>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_1 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_1>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_2 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_2>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_3 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_3>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_4 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_4>, + <&mmss_noc MASTER_MDP_DISP_CRM_HW_5 + &mc_virt SLAVE_EBI1_DISP_CRM_HW_5>, + <&mmss_noc MASTER_MDP_DISP_CRM_SW_0 + &mc_virt SLAVE_EBI1_DISP_CRM_SW_0>; + interconnect-names = "qcom,sde-data-bus-hw-0", "qcom,sde-data-bus-hw-1", + "qcom,sde-data-bus-hw-2", "qcom,sde-data-bus-hw-3", + "qcom,sde-data-bus-hw-4", "qcom,sde-data-bus-hw-5", + "qcom,sde-data-bus-sw-0"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + }; +}; + +&mdss_mdp { + clocks = + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + + clock-names = "gcc_bus", + "iface_clk", "vsync_clk", "lut_clk"; + clock-rate = <0 0 19200000 660000000>; + clock-max-rate = <0 0 19200000 660000000>; + + qcom,hw-fence-sw-version = <0x1>; + + mmcx-supply = <&VDD_MMCX_LEVEL>; + + qti,smmu-proxy-cb-id = ; + + qcom,sde-vm-exclude-reg-names = "ipcc_reg", "swfuse_phys"; + + /* data and reg bus scale settings */ + interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "qcom,sde-data-bus0", + "qcom,sde-ebi-bus", "qcom,sde-reg-bus"; + + qcom,sde-has-idle-pc; + + qcom,sde-ib-bw-vote = <2500000 0 800000>; + qcom,sde-dspp-ltm-version = <0x00010003>; + /* offsets are based off dspp 0, 1, 2, and 3 */ + qcom,sde-dspp-ltm-off = <0x15300 0x14300 0x13300>; + + qcom,platform-supply-entries { + #address-cells = <1>; + #size-cells = <0>; + + qcom,platform-supply-entry@0 { + reg = <0>; + qcom,supply-name = "mmcx"; + qcom,supply-min-voltage = <0>; + qcom,supply-max-voltage = <0>; + qcom,supply-enable-load = <0>; + qcom,supply-disable-load = <0>; + }; + }; +}; + +&mdss_dsi0 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi1 { + vdda-1p2-supply = <&L4B>; + qcom,split-link-supported; + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", + "pixel_clk", "pixel_clk_rcg", "esc_clk", "xo"; +}; + +&mdss_dsi_phy0 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +}; + +&mdss_dsi_phy1 { + vdda-0p9-supply = <&L2B>; + qcom,panel-allow-phy-poweroff; + qcom,dsi-pll-ssc-en; + qcom,dsi-pll-ssc-mode = "down-spread"; + pll_codes_region = <&dsi_pll_codes_data>; +};