From d6149c4ac615c231536003a6b68ed0e8851cb489 Mon Sep 17 00:00:00 2001 From: Satya Durga Srinivasu Prabhala Date: Fri, 22 Dec 2023 10:21:40 -0800 Subject: [PATCH] ARM: dts: msm: correct soccp-config offset for Sun SOC SOCCP sleep status register is incorrectly set to 0x9a000, correct it. Change-Id: I8533e9788614dbb4862ddd272caee7e76b96ed7e Signed-off-by: Satya Durga Srinivasu Prabhala --- qcom/sun.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 61a7b6c0..8b71b2c1 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -3210,7 +3210,7 @@ clock-names = "xo"; memory-region = <&soccp_mem 0>; - soccp-config = <&tcsr 0x9a000>; + soccp-config = <&tcsr 0x1a000>; /* Inputs from SOCCP */ interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,