From 250af492a75bf074a176a770e11058901b8eafea Mon Sep 17 00:00:00 2001
From: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
Date: Mon, 30 Oct 2023 22:19:14 -0700
Subject: [PATCH] ARM: dts: msm: Add Qupv3 Q2SPI instance for pineapple

This change adds Q2SPI support on Qupv3_2 SE5 Instance.

Change-Id: Ib1700b42c04600cc335d560d2991099ea12f8b7e
Signed-off-by: Chandana Kishori Chiluveru <quic_cchiluve@quicinc.com>
---
 qcom/pineapple-pinctrl.dtsi | 82 +++++++++++++++++++++++++++++++++++++
 qcom/pineapple-qupv3.dtsi   | 26 ++++++++++++
 2 files changed, 108 insertions(+)

diff --git a/qcom/pineapple-pinctrl.dtsi b/qcom/pineapple-pinctrl.dtsi
index 67ccadf1..add521f5 100644
--- a/qcom/pineapple-pinctrl.dtsi
+++ b/qcom/pineapple-pinctrl.dtsi
@@ -2168,6 +2168,88 @@
 		};
 	};
 
+	qupv3_se13_q2spi_pins: qupv3_se13_q2spi_pins {
+		qupv3_se13_q2spi_miso_active: qupv3_se13_q2spi_miso_active {
+			mux {
+				pins = "gpio20";
+				function = "qup2_se5_l0";
+			};
+
+			config {
+				pins = "gpio20";
+				drive-strength = <6>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se13_q2spi_mosi_active: qupv3_se13_q2spi_mosi_active {
+			mux {
+				pins = "gpio21";
+				function = "qup2_se5_l1";
+			};
+
+			config {
+				pins = "gpio21";
+				drive-strength = <6>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se13_q2spi_clk_active: qupv3_se13_q2spi_clk_active {
+			mux {
+				pins = "gpio22";
+				function = "qup2_se5_l2";
+			};
+
+			config {
+				pins = "gpio22";
+				drive-strength = <6>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se13_q2spi_doorbell_active: qupv3_se13_q2spi_cs_active {
+			mux {
+				pins = "gpio23";
+				function = "qup2_se5_l6";
+			};
+
+			config {
+				pins = "gpio23";
+				drive-strength = <6>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se13_q2spi_sleep: qupv3_se13_q2spi_sleep {
+			mux {
+				pins = "gpio21", "gpio22",
+					"gpio23";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio21", "gpio22",
+					"gpio23";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+
+		qupv3_se13_q2spi_miso_sleep: qupv3_se13_q2spi_miso_sleep {
+			mux {
+				pins = "gpio20";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio20";
+				drive-strength = <2>;
+				bias-disable;
+			};
+		};
+	};
+
 	qupv3_hub_i2c0_pins: qupv3_hub_i2c0_pins {
 		qupv3_hub_i2c0_sda_active: qupv3_hub_i2c0_sda_active {
 			mux {
diff --git a/qcom/pineapple-qupv3.dtsi b/qcom/pineapple-qupv3.dtsi
index 7a19bbca..88425d2c 100644
--- a/qcom/pineapple-qupv3.dtsi
+++ b/qcom/pineapple-qupv3.dtsi
@@ -910,6 +910,32 @@
 			status = "disabled";
 		};
 
+		/* UWB Q2SPI SE Instance */
+		qupv3_se13_q2spi: q2spi@894000 {
+			compatible = "qcom,q2spi-msm-geni";
+			reg = <0x894000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg-names = "se_phys";
+			interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
+			interconnect-names = "qup-core", "qup-config", "qup-memory";
+			interconnects =
+			<&clk_virt MASTER_QUP_CORE_2 &clk_virt SLAVE_QUP_CORE_2>,
+			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_2>,
+			<&aggre2_noc MASTER_QUP_2 &mc_virt  SLAVE_EBI1>;
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&qupv3_se13_q2spi_mosi_active>, <&qupv3_se13_q2spi_miso_active>,
+				<&qupv3_se13_q2spi_clk_active>, <&qupv3_se13_q2spi_doorbell_active>;
+			pinctrl-1 = <&qupv3_se13_q2spi_sleep>, <&qupv3_se13_q2spi_miso_sleep>;
+			dmas = <&gpi_dma2 0 5 14 64 0>,
+				<&gpi_dma2 1 5 14 64 0>;
+			dma-names = "tx", "rx";
+			q2spi-max-frequency = <10000000>;
+			status = "ok";
+		};
+
 		/* HS UART Instance */
 		qupv3_se14_4uart: qcom,qup_uart@898000 {
 			compatible = "qcom,msm-geni-serial-hs";