From 1cc0326a2814016514baeb8faddf4de4f249571e Mon Sep 17 00:00:00 2001
From: leihan <quic_leihan@quicinc.com>
Date: Fri, 11 Aug 2023 10:14:51 +0800
Subject: [PATCH] dt-bindings: soc: qcom: Add bindings for QSEE IPC interrupt
 bridge

Add the bindings for the QSEE IPC interrupt bridge in YAML.

QSEE IPC interrupt bridge driver can forward remote processor
interrupts to tz.

Change-Id: I1714cfc55422338c0d0674774682ab1f7ac5f4a1
Signed-off-by: leihan <quic_leihan@quicinc.com>
---
 bindings/soc/qcom/qsee_ipc_irq_bridge.yaml | 93 ++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 bindings/soc/qcom/qsee_ipc_irq_bridge.yaml

diff --git a/bindings/soc/qcom/qsee_ipc_irq_bridge.yaml b/bindings/soc/qcom/qsee_ipc_irq_bridge.yaml
new file mode 100644
index 00000000..f59ac22c
--- /dev/null
+++ b/bindings/soc/qcom/qsee_ipc_irq_bridge.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qsee_ipc_irq_bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Secure Execution Environment IPC Interrupt Bridge
+
+maintainers:
+  - Lei Han <quic_leihan@quicinc.com>
+
+description: |
+  Bridge driver for forwarding remote processor interrupts to tz.
+
+properties:
+  compatible:
+    const: qcom,qsee-ipc-irq-bridge
+
+patternProperties:
+  '^qcom,qsee-ipc-irq-[a-zA-Z]+$':
+    type: object
+    description:
+      qcom,qsee-ipc-irq-subsystem
+
+    properties:
+      qcom,dev-name:
+        $ref: '/schemas/types.yaml#/definitions/string'
+        maxItems: 1
+        description:
+          The bridge device name.
+
+      interrupt:
+        $ref: '/schemas/types.yaml#/definitions/uint32-array'
+        minItems: 1
+        description:
+          IPC interrupt line from remote subsystem to QSEE.
+
+      label:
+        $ref: '/schemas/types.yaml#/definitions/string'
+        maxItems: 1
+        description:
+          The name of this subsystem.
+
+      qcom,rx-irq-clr:
+        $ref: '/schemas/types.yaml#/definitions/phandle'
+        maxItems: 1
+        description:
+          The register to clear the level triggered rx interrupt.
+
+      qcom,rx-irq-clr-mask:
+        $ref: '/schemas/types.yaml#/definitions/uint32'
+        maxItems: 1
+        description:
+          The bitmask to clear the rx interrupt.
+
+    required:
+      - qcom,dev-name
+      - interrupt
+      - label
+
+    additionalProperties: false
+
+required:
+  - compatible
+
+additionalProperties: false
+
+examples:
+  - |
+    qcom,qsee_ipc_irq_bridge {
+        compatible = "qcom,qsee-ipc-irq-bridge";
+
+        qcom,qsee-ipc-irq-spss {
+            qcom,rx-irq-clr = <0x1d08008 0x4>;
+            qcom,rx-irq-clr-mask = <0x2>;
+            qcom,dev-name = "qsee_ipc_irq_spss";
+            interrupts = <0 349 4>;
+            label = "spss";
+        };
+    };
+  - |
+    qcom,qsee_ipc_irq_bridge {
+        compatible = "qcom,qsee-ipc-irq-bridge";
+
+        qcom,qsee-ipc-irq-spss {
+            qcom,dev-name = "qsee_ipc_irq_spss";
+            interrupt-parent = <&ipcc_mproc>;
+            interrupts = <IPCC_CLIENT_SPSS
+                          IPCC_MPROC_SIGNAL_TZ
+                          IRQ_TYPE_EDGE_RISING>;
+            label = "spss";
+        };
+    };
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