ARM: dts: msm: Add PCIe RC configuration for sdxkova
Add all 3 PCIe RC configurations for sdxkova. The number of address
cells and size cells are seen as 2 in msm-imem. Based on this add the
register base addresses, MSI register addresses, Host address in ranges
as 64-bit addresses.
Update the PHY settings from latest HSR.
- For PCIe0 and PCIe1 there are no changes in PHY settings, update
the corresponding PHY versions to v1.11 and v1.12.
- For PCIe2, add one change (PCS_G3S2_PRE_GAIN) as per the PHY
version v1.5.
Change-Id: I09519045a13e96878046d905bbe6f2378578c464
Signed-off-by: Sai Chaitanya Kaveti <quic_skaveti@quicinc.com>
This commit is contained in:
Sai Chaitanya Kaveti
831
qcom/sdxkova-pcie.dtsi
Normal file
831
qcom/sdxkova-pcie.dtsi
Normal file
@@ -0,0 +1,831 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,sdx75-gcc.h>
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&soc {
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pcie0: qcom,pcie@1bf0000 {
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compatible = "qcom,pci-msm";
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reg = <0x0 0x01bf0000 0x0 0x4000>,
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<0x0 0x01bf7000 0x0 0x2000>,
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<0x0 0x48000000 0x0 0xf20>,
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<0x0 0x48000f20 0x0 0xa8>,
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<0x0 0x48001000 0x0 0x2000>,
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<0x0 0x48100000 0x0 0x100000>,
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<0x0 0x01bf4000 0x0 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
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"conf", "mhi";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x48200000 0x0 0x48200000 0x0 0x100000>,
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<0x02000000 0x0 0x48300000 0x0 0x48300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_default
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>;
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vreg-1p2-supply = <&L1B>;
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vreg-0p9-supply = <&L4B>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 21700>;
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qcom,vreg-0p9-voltage-level = <880000 880000 177000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen4 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK_SRC>,
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<&pcie_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_sleep_clk", "pcie_phy_refgen_clk",
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"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
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qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <100000000>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_BCR>,
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<&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x0800>;
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iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
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<0x100 &apps_smmu 0x0801 0x1>;
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qcom,boot-option = <0x0>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,tpwr-on-scale = <1>;
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qcom,tpwr-on-value = <9>;
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qcom,eq-fmdc-t-min-phase23 = <1>;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,pcie-phy-ver = <111>;
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qcom,phy-status-offset = <0x1214>;
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qcom,phy-status-bit = <7>;
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qcom,phy-power-down-offset = <0x1240>;
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qcom,phy-sequence = <0x1240 0x03 0x0
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0x0030 0x18 0x0
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0x0034 0x03 0x0
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0x0078 0x01 0x0
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0x007c 0x00 0x0
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0x0080 0x51 0x0
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0x00ac 0x34 0x0
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0x0208 0x0c 0x0
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0x020c 0x0a 0x0
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0x0218 0x04 0x0
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0x0220 0x16 0x0
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0x0234 0x00 0x0
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0x029c 0x80 0x0
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0x02a0 0x7c 0x0
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0x02b4 0x05 0x0
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0x02d4 0x10 0x0
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0x02e8 0x0a 0x0
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0x030c 0x11 0x0
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0x0320 0x0b 0x0
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0x0348 0x1c 0x0
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0x0388 0x20 0x0
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0x0394 0x30 0x0
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0x03dc 0x09 0x0
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0x03f4 0xd4 0x0
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0x03f8 0x73 0x0
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0x03fc 0x18 0x0
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0x0400 0x9a 0x0
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0x0404 0x36 0x0
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0x0408 0xb6 0x0
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0x040c 0xee 0x0
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0x0410 0xcb 0x0
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0x0414 0xcb 0x0
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0x0418 0xe0 0x0
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0x041c 0xdf 0x0
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0x0420 0x78 0x0
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0x0424 0x76 0x0
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0x0428 0xff 0x0
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0x02e0 0x00 0x0
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0x0830 0x18 0x0
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0x0834 0x03 0x0
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0x0878 0x01 0x0
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0x087c 0x00 0x0
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0x0880 0x51 0x0
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0x08ac 0x34 0x0
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0x0a08 0x0c 0x0
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0x0a0c 0x0a 0x0
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0x0a18 0x04 0x0
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0x0a20 0x16 0x0
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0x0a34 0x00 0x0
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0x0a9c 0x80 0x0
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0x0aa0 0x7c 0x0
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0x0ab4 0x05 0x0
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0x0ad4 0x10 0x0
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0x0ae8 0x0a 0x0
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0x0b0c 0x11 0x0
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0x0b20 0x0b 0x0
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0x0b48 0x1c 0x0
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0x0b88 0x20 0x0
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0x0b94 0x30 0x0
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0x0bdc 0x09 0x0
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0x0bf4 0xd4 0x0
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0x0bf8 0x73 0x0
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0x0bfc 0x18 0x0
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0x0c00 0x9a 0x0
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0x0c04 0x36 0x0
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0x0c08 0xb6 0x0
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0x0c0c 0xee 0x0
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0x0c10 0xcb 0x0
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0x0c14 0xcb 0x0
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0x0c18 0xe0 0x0
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0x0c1c 0xdf 0x0
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0x0c20 0x78 0x0
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0x0c24 0x76 0x0
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0x0c28 0xff 0x0
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0x0ae0 0x00 0x0
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0x0ea0 0x01 0x0
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0x0eb4 0x00 0x0
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0x0ec4 0x02 0x0
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0x0ec8 0x0d 0x0
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0x0ed4 0xd4 0x0
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0x0ed8 0x12 0x0
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0x0edc 0xdb 0x0
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0x0ee0 0x9a 0x0
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0x0ee4 0x35 0x0
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0x0ee8 0xb6 0x0
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0x0eec 0x64 0x0
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0x0ef0 0x1f 0x0
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0x0ef4 0x1f 0x0
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0x0ef8 0x1f 0x0
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0x0efc 0x1f 0x0
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0x0f00 0x1f 0x0
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0x0f04 0x1f 0x0
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0x0f0c 0x1f 0x0
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0x0f14 0x1f 0x0
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0x0f1c 0x1f 0x0
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0x0f28 0x5b 0x0
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0x1000 0x97 0x0
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0x1004 0x0c 0x0
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0x1010 0x06 0x0
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0x1014 0x16 0x0
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0x1018 0x36 0x0
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0x101c 0x04 0x0
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0x1020 0x14 0x0
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0x1024 0x34 0x0
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0x1028 0xd0 0x0
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0x1030 0x55 0x0
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0x1034 0x55 0x0
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0x1038 0x05 0x0
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0x103c 0x12 0x0
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0x1060 0xde 0x0
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0x1064 0x07 0x0
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0x1070 0x06 0x0
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0x1074 0x16 0x0
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0x1078 0x36 0x0
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0x107c 0x0a 0x0
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0x1080 0x0a 0x0
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0x1084 0x1a 0x0
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0x1088 0x82 0x0
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0x1090 0x55 0x0
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0x1094 0x55 0x0
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0x1098 0x03 0x0
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0x109c 0x00 0x0
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0x10bc 0x0e 0x0
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0x10c0 0x01 0x0
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0x10cc 0x31 0x0
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0x10d0 0x01 0x0
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0x10d8 0x40 0x0
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0x10dc 0x14 0x0
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0x10e0 0x90 0x0
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0x10e4 0x82 0x0
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0x10f4 0x0f 0x0
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0x1110 0x08 0x0
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0x1120 0x46 0x0
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0x1124 0x04 0x0
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0x1140 0x14 0x0
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0x1164 0x34 0x0
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0x1170 0xa0 0x0
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0x1174 0x06 0x0
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0x1184 0x88 0x0
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0x1188 0x14 0x0
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0x1198 0x0f 0x0
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0x1378 0x2e 0x0
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0x1390 0xcc 0x0
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0x13f8 0x00 0x0
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0x13fc 0x22 0x0
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0x141c 0xc1 0x0
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0x129c 0x83 0x0
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0x12a0 0x09 0x0
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0x12a4 0xa2 0x0
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0x1450 0x03 0x0
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0x1490 0x00 0x0
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0x14a0 0x16 0x0
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0x14f0 0x27 0x0
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0x14f4 0x27 0x0
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0x1508 0x02 0x0
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0x155c 0x2e 0x0
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0x157c 0x03 0x0
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0x1584 0x28 0x0
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0x13dc 0x04 0x0
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0x13e0 0x02 0x0
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0x1418 0xc0 0x0
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0x140c 0x1d 0x0
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0x158c 0x0f 0x0
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0x15ac 0xf2 0x0
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0x15c0 0xf2 0x0
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0x1370 0x17 0x0
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0x1a38 0x00 0x0
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0x1e38 0x00 0x0
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0x1e24 0x00 0x0
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0x1e28 0x00 0x0
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0x1200 0x00 0x0
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0x1244 0x03 0x0>;
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status = "disabled";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x0 0xa0000000 0x0 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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pcie1: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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reg = <0x0 0x01c08000 0x0 0x4000>,
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<0x0 0x01c0e000 0x0 0x2000>,
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<0x0 0x68000000 0x0 0xf1d>,
|
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<0x0 0x68000f20 0x0 0xa8>,
|
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<0x0 0x68001000 0x0 0x1000>,
|
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<0x0 0x68100000 0x0 0x100000>,
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<0x0 0x01c0c000 0x0 0x1000>;
|
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi";
|
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|
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cell-index = <1>;
|
||||
linux,pci-domain = <1>;
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||||
|
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#address-cells = <3>;
|
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#size-cells = <2>;
|
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ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>,
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<0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie1>;
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interrupts = <0 1 2 3 4>;
|
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
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"int_d";
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#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0xffffffff>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 1 &intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &intc GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &intc GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-parent = <&pcie1_msi>;
|
||||
|
||||
perst-gpio = <&tlmm 125 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpio = <&tlmm 123 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie1_clkreq_default
|
||||
&pcie1_perst_default
|
||||
&pcie1_wake_default>;
|
||||
pinctrl-1 = <&pcie1_clkreq_sleep
|
||||
&pcie1_perst_default
|
||||
&pcie1_wake_default>;
|
||||
|
||||
gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
|
||||
gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
|
||||
vreg-1p2-supply = <&L1B>;
|
||||
vreg-0p9-supply = <&L4B>;
|
||||
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||||
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
||||
|
||||
qcom,vreg-1p2-voltage-level = <1200000 1200000 12000>;
|
||||
qcom,vreg-0p9-voltage-level = <912000 880000 77800>;
|
||||
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,bw-scale = /* Gen1 */
|
||||
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000
|
||||
/* Gen2 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000
|
||||
/* Gen3 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000>;
|
||||
|
||||
interconnect-names = "icc_path";
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_1_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPE_DIV2_CLK>,
|
||||
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
|
||||
<&pcie_1_pipe_clk>;
|
||||
|
||||
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
||||
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
||||
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
||||
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
||||
"pcie_pipe_div2_clk", "pcie_phy_refgen_clk",
|
||||
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
|
||||
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <100000000>, <0>, <0>;
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
||||
<0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_1_BCR>,
|
||||
<&gcc GCC_PCIE_1_PHY_BCR>;
|
||||
reset-names = "pcie_1_core_reset",
|
||||
"pcie_1_phy_reset";
|
||||
|
||||
qcom,smmu-sid-base = <0x0880>;
|
||||
iommu-map = <0x0 &apps_smmu 0x0880 0x1>,
|
||||
<0x100 &apps_smmu 0x0881 0x1>;
|
||||
|
||||
qcom,boot-option = <0x0>;
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,tpwr-on-scale = <1>;
|
||||
qcom,tpwr-on-value = <9>;
|
||||
qcom,eq-fmdc-t-min-phase23 = <1>;
|
||||
qcom,l1-2-th-scale = <2>;
|
||||
qcom,l1-2-th-value = <150>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
|
||||
qcom,pcie-phy-ver = <112>;
|
||||
qcom,phy-status-offset = <0x214>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x240>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x00c0 0x01 0x0
|
||||
0x00cc 0x31 0x0
|
||||
0x00d0 0x01 0x0
|
||||
0x0060 0xff 0x0
|
||||
0x0064 0x06 0x0
|
||||
0x0000 0x4c 0x0
|
||||
0x0004 0x06 0x0
|
||||
0x00e0 0x90 0x0
|
||||
0x00e4 0x82 0x0
|
||||
0x00f4 0x07 0x0
|
||||
0x0070 0x02 0x0
|
||||
0x0010 0x02 0x0
|
||||
0x0074 0x16 0x0
|
||||
0x0014 0x16 0x0
|
||||
0x0078 0x36 0x0
|
||||
0x0018 0x36 0x0
|
||||
0x0110 0x08 0x0
|
||||
0x00bc 0x0e 0x0
|
||||
0x0120 0x42 0x0
|
||||
0x0080 0x08 0x0
|
||||
0x0084 0x1a 0x0
|
||||
0x0020 0x14 0x0
|
||||
0x0024 0x34 0x0
|
||||
0x0088 0x82 0x0
|
||||
0x0028 0x68 0x0
|
||||
0x0090 0xab 0x0
|
||||
0x0094 0xea 0x0
|
||||
0x0098 0x02 0x0
|
||||
0x0030 0xab 0x0
|
||||
0x0034 0xaa 0x0
|
||||
0x0038 0x02 0x0
|
||||
0x0140 0x14 0x0
|
||||
0x0164 0x34 0x0
|
||||
0x003c 0x01 0x0
|
||||
0x001c 0x04 0x0
|
||||
0x0174 0x16 0x0
|
||||
0x01bc 0x0f 0x0
|
||||
0x0170 0xa0 0x0
|
||||
0x11a4 0x38 0x0
|
||||
0x10dc 0x0d 0x0
|
||||
0x1160 0xbf 0x0
|
||||
0x1164 0xbf 0x0
|
||||
0x1168 0xb7 0x0
|
||||
0x116c 0xea 0x0
|
||||
0x115c 0x3f 0x0
|
||||
0x1174 0x5c 0x0
|
||||
0x1178 0x9c 0x0
|
||||
0x117c 0x1a 0x0
|
||||
0x1180 0x89 0x0
|
||||
0x1170 0xdc 0x0
|
||||
0x1188 0x94 0x0
|
||||
0x118c 0x5b 0x0
|
||||
0x1190 0x1a 0x0
|
||||
0x1194 0x89 0x0
|
||||
0x10cc 0x00 0x0
|
||||
0x1008 0x09 0x0
|
||||
0x1014 0x05 0x0
|
||||
0x104c 0x08 0x0
|
||||
0x1050 0x08 0x0
|
||||
0x10d8 0x0f 0x0
|
||||
0x1118 0x1c 0x0
|
||||
0x10f8 0x07 0x0
|
||||
0x11f8 0x08 0x0
|
||||
0x1600 0x00 0x0
|
||||
0x0e84 0x15 0x0
|
||||
0x0e90 0x3f 0x0
|
||||
0x0ee4 0x02 0x0
|
||||
0x0e40 0x06 0x0
|
||||
0x0e3c 0x18 0x0
|
||||
0x19a4 0x38 0x0
|
||||
0x18dc 0x0d 0x0
|
||||
0x1960 0xbf 0x0
|
||||
0x1964 0xbf 0x0
|
||||
0x1968 0xb7 0x0
|
||||
0x196c 0xea 0x0
|
||||
0x195c 0x3f 0x0
|
||||
0x1974 0x5c 0x0
|
||||
0x1978 0x9c 0x0
|
||||
0x197c 0x1a 0x0
|
||||
0x1980 0x89 0x0
|
||||
0x1970 0xdc 0x0
|
||||
0x1988 0x94 0x0
|
||||
0x198c 0x5b 0x0
|
||||
0x1990 0x1a 0x0
|
||||
0x1994 0x89 0x0
|
||||
0x18cc 0x00 0x0
|
||||
0x1808 0x09 0x0
|
||||
0x1814 0x05 0x0
|
||||
0x184c 0x08 0x0
|
||||
0x1850 0x08 0x0
|
||||
0x18d8 0x0f 0x0
|
||||
0x1918 0x1c 0x0
|
||||
0x18f8 0x07 0x0
|
||||
0x19f8 0x08 0x0
|
||||
0x1684 0x15 0x0
|
||||
0x1690 0x3f 0x0
|
||||
0x16e4 0x02 0x0
|
||||
0x1640 0x06 0x0
|
||||
0x163c 0x18 0x0
|
||||
0x02dc 0x05 0x0
|
||||
0x0388 0x77 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x06a4 0x1e 0x0
|
||||
0x06f4 0x27 0x0
|
||||
0x03e0 0x0f 0x0
|
||||
0x060c 0x1d 0x0
|
||||
0x0614 0x07 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x03d0 0x8c 0x0
|
||||
0x0368 0x17 0x0
|
||||
0x1424 0x00 0x0
|
||||
0x1428 0x00 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie1_rp: pcie1_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_msi: qcom,pcie1_msi@a0000000 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0xa0000000 0x0 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,snps;
|
||||
};
|
||||
|
||||
pcie2: qcom,pcie@1c10000 {
|
||||
compatible = "qcom,pci-msm";
|
||||
|
||||
reg = <0x0 0x01c10000 0x0 0x4000>,
|
||||
<0x0 0x1c16000 0x0 0x2000>,
|
||||
<0x0 0x6c000000 0x0 0xf1d>,
|
||||
<0x0 0x6c000f20 0x0 0xa8>,
|
||||
<0x0 0x6c001000 0x0 0x1000>,
|
||||
<0x0 0x6c100000 0x0 0x100000>,
|
||||
<0x0 0x01c14000 0x0 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi";
|
||||
|
||||
cell-index = <2>;
|
||||
linux,pci-domain = <2>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x01000000 0x0 0x6c200000 0x0 0x6c200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x6c300000 0x0 0x6c300000 0x0 0x3d00000>;
|
||||
|
||||
interrupt-parent = <&pcie2>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
||||
"int_d";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0xffffffff>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 1 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &intc GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
msi-parent = <&pcie2_msi>;
|
||||
|
||||
perst-gpio = <&tlmm 122 GPIO_ACTIVE_HIGH>;
|
||||
wake-gpio = <&tlmm 120 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pcie2_clkreq_default
|
||||
&pcie2_perst_default
|
||||
&pcie2_wake_default>;
|
||||
pinctrl-1 = <&pcie2_clkreq_sleep
|
||||
&pcie2_perst_default
|
||||
&pcie2_wake_default>;
|
||||
|
||||
gdsc-core-vdd-supply = <&gcc_pcie_2_gdsc>;
|
||||
gdsc-phy-vdd-supply = <&gcc_pcie_2_phy_gdsc>;
|
||||
vreg-1p2-supply = <&L1B>;
|
||||
vreg-0p9-supply = <&L4B>;
|
||||
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||||
vreg-mx-supply = <&VDD_MXA_LEVEL>;
|
||||
|
||||
qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>;
|
||||
qcom,vreg-0p9-voltage-level = <912000 880000 48000>;
|
||||
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
|
||||
qcom,bw-scale = /* Gen1 */
|
||||
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000
|
||||
/* Gen2 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000
|
||||
/* Gen3 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
100000000>;
|
||||
|
||||
interconnect-names = "icc_path";
|
||||
interconnects = <&pcie_anoc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_PCIE_2_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_CLKREF_EN>,
|
||||
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
|
||||
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
|
||||
<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
|
||||
<&pcie_2_pipe_clk>;
|
||||
|
||||
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
||||
"pcie_aux_clk", "pcie_cfg_ahb_clk",
|
||||
"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
|
||||
"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
|
||||
"pcie_pipe_div2_clk", "pcie_phy_refgen_clk",
|
||||
"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
|
||||
qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <0>, <100000000>, <0>, <0>;
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
||||
<0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_2_BCR>,
|
||||
<&gcc GCC_PCIE_2_PHY_BCR>;
|
||||
reset-names = "pcie_2_core_reset",
|
||||
"pcie_2_phy_reset";
|
||||
|
||||
qcom,smmu-sid-base = <0x0900>;
|
||||
iommu-map = <0x0 &apps_smmu 0x0900 0x1>,
|
||||
<0x100 &apps_smmu 0x0901 0x1>;
|
||||
|
||||
qcom,boot-option = <0x0>;
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,tpwr-on-scale = <1>;
|
||||
qcom,tpwr-on-value = <9>;
|
||||
qcom,eq-fmdc-t-min-phase23 = <1>;
|
||||
qcom,l1-2-th-scale = <2>;
|
||||
qcom,l1-2-th-value = <150>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
|
||||
qcom,pcie-phy-ver = <105>;
|
||||
qcom,phy-status-offset = <0x214>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x240>;
|
||||
qcom,phy-sequence = <0x0240 0x03 0x0
|
||||
0x0000 0x4c 0x0
|
||||
0x0004 0x06 0x0
|
||||
0x0010 0x02 0x0
|
||||
0x0014 0x16 0x0
|
||||
0x0018 0x36 0x0
|
||||
0x001c 0x04 0x0
|
||||
0x0020 0x14 0x0
|
||||
0x0024 0x34 0x0
|
||||
0x0028 0x68 0x0
|
||||
0x0030 0xab 0x0
|
||||
0x0034 0xaa 0x0
|
||||
0x0038 0x02 0x0
|
||||
0x003c 0x01 0x0
|
||||
0x0048 0xb4 0x0
|
||||
0x004c 0x03 0x0
|
||||
0x0060 0xde 0x0
|
||||
0x0064 0x07 0x0
|
||||
0x0070 0x02 0x0
|
||||
0x0074 0x16 0x0
|
||||
0x0078 0x36 0x0
|
||||
0x0080 0x0a 0x0
|
||||
0x0084 0x1a 0x0
|
||||
0x0088 0x82 0x0
|
||||
0x0090 0xab 0x0
|
||||
0x0094 0xea 0x0
|
||||
0x0098 0x02 0x0
|
||||
0x00a8 0x24 0x0
|
||||
0x00bc 0x0e 0x0
|
||||
0x00c0 0x00 0x0
|
||||
0x00cc 0x31 0x0
|
||||
0x00d0 0x01 0x0
|
||||
0x00e0 0x90 0x0
|
||||
0x00e4 0x82 0x0
|
||||
0x00f4 0x07 0x0
|
||||
0x0110 0x08 0x0
|
||||
0x0120 0x42 0x0
|
||||
0x0140 0x14 0x0
|
||||
0x0164 0x34 0x0
|
||||
0x0170 0xa0 0x0
|
||||
0x0174 0x16 0x0
|
||||
0x01bc 0x0f 0x0
|
||||
0x02dc 0x05 0x0
|
||||
0x0370 0x2e 0x0
|
||||
0x0388 0x77 0x0
|
||||
0x0398 0x0b 0x0
|
||||
0x03d0 0x0c 0x0
|
||||
0x03e0 0x0f 0x0
|
||||
0x060c 0x1d 0x0
|
||||
0x0620 0xc1 0x0
|
||||
0x0654 0x00 0x0
|
||||
0x0694 0x00 0x0
|
||||
0x06f4 0x27 0x0
|
||||
0x0e3c 0x17 0x0
|
||||
0x0e40 0x06 0x0
|
||||
0x0e84 0x15 0x0
|
||||
0x0e90 0x3f 0x0
|
||||
0x0ea4 0x12 0x0
|
||||
0x0ee4 0x02 0x0
|
||||
0x1008 0x09 0x0
|
||||
0x1014 0x05 0x0
|
||||
0x1034 0x7f 0x0
|
||||
0x1044 0xf0 0x0
|
||||
0x104c 0x08 0x0
|
||||
0x1050 0x08 0x0
|
||||
0x1060 0x30 0x0
|
||||
0x10cc 0xf0 0x0
|
||||
0x10d4 0x04 0x0
|
||||
0x10d8 0x0f 0x0
|
||||
0x10dc 0x0d 0x0
|
||||
0x10ec 0x0e 0x0
|
||||
0x10f0 0x4a 0x0
|
||||
0x10f4 0x0a 0x0
|
||||
0x10f8 0x07 0x0
|
||||
0x1110 0x14 0x0
|
||||
0x1118 0x0c 0x0
|
||||
0x115c 0x3f 0x0
|
||||
0x1160 0xbf 0x0
|
||||
0x1164 0xbf 0x0
|
||||
0x1168 0xb7 0x0
|
||||
0x116c 0xea 0x0
|
||||
0x1170 0xdc 0x0
|
||||
0x1174 0x5c 0x0
|
||||
0x1178 0x9c 0x0
|
||||
0x117c 0x1a 0x0
|
||||
0x1180 0x89 0x0
|
||||
0x1188 0x94 0x0
|
||||
0x118c 0x5b 0x0
|
||||
0x1190 0x1a 0x0
|
||||
0x1194 0x89 0x0
|
||||
0x11a4 0x38 0x0
|
||||
0x11f8 0x08 0x0
|
||||
0x0200 0x00 0x0
|
||||
0x0244 0x03 0x0>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie2_rp: pcie2_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_msi: qcom,pcie2_msi@a0000000 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0xa0000000 0x0 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,snps;
|
||||
};
|
||||
};
|
||||
@@ -6,6 +6,8 @@
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
#include "sdx75.dtsi"
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
/delete-node/ &apps_smmu;
|
||||
/delete-node/ &tcsr_mutex;
|
||||
#include "msm-arm-smmu-sdxkova.dtsi"
|
||||
@@ -293,6 +295,168 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0 {
|
||||
pcie0_perst_default: pcie0_perst_default {
|
||||
mux {
|
||||
pins = "gpio44";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio44";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_default: pcie0_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio43";
|
||||
function = "pcie0_clkreq_n";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_default: pcie0_wake_default {
|
||||
mux {
|
||||
pins = "gpio42";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio42";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio43";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie1 {
|
||||
pcie1_perst_default: pcie1_perst_default {
|
||||
mux {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio125";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_default: pcie1_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio124";
|
||||
function = "pcie1_clkreq_n";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio124";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_wake_default: pcie1_wake_default {
|
||||
mux {
|
||||
pins = "gpio123";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio123";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio124";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio124";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie2 {
|
||||
pcie2_perst_default: pcie2_perst_default {
|
||||
mux {
|
||||
pins = "gpio122";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio122";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_default: pcie2_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "pcie2_clkreq_n";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_wake_default: pcie2_wake_default {
|
||||
mux {
|
||||
pins = "gpio120";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio120";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
|
||||
qupv3_se3_default_cts: qupv3_se3_default_cts {
|
||||
mux {
|
||||
@@ -1086,7 +1250,7 @@
|
||||
#include "sdxkova-regulators.dtsi"
|
||||
|
||||
&chosen {
|
||||
bootargs = "cpufreq.default_governor=performance";
|
||||
bootargs = "cpufreq.default_governor=performance pcie_ports=compat";
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2130,6 +2294,7 @@
|
||||
|
||||
#include "sdxkova-usb.dtsi"
|
||||
#include "ipcc-test-sdxkova.dtsi"
|
||||
#include "sdxkova-pcie.dtsi"
|
||||
|
||||
&CPU0 {
|
||||
/delete-property/ clocks;
|
||||
|
||||
Reference in New Issue
Block a user