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ARM: dts: msm: change compatible of ETM on Sun

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Change compatible of ETM to "arm,coresight-etm4x-sysreg" to use sysreg
access on Sun.

Change-Id: Ie7fbc759a96e0fb4fbe87c7f5467d301cef3405d
Signed-off-by: Yuanfang Zhang <quic_yuanfang@quicinc.com>
This commit is contained in:
Yuanfang Zhang
2024-02-05 14:06:24 +08:00
parent f5a7a87a21
commit 1a2eeaae79
1 changed files with 8 additions and 24 deletions
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32
qcom/sun-coresight.dtsi
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@@ -2162,9 +2162,7 @@
}; };
etm@12c21000 { etm@12c21000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x12c21000 0x1000>;
cpu = <&CPU0>; cpu = <&CPU0>;
coresight-name = "coresight-etm0"; coresight-name = "coresight-etm0";
@@ -2270,9 +2268,7 @@
}; };
etm@12d21000 { etm@12d21000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x12d21000 0x1000>;
cpu = <&CPU1>; cpu = <&CPU1>;
coresight-name = "coresight-etm1"; coresight-name = "coresight-etm1";
@@ -2377,9 +2373,7 @@
}; };
etm@12e21000 { etm@12e21000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x12e21000 0x1000>;
cpu = <&CPU2>; cpu = <&CPU2>;
coresight-name = "coresight-etm2"; coresight-name = "coresight-etm2";
@@ -2484,9 +2478,7 @@
}; };
etm@12f21000 { etm@12f21000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x12f21000 0x1000>;
cpu = <&CPU3>; cpu = <&CPU3>;
coresight-name = "coresight-etm3"; coresight-name = "coresight-etm3";
@@ -2591,9 +2583,7 @@
}; };
etm@13021000 { etm@13021000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x13021000 0x1000>;
cpu = <&CPU4>; cpu = <&CPU4>;
coresight-name = "coresight-etm4"; coresight-name = "coresight-etm4";
@@ -2698,9 +2688,7 @@
}; };
etm@13121000 { etm@13121000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x13121000 0x1000>;
cpu = <&CPU5>; cpu = <&CPU5>;
coresight-name = "coresight-etm5"; coresight-name = "coresight-etm5";
@@ -3033,9 +3021,7 @@
}; };
etm@13521000 { etm@13521000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x13521000 0x1000>;
cpu = <&CPU6>; cpu = <&CPU6>;
coresight-name = "coresight-etm6"; coresight-name = "coresight-etm6";
@@ -3140,9 +3126,7 @@
}; };
etm@13621000 { etm@13621000 {
compatible = "arm,primecell"; compatible = "arm,coresight-etm4x-sysreg";
arm,primecell-periphid = <0x000bb95d>;
reg = <0x13621000 0x1000>;
cpu = <&CPU7>; cpu = <&CPU7>;
coresight-name = "coresight-etm7"; coresight-name = "coresight-etm7";