From 24e6ec54d7ceb3c4ab50dd123df2d5d56bc7d75e Mon Sep 17 00:00:00 2001 From: Prerna Singh Date: Tue, 30 Apr 2024 11:22:23 +0530 Subject: [PATCH] dt-bindings: clock: Add clock controller bindings for Monaco Add clock controller bindings for GCC/GPUCC/DISPCC/DEBUGCC on Monaco Platform. Add clock controller bindings for RPMCC for Monaco, Khaje and Holi platform. Change-Id: I98e6b2094daabc6e6b8b450a397ea3c19799b50a Signed-off-by: Prerna Singh --- bindings/clock/qcom,debugcc.yaml | 1 + bindings/clock/qcom,dispcc-monaco.yaml | 75 ++++++++++++++++++++++++++ bindings/clock/qcom,gcc-monaco.yaml | 69 ++++++++++++++++++++++++ bindings/clock/qcom,gpucc.yaml | 2 + bindings/clock/qcom,rpmcc.yaml | 3 ++ 5 files changed, 150 insertions(+) create mode 100644 bindings/clock/qcom,dispcc-monaco.yaml create mode 100644 bindings/clock/qcom,gcc-monaco.yaml diff --git a/bindings/clock/qcom,debugcc.yaml b/bindings/clock/qcom,debugcc.yaml index 1f057273..2de7c538 100644 --- a/bindings/clock/qcom,debugcc.yaml +++ b/bindings/clock/qcom,debugcc.yaml @@ -20,6 +20,7 @@ properties: - qcom,sun-debugcc - qcom,parrot-debugcc - qcom,sm4450-debugcc + - qcom,monaco-debugcc clocks: items: diff --git a/bindings/clock/qcom,dispcc-monaco.yaml b/bindings/clock/qcom,dispcc-monaco.yaml new file mode 100644 index 00000000..10273f77 --- /dev/null +++ b/bindings/clock/qcom,dispcc-monaco.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,dispcc-monaco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Display Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Qualcomm Technologies, Inc. display clock control module which supports the clocks and + power domains on Monaco. + + See also: + dt-bindings/clock/qcom,dispcc-monaco.h + +properties: + compatible: + enum: + - qcom,monaco-dispcc + + clocks: + items: + - description: Brard XO source + - description: Brard XO_AO source + - description: Sleep clock source + - description: GPLL0 OUT MAIN clock source + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + - const: gpll0_out_main + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + dispcc: clock-controller@5f00000 { + compatible = "qcom,monaco-dispcc", "syscon"; + reg = <0x05f00000 0x20000>; + reg-names = "cc_base"; + clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main", + "sleep_clk"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&gcc GPLL0>, <&sleep_clk>; + vdd_cx-supply = <&VDD_CX_LEVEL>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gcc-monaco.yaml b/bindings/clock/qcom,gcc-monaco.yaml new file mode 100644 index 00000000..34224d72 --- /dev/null +++ b/bindings/clock/qcom,gcc-monaco.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-monaco.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Global Clock & Reset Controller + +maintainers: + - Taniya Das + +description: | + Global clock control module which supports the clocks, resets and + power domains on Monaco. + + See also: + - dt-bindings/clock/qcom,gcc-monaco.h + +properties: + compatible: + const: qcom,monaco-gcc + + clocks: + items: + - description: Board XO source + - description: Board XO_AO source + - description: Sleep clock source + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: bi_tcxo_ao + - const: sleep_clk + minItems: 2 + + vdd_cx-supply: + description: Phandle pointer to the vdd_cx logic rail supply + + vdd_mxa-supply: + description: Phandle pointer to the vdd_mxa logic rail supply + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: "qcom,gcc.yaml#" + +unevaluatedProperties: false + +examples: + - | + #include + gcc: clock-controller@1410000 { + compatible = "qcom,monaco-gcc", "syscon"; + reg = <0x1400000 0x1e0000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + vdd_mx-supply = <&VDD_MXA_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&rpmcc RPM_SMD_XO_A_CLK_SRC>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/bindings/clock/qcom,gpucc.yaml b/bindings/clock/qcom,gpucc.yaml index 81f6a9dc..ecf3cd6a 100644 --- a/bindings/clock/qcom,gpucc.yaml +++ b/bindings/clock/qcom,gpucc.yaml @@ -25,6 +25,7 @@ description: | dt-bindings/clock/qcom,gpucc-pineapple.h dt-bindings/clock/qcom,gpucc-sun.h dt-bindings/clock/qcom,gpucc-parrot.h + dt-bindings/clock/qcom,gpucc-monaco.h properties: compatible: @@ -41,6 +42,7 @@ properties: - qcom,pineapple-gpucc - qcom,sun-gpucc - qcom,parrot-gpucc + - qcom,monaco-gpucc clocks: items: diff --git a/bindings/clock/qcom,rpmcc.yaml b/bindings/clock/qcom,rpmcc.yaml index 2a95bf86..0bac78a7 100644 --- a/bindings/clock/qcom,rpmcc.yaml +++ b/bindings/clock/qcom,rpmcc.yaml @@ -45,6 +45,9 @@ properties: - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 - qcom,rpmcc-sm6375 + - qcom,rpmcc-holi + - qcom,rpmcc-khaje + - qcom,rpmcc-monaco - const: qcom,rpmcc '#clock-cells':