From 4a42af5e4c02c88d7399fc85f2d7c599d5bc6ebf Mon Sep 17 00:00:00 2001
From: Sanjay Yadav <quic_sanjyada@quicinc.com>
Date: Wed, 19 Feb 2025 22:27:25 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Add Kera GPU ACD values

Add ACD control register values and support for Kera GPU.

Change-Id: Idfb20fe8b46655fadf121d2a8192a4fbc42c051c
Signed-off-by: Sanjay Yadav <quic_sanjyada@quicinc.com>
---
 gpu/kera-gpu-pwrlevels.dtsi | 20 ++++++++++++++++++++
 gpu/kera-gpu.dtsi           | 15 +++++++++++++++
 2 files changed, 35 insertions(+)

diff --git a/gpu/kera-gpu-pwrlevels.dtsi b/gpu/kera-gpu-pwrlevels.dtsi
index a84af42e..3f522a55 100644
--- a/gpu/kera-gpu-pwrlevels.dtsi
+++ b/gpu/kera-gpu-pwrlevels.dtsi
@@ -26,6 +26,8 @@
 			qcom,bus-freq-ddr8 = <9>;
 			qcom,bus-min-ddr8 = <8>;
 			qcom,bus-max-ddr8 = <10>;
+
+			qcom,acd-level = <ACD_LEVEL_Turbo_L2>;
 		};
 
 		/* Turbo_L1 */
@@ -41,6 +43,8 @@
 			qcom,bus-freq-ddr8 = <9>;
 			qcom,bus-min-ddr8 = <8>;
 			qcom,bus-max-ddr8 = <10>;
+
+			qcom,acd-level = <ACD_LEVEL_Turbo_L1>;
 		};
 
 		/* Turbo */
@@ -56,6 +60,8 @@
 			qcom,bus-freq-ddr8 = <8>;
 			qcom,bus-min-ddr8 = <8>;
 			qcom,bus-max-ddr8 = <9>;
+
+			qcom,acd-level = <ACD_LEVEL_Turbo>;
 		};
 
 		/* Nom_L1 */
@@ -71,6 +77,8 @@
 			qcom,bus-freq-ddr8 = <8>;
 			qcom,bus-min-ddr8 = <8>;
 			qcom,bus-max-ddr8 = <8>;
+
+			qcom,acd-level = <ACD_LEVEL_Nominal_L1>;
 		};
 
 		/* Nom */
@@ -86,6 +94,8 @@
 			qcom,bus-freq-ddr8 = <7>;
 			qcom,bus-min-ddr8 = <6>;
 			qcom,bus-max-ddr8 = <8>;
+
+			qcom,acd-level = <ACD_LEVEL_Nominal>;
 		};
 
 		/* SVS_L2 */
@@ -101,6 +111,8 @@
 			qcom,bus-freq-ddr8 = <6>;
 			qcom,bus-min-ddr8 = <5>;
 			qcom,bus-max-ddr8 = <7>;
+
+			qcom,acd-level = <ACD_LEVEL_SVS_L2>;
 		};
 
 		/* SVS_L1 */
@@ -116,6 +128,8 @@
 			qcom,bus-freq-ddr8 = <6>;
 			qcom,bus-min-ddr8 = <5>;
 			qcom,bus-max-ddr8 = <7>;
+
+			qcom,acd-level = <ACD_LEVEL_SVS_L1>;
 		};
 
 		/* SVS */
@@ -131,6 +145,8 @@
 			qcom,bus-freq-ddr8 = <4>;
 			qcom,bus-min-ddr8 = <2>;
 			qcom,bus-max-ddr8 = <5>;
+
+			qcom,acd-level = <ACD_LEVEL_SVS>;
 		};
 
 		/* Low_SVS */
@@ -146,6 +162,8 @@
 			qcom,bus-freq-ddr8 = <2>;
 			qcom,bus-min-ddr8 = <2>;
 			qcom,bus-max-ddr8 = <4>;
+
+			qcom,acd-level = <ACD_LEVEL_LowSVS>;
 		};
 
 		/* Low_SVS_D1 */
@@ -161,6 +179,8 @@
 			qcom,bus-freq-ddr8 = <2>;
 			qcom,bus-min-ddr8 = <2>;
 			qcom,bus-max-ddr8 = <4>;
+
+			qcom,acd-level = <ACD_LEVEL_LowSVS_D1>;
 		};
 	};
 };
diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi
index 24fea604..315e1028 100644
--- a/gpu/kera-gpu.dtsi
+++ b/gpu/kera-gpu.dtsi
@@ -5,6 +5,18 @@
 
 #define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
 
+/* ACD Control register values */
+#define ACD_LEVEL_Turbo_L2	0xa8295ffd
+#define ACD_LEVEL_Turbo_L1	0xa82a5ffd
+#define ACD_LEVEL_Turbo		0x882c5ffd
+#define ACD_LEVEL_Nominal_L1	0x882d5ffd
+#define ACD_LEVEL_Nominal	0x882d5ffd
+#define ACD_LEVEL_SVS_L2	0xa82d5ffd
+#define ACD_LEVEL_SVS_L1	0x882f5ffd
+#define ACD_LEVEL_SVS		0Xc02d5ffd
+#define ACD_LEVEL_LowSVS	0Xc82f5ffd
+#define ACD_LEVEL_LowSVS_D1	0Xc82f5ffd
+
 &msm_gpu {
 	compatible = "qcom,adreno-gpu-gen7-17-0", "qcom,kgsl-3d0";
 	status = "ok";
@@ -169,5 +181,8 @@
 
 		iommus = <&kgsl_smmu 0x5 0x000>;
 		qcom,iommu-dma = "disabled";
+
+		mboxes = <&qmp_aop 0>;
+		mbox-names = "aop";
 	};
 };

From ce5d522804fc2ed0f31fb080018a1833a1b14aee Mon Sep 17 00:00:00 2001
From: Sanjay Yadav <quic_sanjyada@quicinc.com>
Date: Thu, 13 Mar 2025 15:03:35 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Remove GPU model reference from Kera GPU

Remove GPU model reference from Kera GPU.

Change-Id: I723b521c23386ed6f50cb32b87b3053cb712aed6
Signed-off-by: Sanjay Yadav <quic_sanjyada@quicinc.com>
---
 gpu/kera-gpu.dtsi | 2 --
 1 file changed, 2 deletions(-)

diff --git a/gpu/kera-gpu.dtsi b/gpu/kera-gpu.dtsi
index 24fea604..eb241e89 100644
--- a/gpu/kera-gpu.dtsi
+++ b/gpu/kera-gpu.dtsi
@@ -26,8 +26,6 @@
 	clock-names = "gcc_gpu_memnoc_gfx", "gpu_cc_ahb",
 		"gpu_cc_hlos1_vote_gpu_smmu", "apb_pclk";
 
-	qcom,gpu-model = "Adreno716";
-
 	qcom,min-access-length = <32>;
 
 	qcom,ubwc-mode = <4>;