From bc61fa2fe011280defa38750f4dccff6f32771bc Mon Sep 17 00:00:00 2001 From: Amruth Naga Date: Fri, 24 May 2024 10:04:55 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add NFC device node for ravelin Device node changes required on ravelin, describing the GPIO configuration for Nfc controller chip. Modified corresponding Nfc device node for ATP, IDP & QRD platforms Change-Id: I331d0ad5aff3cd51bff5cf5268fbfe58c71d8280 --- Kbuild | 7 ++++ nxp/ravelin-nfc-atp.dts | 17 ++++++++++ nxp/ravelin-nfc-common.dtsi | 28 +++++++++++++++ nxp/ravelin-nfc-idp.dts | 17 ++++++++++ nxp/ravelin-nfc-pinctrl.dtsi | 66 ++++++++++++++++++++++++++++++++++++ nxp/ravelin-nfc-qrd.dts | 18 ++++++++++ nxp/ravelin-nfc.dts | 17 ++++++++++ 7 files changed, 170 insertions(+) create mode 100644 nxp/ravelin-nfc-atp.dts create mode 100644 nxp/ravelin-nfc-common.dtsi create mode 100644 nxp/ravelin-nfc-idp.dts create mode 100644 nxp/ravelin-nfc-pinctrl.dtsi create mode 100644 nxp/ravelin-nfc-qrd.dts create mode 100644 nxp/ravelin-nfc.dts diff --git a/Kbuild b/Kbuild index cc665c7c..eb8f4603 100644 --- a/Kbuild +++ b/Kbuild @@ -21,6 +21,13 @@ dtbo-y += nxp/parrot-nfc.dtbo \ nxp/parrot-nfc-atp.dtbo endif +ifeq ($(CONFIG_ARCH_RAVELIN),y) +dtbo-y += nxp/ravelin-nfc.dtbo \ + nxp/ravelin-nfc-qrd.dtbo \ + nxp/ravelin-nfc-idp.dtbo \ + nxp/ravelin-nfc-atp.dtbo +endif + always-y := $(dtb-y) $(dtbo-y) subdir-y := $(dts-dirs) clean-files := *.dtb *.dtbo diff --git a/nxp/ravelin-nfc-atp.dts b/nxp/ravelin-nfc-atp.dts new file mode 100644 index 00000000..801c3056 --- /dev/null +++ b/nxp/ravelin-nfc-atp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-nfc-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin ATP"; + compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>, <663 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/nxp/ravelin-nfc-common.dtsi b/nxp/ravelin-nfc-common.dtsi new file mode 100644 index 00000000..312a7235 --- /dev/null +++ b/nxp/ravelin-nfc-common.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&qupv3_se0_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + nq@28 { + compatible = "qcom,sn-nci"; + reg = <0x28>; + qcom,sn-irq = <&tlmm 9 0x00>; + qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-clkreq = <&tlmm 7 0x00>; + qcom,sn-vdd-1p8-supply = <&L21B>; + qcom,sn-vdd-1p8-voltage = <1800000 1800000>; + qcom,sn-vdd-1p8-current = <157000>; + interrupt-parent = <&tlmm>; + interrupts = <9 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; diff --git a/nxp/ravelin-nfc-idp.dts b/nxp/ravelin-nfc-idp.dts new file mode 100644 index 00000000..4b5ee96d --- /dev/null +++ b/nxp/ravelin-nfc-idp.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-nfc-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin IDP"; + compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>, <663 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/nxp/ravelin-nfc-pinctrl.dtsi b/nxp/ravelin-nfc-pinctrl.dtsi new file mode 100644 index 00000000..90ddf11e --- /dev/null +++ b/nxp/ravelin-nfc-pinctrl.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +&tlmm { + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* NFC Read Interrupt */ + pins = "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; /* 2 MA */ + bias-pull-down; + }; + }; + + nfc_enable_active: nfc_enable_active { + mux { + /* Enable and Clock request gpios */ + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; //nfc +}; //tlmm diff --git a/nxp/ravelin-nfc-qrd.dts b/nxp/ravelin-nfc-qrd.dts new file mode 100644 index 00000000..ed7330cf --- /dev/null +++ b/nxp/ravelin-nfc-qrd.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-nfc-common.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Ravelin QRD"; + compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, <653 0x10000>, + <654 0x10000>, <663 0x10000>; + qcom,board-id = <0x1000B 0>; +}; diff --git a/nxp/ravelin-nfc.dts b/nxp/ravelin-nfc.dts new file mode 100644 index 00000000..e9e3bfdc --- /dev/null +++ b/nxp/ravelin-nfc.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "ravelin-nfc-pinctrl.dtsi" +/ { + model = "Qualcomm Technologies, Inc. Ravelin SoC"; + compatible = "qcom,ravelin"; + qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, <653 0x10000>, + <654 0x10000>, <663 0x10000>; + qcom,board-id = <0 0>; +}; From 71898137ac3932cc0dfbb85004472927a884e9d4 Mon Sep 17 00:00:00 2001 From: Amruth Naga Date: Tue, 9 Jul 2024 11:37:33 +0530 Subject: [PATCH 2/3] [NFC][DTS]: Remove Unused MSM-ID's - Removed Unused MSM-ID's Change-Id: I098839f8b25ab2e3968ec3428c3f6a9af5b2f424 --- nxp/ravelin-nfc-atp.dts | 2 +- nxp/ravelin-nfc-idp.dts | 2 +- nxp/ravelin-nfc-qrd.dts | 3 +-- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/nxp/ravelin-nfc-atp.dts b/nxp/ravelin-nfc-atp.dts index 801c3056..b09bb368 100644 --- a/nxp/ravelin-nfc-atp.dts +++ b/nxp/ravelin-nfc-atp.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin ATP"; compatible = "qcom,ravelin-atp", "qcom,ravelin", "qcom,atp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>, <663 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>; qcom,board-id = <33 0>; }; diff --git a/nxp/ravelin-nfc-idp.dts b/nxp/ravelin-nfc-idp.dts index 4b5ee96d..9e0be587 100644 --- a/nxp/ravelin-nfc-idp.dts +++ b/nxp/ravelin-nfc-idp.dts @@ -12,6 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin IDP"; compatible = "qcom,ravelin-idp", "qcom,ravelin", "qcom,idp"; - qcom,msm-id = <568 0x10000>, <602 0x10000>, <653 0x10000>, <654 0x10000>, <663 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>; qcom,board-id = <34 0>; }; diff --git a/nxp/ravelin-nfc-qrd.dts b/nxp/ravelin-nfc-qrd.dts index ed7330cf..fab15c32 100644 --- a/nxp/ravelin-nfc-qrd.dts +++ b/nxp/ravelin-nfc-qrd.dts @@ -12,7 +12,6 @@ / { model = "Qualcomm Technologies, Inc. Ravelin QRD"; compatible = "qcom,ravelin-qrd", "qcom,ravelin", "qcom,qrd"; - qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, <653 0x10000>, - <654 0x10000>, <663 0x10000>; + qcom,msm-id = <568 0x10000>, <602 0x10000>; qcom,board-id = <0x1000B 0>; }; From 66519741f1fd0bdfd9582780268b99f403b765c1 Mon Sep 17 00:00:00 2001 From: Amruth Naga Date: Wed, 17 Jul 2024 16:28:48 +0530 Subject: [PATCH 3/3] [NFC][DTS]: Fix the FW upgrade issue - Added missed FW gpio changes. Change-Id: Ifafd2041799cf1d0b0b80b2b5a601916280f017a --- nxp/ravelin-nfc-common.dtsi | 1 + nxp/ravelin-nfc-pinctrl.dtsi | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/nxp/ravelin-nfc-common.dtsi b/nxp/ravelin-nfc-common.dtsi index 312a7235..5b476256 100644 --- a/nxp/ravelin-nfc-common.dtsi +++ b/nxp/ravelin-nfc-common.dtsi @@ -14,6 +14,7 @@ reg = <0x28>; qcom,sn-irq = <&tlmm 9 0x00>; qcom,sn-ven = <&tlmm 6 0x00>; + qcom,sn-firm = <&tlmm 8 0x00>; qcom,sn-clkreq = <&tlmm 7 0x00>; qcom,sn-vdd-1p8-supply = <&L21B>; qcom,sn-vdd-1p8-voltage = <1800000 1800000>; diff --git a/nxp/ravelin-nfc-pinctrl.dtsi b/nxp/ravelin-nfc-pinctrl.dtsi index 90ddf11e..790a1704 100644 --- a/nxp/ravelin-nfc-pinctrl.dtsi +++ b/nxp/ravelin-nfc-pinctrl.dtsi @@ -38,13 +38,13 @@ nfc_enable_active: nfc_enable_active { mux { - /* Enable and Clock request gpios */ - pins = "gpio6", "gpio7"; + /* Enable, Firmware and Clock request gpios */ + pins = "gpio6","gpio8", "gpio7"; function = "gpio"; }; config { - pins = "gpio6", "gpio7"; + pins = "gpio6", "gpio8", "gpio7"; drive-strength = <2>; /* 2 MA */ bias-disable; }; @@ -52,12 +52,12 @@ nfc_enable_suspend: nfc_enable_suspend { mux { - pins = "gpio6", "gpio7"; + pins = "gpio6", "gpio8", "gpio7"; function = "gpio"; }; config { - pins = "gpio6", "gpio7"; + pins = "gpio6", "gpio8", "gpio7"; drive-strength = <2>; /* 2 MA */ bias-disable; };