From 14871db80d3cf61d59d4b5401cff84bd2db7143f Mon Sep 17 00:00:00 2001 From: Abhinav Saurabh Date: Tue, 1 Oct 2024 19:24:50 +0530 Subject: [PATCH] ARM: dts: msm: enable display on tuna trustedvm platforms Enable display on tuna trustedvm platforms. Change-Id: I0135626484601f55438135f4beeb6d114d50a559 Signed-off-by: Abhinav Saurabh --- ...trustedvm-tuna-sde-display-atp-overlay.dts | 18 ++ ...trustedvm-tuna-sde-display-cdp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-cdp.dtsi | 161 ++++++++++++++++++ ...edvm-tuna-sde-display-mtp-kiwi-overlay.dts | 18 ++ .../trustedvm-tuna-sde-display-mtp-kiwi.dtsi | 6 + ...trustedvm-tuna-sde-display-mtp-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-mtp.dtsi | 156 +++++++++++++++++ ...trustedvm-tuna-sde-display-qrd-overlay.dts | 18 ++ display/trustedvm-tuna-sde-display-qrd.dtsi | 106 ++++++++++++ ...trustedvm-tuna-sde-display-rcm-overlay.dts | 18 ++ ...rustedvm-tuna-sde-display-rumi-overlay.dts | 17 ++ display/trustedvm-tuna-sde-display-rumi.dtsi | 10 ++ display/trustedvm-tuna-sde-display.dtsi | 28 +++ 13 files changed, 592 insertions(+) create mode 100644 display/trustedvm-tuna-sde-display-atp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-cdp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi create mode 100644 display/trustedvm-tuna-sde-display-mtp-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-mtp.dtsi create mode 100644 display/trustedvm-tuna-sde-display-qrd-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-qrd.dtsi create mode 100644 display/trustedvm-tuna-sde-display-rcm-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi-overlay.dts create mode 100644 display/trustedvm-tuna-sde-display-rumi.dtsi create mode 100644 display/trustedvm-tuna-sde-display.dtsi diff --git a/display/trustedvm-tuna-sde-display-atp-overlay.dts b/display/trustedvm-tuna-sde-display-atp-overlay.dts new file mode 100644 index 00000000..92d161b3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-atp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM ATP"; + compatible = "qcom,tuna-atp", "qcom,tuna", "qcom,tunap-atp", "qcom,tunap", + "qcom,atp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <33 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp-overlay.dts b/display/trustedvm-tuna-sde-display-cdp-overlay.dts new file mode 100644 index 00000000..823d8b0c --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM CDP"; + compatible = "qcom,tuna-cdp", "qcom,tuna", "qcom,tunap-cdp", "qcom,tunap", + "qcom,cdp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <1 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-cdp.dtsi b/display/trustedvm-tuna-sde-display-cdp.dtsi new file mode 100644 index 00000000..bd14043b --- /dev/null +++ b/display/trustedvm-tuna-sde-display-cdp.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts new file mode 100644 index 00000000..b552bb5d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp-kiwi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP + kiwi WLAN"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 2>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi new file mode 100644 index 00000000..e9428826 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-kiwi.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display-mtp.dtsi" diff --git a/display/trustedvm-tuna-sde-display-mtp-overlay.dts b/display/trustedvm-tuna-sde-display-mtp-overlay.dts new file mode 100644 index 00000000..4bd8c860 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-mtp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM MTP"; + compatible = "qcom,tuna-mtp", "qcom,tuna", "qcom,tunap-mtp", "qcom,tunap", + "qcom,mtp"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <8 0>, <8 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-mtp.dtsi b/display/trustedvm-tuna-sde-display-mtp.dtsi new file mode 100644 index 00000000..4738255d --- /dev/null +++ b/display/trustedvm-tuna-sde-display-mtp.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_dsc_10b_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_vid_spr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_fhd_plus_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_ddicspr { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd-overlay.dts b/display/trustedvm-tuna-sde-display-qrd-overlay.dts new file mode 100644 index 00000000..5192b5e3 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-qrd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM QRD"; + compatible = "qcom,tuna-qrd", "qcom,tuna", "qcom,tunap-qrd", "qcom,tunap", + "qcom,qrd"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <11 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-qrd.dtsi b/display/trustedvm-tuna-sde-display-qrd.dtsi new file mode 100644 index 00000000..f456854a --- /dev/null +++ b/display/trustedvm-tuna-sde-display-qrd.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&dsi_nt37801_amoled_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_cmd_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_nt37801_amoled_qsync_video_cphy { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <10>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <8191>; + qcom,mdss-dsi-bl-inverted-dbv; + qcom,platform-reset-gpio = <&tlmm 14 0>; + qcom,platform-sec-reset-gpio = <&tlmm 126 0>; +}; + +&dsi_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_vid { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_dual_sim_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,bl-dsc-cmd-state = "dsi_lp_mode"; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; +}; + +&dsi_sim_sec_hd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; +}; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_nt37801_amoled_cmd_cphy>; +}; diff --git a/display/trustedvm-tuna-sde-display-rcm-overlay.dts b/display/trustedvm-tuna-sde-display-rcm-overlay.dts new file mode 100644 index 00000000..2f339264 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rcm-overlay.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-cdp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RCM"; + compatible = "qcom,tuna-rcm", "qcom,tuna", "qcom,tunap-rcm", "qcom,tunap", + "qcom,rcm"; + qcom,msm-id = <681 0x10000>, <655 0x10000>; + qcom,board-id = <21 0>, <21 1>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi-overlay.dts b/display/trustedvm-tuna-sde-display-rumi-overlay.dts new file mode 100644 index 00000000..665cb540 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi-overlay.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; +/plugin/; + +#include "trustedvm-tuna-sde.dtsi" +#include "trustedvm-tuna-sde-display-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Tuna SVM RUMI"; + compatible = "qcom,tuna-rumi", "qcom,tuna", "qcom,rumi"; + qcom,msm-id = <655 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/display/trustedvm-tuna-sde-display-rumi.dtsi b/display/trustedvm-tuna-sde-display-rumi.dtsi new file mode 100644 index 00000000..e9c1e520 --- /dev/null +++ b/display/trustedvm-tuna-sde-display-rumi.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "trustedvm-tuna-sde-display.dtsi" + +&mdss_mdp { + qcom,sde-emulated-env; +}; diff --git a/display/trustedvm-tuna-sde-display.dtsi b/display/trustedvm-tuna-sde-display.dtsi new file mode 100644 index 00000000..22b2e5b0 --- /dev/null +++ b/display/trustedvm-tuna-sde-display.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "tuna-sde-display-common.dtsi" + +&sde_dsi { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&sde_dsi1 { + clocks = <&clock_cpucc 0>, + <&clock_cpucc 1>, + <&clock_cpucc 2>, + <&clock_cpucc 3>; + clock-names = "pll_byte_clk0", "pll_dsi_clk0", + "pll_byte_clk1", "pll_dsi_clk1"; +}; + +&mdss_mdp { + connectors = <&sde_dsi &sde_dsi1>; +};