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ARM: dts: msm: Add Turbo_L1 support to Sun V2 GPU freq plan

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Ensure the Sun V2 GPU Turbo_L1 frequency is available
on AA and AB parts.

Change-Id: I45f6b804a81211584efe4fcb06e4c7b3dc848263
Signed-off-by: Carter Cooper <quic_ccooper@quicinc.com>
This commit is contained in:
Carter Cooper
2024-09-29 20:26:42 -06:00
parent 6ebc4a3afd
commit 13196ae45e
1 changed files with 74 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

122
gpu/sun-v2-gpu-pwrlevels.dtsi
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@@ -349,7 +349,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
qcom,initial-pwrlevel = <11>; qcom,initial-pwrlevel = <12>;
qcom,speed-bin = <0xe8>; qcom,speed-bin = <0xe8>;
/* TURBO_L3 */ /* TURBO_L3 */
@@ -365,9 +365,22 @@
qcom,acd-level = <ACD_LEVEL_TURBO_L3>; qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
}; };
/* NOM_L1 */ /* TURBO_L1 */
qcom,gpu-pwrlevel@1 { qcom,gpu-pwrlevel@1 {
reg = <1>; reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>; qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -379,8 +392,8 @@
}; };
/* NOM */ /* NOM */
qcom,gpu-pwrlevel@2 { qcom,gpu-pwrlevel@3 {
reg = <2>; reg = <3>;
qcom,gpu-freq = <900000000>; qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -392,8 +405,8 @@
}; };
/* SVS_L2 */ /* SVS_L2 */
qcom,gpu-pwrlevel@3 { qcom,gpu-pwrlevel@4 {
reg = <3>; reg = <4>;
qcom,gpu-freq = <832000000>; qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -405,8 +418,8 @@
}; };
/* SVS_L1 */ /* SVS_L1 */
qcom,gpu-pwrlevel@4 { qcom,gpu-pwrlevel@5 {
reg = <4>; reg = <5>;
qcom,gpu-freq = <734000000>; qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -418,8 +431,8 @@
}; };
/* SVS_L0 */ /* SVS_L0 */
qcom,gpu-pwrlevel@5 { qcom,gpu-pwrlevel@6 {
reg = <5>; reg = <6>;
qcom,gpu-freq = <660000000>; qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -431,8 +444,8 @@
}; };
/* SVS */ /* SVS */
qcom,gpu-pwrlevel@6 { qcom,gpu-pwrlevel@7 {
reg = <6>; reg = <7>;
qcom,gpu-freq = <607000000>; qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -444,8 +457,8 @@
}; };
/* Low_SVS_L1 */ /* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 { qcom,gpu-pwrlevel@8 {
reg = <7>; reg = <8>;
qcom,gpu-freq = <525000000>; qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -457,8 +470,8 @@
}; };
/* Low_SVS */ /* Low_SVS */
qcom,gpu-pwrlevel@8 { qcom,gpu-pwrlevel@9 {
reg = <8>; reg = <9>;
qcom,gpu-freq = <443000000>; qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -470,8 +483,8 @@
}; };
/* Low_SVS_D0 */ /* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 { qcom,gpu-pwrlevel@10 {
reg = <9>; reg = <10>;
qcom,gpu-freq = <389000000>; qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -483,8 +496,8 @@
}; };
/* Low_SVS_D1 */ /* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 { qcom,gpu-pwrlevel@11 {
reg = <10>; reg = <11>;
qcom,gpu-freq = <342000000>; qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -494,8 +507,8 @@
}; };
/* Low_SVS_D2 */ /* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 { qcom,gpu-pwrlevel@12 {
reg = <11>; reg = <12>;
qcom,gpu-freq = <222000000>; qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
@@ -505,8 +518,8 @@
}; };
/* Low_SVS_D3 */ /* Low_SVS_D3 */
qcom,gpu-pwrlevel@12 { qcom,gpu-pwrlevel@13 {
reg = <12>; reg = <13>;
qcom,gpu-freq = <160000000>; qcom,gpu-freq = <160000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;
@@ -520,7 +533,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
qcom,initial-pwrlevel = <11>; qcom,initial-pwrlevel = <12>;
qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AA) qcom,sku-codes = <SKU_CODE(PCODE_UNKNOWN, FC_AA)
SKU_CODE(PCODE_UNKNOWN, FC_AB)>; SKU_CODE(PCODE_UNKNOWN, FC_AB)>;
@@ -537,9 +550,22 @@
qcom,acd-level = <ACD_LEVEL_TURBO_L3>; qcom,acd-level = <ACD_LEVEL_TURBO_L3>;
}; };
/* NOM_L1 */ /* TURBO_L1 */
qcom,gpu-pwrlevel@1 { qcom,gpu-pwrlevel@1 {
reg = <1>; reg = <1>;
qcom,gpu-freq = <1050000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <11>;
qcom,bus-max = <11>;
qcom,acd-level = <ACD_LEVEL_TURBO_L1>;
};
/* NOM_L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <967000000>; qcom,gpu-freq = <967000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@@ -551,8 +577,8 @@
}; };
/* NOM */ /* NOM */
qcom,gpu-pwrlevel@2 { qcom,gpu-pwrlevel@3 {
reg = <2>; reg = <3>;
qcom,gpu-freq = <900000000>; qcom,gpu-freq = <900000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>; qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@@ -564,8 +590,8 @@
}; };
/* SVS_L2 */ /* SVS_L2 */
qcom,gpu-pwrlevel@3 { qcom,gpu-pwrlevel@4 {
reg = <3>; reg = <4>;
qcom,gpu-freq = <832000000>; qcom,gpu-freq = <832000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@@ -577,8 +603,8 @@
}; };
/* SVS_L1 */ /* SVS_L1 */
qcom,gpu-pwrlevel@4 { qcom,gpu-pwrlevel@5 {
reg = <4>; reg = <5>;
qcom,gpu-freq = <734000000>; qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@@ -590,8 +616,8 @@
}; };
/* SVS_L0 */ /* SVS_L0 */
qcom,gpu-pwrlevel@5 { qcom,gpu-pwrlevel@6 {
reg = <5>; reg = <6>;
qcom,gpu-freq = <660000000>; qcom,gpu-freq = <660000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
@@ -603,8 +629,8 @@
}; };
/* SVS */ /* SVS */
qcom,gpu-pwrlevel@6 { qcom,gpu-pwrlevel@7 {
reg = <6>; reg = <7>;
qcom,gpu-freq = <607000000>; qcom,gpu-freq = <607000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@@ -616,8 +642,8 @@
}; };
/* Low_SVS_L1 */ /* Low_SVS_L1 */
qcom,gpu-pwrlevel@7 { qcom,gpu-pwrlevel@8 {
reg = <7>; reg = <8>;
qcom,gpu-freq = <525000000>; qcom,gpu-freq = <525000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
@@ -629,8 +655,8 @@
}; };
/* Low_SVS */ /* Low_SVS */
qcom,gpu-pwrlevel@8 { qcom,gpu-pwrlevel@9 {
reg = <8>; reg = <9>;
qcom,gpu-freq = <443000000>; qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
@@ -642,8 +668,8 @@
}; };
/* Low_SVS_D0 */ /* Low_SVS_D0 */
qcom,gpu-pwrlevel@9 { qcom,gpu-pwrlevel@10 {
reg = <9>; reg = <10>;
qcom,gpu-freq = <389000000>; qcom,gpu-freq = <389000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
@@ -655,8 +681,8 @@
}; };
/* Low_SVS_D1 */ /* Low_SVS_D1 */
qcom,gpu-pwrlevel@10 { qcom,gpu-pwrlevel@11 {
reg = <10>; reg = <11>;
qcom,gpu-freq = <342000000>; qcom,gpu-freq = <342000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
@@ -666,8 +692,8 @@
}; };
/* Low_SVS_D2 */ /* Low_SVS_D2 */
qcom,gpu-pwrlevel@11 { qcom,gpu-pwrlevel@12 {
reg = <11>; reg = <12>;
qcom,gpu-freq = <222000000>; qcom,gpu-freq = <222000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
@@ -677,8 +703,8 @@
}; };
/* Low_SVS_D3 */ /* Low_SVS_D3 */
qcom,gpu-pwrlevel@12 { qcom,gpu-pwrlevel@13 {
reg = <12>; reg = <13>;
qcom,gpu-freq = <160000000>; qcom,gpu-freq = <160000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>;