diff --git a/qcom/nfc/Kbuild b/qcom/nfc/Kbuild
new file mode 100644
index 00000000..1ae2f2b2
--- /dev/null
+++ b/qcom/nfc/Kbuild
@@ -0,0 +1,38 @@
+ifeq ($(CONFIG_ARCH_SUN),y)
+dtbo-y += nxp/sun-nfc.dtbo \
+          nxp/sun-nfc-cdp.dtbo \
+          nxp/sun-nfc-mtp.dtbo \
+          nxp/sun-nfc-qrd.dtbo \
+          nxp/tuna-nfc.dtbo \
+          nxp/kera-nfc.dtbo \
+
+dtbo-y += st/sun-nfc.dtbo \
+          st/sun-nfc-mtp.dtbo \
+          st/sun-nfc-cdp.dtbo \
+          st/sun-nfc-qrd-sku1.dtbo \
+          st/sun-nfc-qrd-sku1-v8.dtbo \
+          st/sun-nfc-qrd-sku2-v8.dtbo \
+          st/sun-nfc-atp.dtbo \
+          st/sun-mtp-kiwi-v8.dtbo \
+          st/sun-nfc-rcm.dtbo \
+          st/tuna-nfc.dtbo \
+          st/kera-nfc.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_PARROT),y)
+dtbo-y += nxp/parrot-nfc.dtbo \
+          nxp/parrot-nfc-qrd.dtbo \
+          nxp/parrot-nfc-idp.dtbo \
+          nxp/parrot-nfc-atp.dtbo \
+          nxp/parrot-nfc-idp-wcn6755.dtbo \
+          nxp/parrot-nfc-idp-wcn3990-amoled-rcm.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_RAVELIN),y)
+dtbo-y += nxp/ravelin-nfc.dtbo
+endif
+
+
+always-y        := $(dtb-y) $(dtbo-y)
+subdir-y        := $(dts-dirs)
+clean-files     := *.dtb *.dtbo
diff --git a/qcom/nfc/Makefile b/qcom/nfc/Makefile
new file mode 100644
index 00000000..f2d100f2
--- /dev/null
+++ b/qcom/nfc/Makefile
@@ -0,0 +1,12 @@
+KBUILD_OPTIONS += KBUILD_EXTMOD_DTS=.
+
+all: dtbs
+
+%:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
+
+modules_install:
+	$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
+
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
\ No newline at end of file
diff --git a/qcom/nfc/nxp/kera-nfc-common.dtsi b/qcom/nfc/nxp/kera-nfc-common.dtsi
new file mode 100644
index 00000000..c15f739d
--- /dev/null
+++ b/qcom/nfc/nxp/kera-nfc-common.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "kera-nfc-pinctrl.dtsi"
+&qupv3_se9_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 7 0x00>;
+		qcom,sn-ven = <&tlmm 57 0x00>;
+		qcom,sn-clkreq = <&tlmm 6 0x00>;
+		qcom,sn-szone = "enable";
+		interrupt-parent = <&tlmm>;
+		interrupts = <7 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
+
diff --git a/qcom/nfc/nxp/kera-nfc-pinctrl.dtsi b/qcom/nfc/nxp/kera-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..f0ac326d
--- /dev/null
+++ b/qcom/nfc/nxp/kera-nfc-pinctrl.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, and Clock request gpios */
+				pins = "gpio57", "gpio6";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio57", "gpio6";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio57", "gpio6";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio57", "gpio6";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
+
diff --git a/qcom/nfc/nxp/kera-nfc.dts b/qcom/nfc/nxp/kera-nfc.dts
new file mode 100644
index 00000000..2cd005d2
--- /dev/null
+++ b/qcom/nfc/nxp/kera-nfc.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "kera-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Kera SoC";
+        compatible = "qcom,kera";
+        qcom,msm-id = <686 0x10000>, <659 0x10000>;
+        qcom,board-id = <33 0>, <0x10001 0>, <0x30001 0>, <0x20001 0>, <0x40001 0>,
+                    <0x10008 0>, <0x20008 0>, <0x20008 1>, <0x10008 1>, <0x10015 0>,
+                    <0x10015 1>, <0x20015 0>, <0x20015 1>, <0x30015 0>, <0x30015 1>,
+                    <0x1000B 0>, <0x3000B 0>, <0x2000B 0>, <0x3000B 1>;
+};
diff --git a/qcom/nfc/nxp/parrot-nfc-atp.dts b/qcom/nfc/nxp/parrot-nfc-atp.dts
new file mode 100644
index 00000000..a5ec33df
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-atp.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot ATP";
+	compatible = "qcom,parrot-atp", "qcom,parrot", "qcom,atp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+	qcom,board-id = <33 0>;
+};
diff --git a/qcom/nfc/nxp/parrot-nfc-common.dtsi b/qcom/nfc/nxp/parrot-nfc-common.dtsi
new file mode 100644
index 00000000..5080a9f7
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-common.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&qupv3_se6_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 9 0x00>;
+		qcom,sn-ven = <&tlmm 6 0x00>;
+		qcom,sn-clkreq = <&tlmm 7 0x00>;
+		qcom,sn-vdd-1p8-supply = <&L21B>;
+		qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
+		qcom,sn-vdd-1p8-current = <157000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
diff --git a/qcom/nfc/nxp/parrot-nfc-idp-wcn3990-amoled-rcm.dts b/qcom/nfc/nxp/parrot-nfc-idp-wcn3990-amoled-rcm.dts
new file mode 100644
index 00000000..2acebba2
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-idp-wcn3990-amoled-rcm.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot WCN3990 IDP + AMOLED + RCM";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+	qcom,board-id = <34 3>;
+};
diff --git a/qcom/nfc/nxp/parrot-nfc-idp-wcn6755.dts b/qcom/nfc/nxp/parrot-nfc-idp-wcn6755.dts
new file mode 100644
index 00000000..b09f7068
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-idp-wcn6755.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-common.dtsi"
+ / {
+ 	model = "Qualcomm Technologies, Inc. Parrot WCN6755 IDP";
+ 	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+ 	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+ 			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+ 			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+ 	qcom,board-id = <34 5>;
+ };
diff --git a/qcom/nfc/nxp/parrot-nfc-idp.dts b/qcom/nfc/nxp/parrot-nfc-idp.dts
new file mode 100644
index 00000000..de504d1d
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-idp.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot IDP";
+	compatible = "qcom,parrot-idp", "qcom,parrot", "qcom,idp";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+	qcom,board-id = <34 0>, <34 1>, <34 5>;
+};
diff --git a/qcom/nfc/nxp/parrot-nfc-pinctrl.dtsi b/qcom/nfc/nxp/parrot-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..90ddf11e
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable and Clock request gpios */
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio6", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/nxp/parrot-nfc-qrd.dts b/qcom/nfc/nxp/parrot-nfc-qrd.dts
new file mode 100644
index 00000000..679cea7b
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc-qrd.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot QRD";
+	compatible = "qcom,parrot-qrd";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+	qcom,board-id = <0x1000B 0>;
+};
+
diff --git a/qcom/nfc/nxp/parrot-nfc.dts b/qcom/nfc/nxp/parrot-nfc.dts
new file mode 100644
index 00000000..14b167c6
--- /dev/null
+++ b/qcom/nfc/nxp/parrot-nfc.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "parrot-nfc-pinctrl.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Parrot SoC";
+	compatible = "qcom,parrot";
+	qcom,msm-id = <537 0x10000>, <583 0x10000>, <613 0x10000>, <631 0x10000>,
+			<633 0x10000>, <634 0x10000>, <638 0x10000>,
+			<663 0x10000>, <713 0x10000>, <714 0x10000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/nfc/nxp/ravelin-nfc-common.dtsi b/qcom/nfc/nxp/ravelin-nfc-common.dtsi
new file mode 100644
index 00000000..9cd4d439
--- /dev/null
+++ b/qcom/nfc/nxp/ravelin-nfc-common.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "ravelin-nfc-pinctrl.dtsi"
+
+&qupv3_se0_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 9 0x00>;
+		qcom,sn-ven = <&tlmm 6 0x00>;
+                qcom,sn-firm = <&tlmm 8 0x00>;
+		qcom,sn-clkreq = <&tlmm 7 0x00>;
+		qcom,sn-vdd-1p8-supply = <&L21B>;
+		qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
+		qcom,sn-vdd-1p8-current = <157000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <9 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
diff --git a/qcom/nfc/nxp/ravelin-nfc-pinctrl.dtsi b/qcom/nfc/nxp/ravelin-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..790a1704
--- /dev/null
+++ b/qcom/nfc/nxp/ravelin-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio9";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio9";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, Firmware and Clock request gpios */
+				pins = "gpio6","gpio8", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio8", "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio6", "gpio8", "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio6", "gpio8", "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/nxp/ravelin-nfc.dts b/qcom/nfc/nxp/ravelin-nfc.dts
new file mode 100644
index 00000000..5422e356
--- /dev/null
+++ b/qcom/nfc/nxp/ravelin-nfc.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "ravelin-nfc-common.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Ravelin SoC";
+	compatible = "qcom,ravelin";
+	qcom,msm-id = <568 0x10000>, <602 0x10000>, <581 0x10000>, <582 0x10000>, <653 0x10000>,
+                      <654 0x10000>;
+	qcom,board-id = <33 0>,<34 0>, <0x1000B 0>, <34 0x601>,  <0x1000B 0x600>, <34 2>;
+};
diff --git a/qcom/nfc/nxp/sun-nfc-cdp.dts b/qcom/nfc/nxp/sun-nfc-cdp.dts
new file mode 100644
index 00000000..62d78a3c
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc-cdp.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+
+/ {
+        model = "Qualcomm Technologies, Inc. Sun CDP";
+        compatible = "qcom,sun-cdp", "qcom,sun", "qcom,sunp-cdp", "qcom,sunp", "qcom,cdp";
+        qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+        qcom,board-id = <0x40001 0>;
+};
diff --git a/qcom/nfc/nxp/sun-nfc-common.dtsi b/qcom/nfc/nxp/sun-nfc-common.dtsi
new file mode 100644
index 00000000..2ba69808
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc-common.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&qupv3_se0_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 75 0x00>;
+		qcom,sn-ven = <&tlmm 34 0x00>;
+		qcom,sn-clkreq = <&tlmm 35 0x00>;
+		qcom,sn-szone = "enable";
+		interrupt-parent = <&tlmm>;
+		interrupts = <75 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
diff --git a/qcom/nfc/nxp/sun-nfc-mtp.dts b/qcom/nfc/nxp/sun-nfc-mtp.dts
new file mode 100644
index 00000000..5e3861dd
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc-mtp.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+
+/ {
+        model = "Qualcomm Technologies, Inc. Sun MTP";
+        compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp", "qcom,mtp";
+        qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+        qcom,board-id = <0x30008 0>, <0x70008 0>;
+};
diff --git a/qcom/nfc/nxp/sun-nfc-pinctrl.dtsi b/qcom/nfc/nxp/sun-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..9f17d1c3
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio75";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio75";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio75";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio75";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, and Clock request gpios */
+				pins = "gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/nxp/sun-nfc-qrd.dts b/qcom/nfc/nxp/sun-nfc-qrd.dts
new file mode 100644
index 00000000..c91e0f50
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc-qrd.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+
+/ {
+        model = "Qualcomm Technologies, Inc. Sun QRD";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp",
+			   "qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+	qcom,board-id = <0x4000B 0>;
+};
diff --git a/qcom/nfc/nxp/sun-nfc.dts b/qcom/nfc/nxp/sun-nfc.dts
new file mode 100644
index 00000000..71915971
--- /dev/null
+++ b/qcom/nfc/nxp/sun-nfc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-pinctrl.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Sun SoC";
+        compatible = "qcom,sun";
+        qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+        qcom,board-id = <0 0>;
+};
diff --git a/qcom/nfc/nxp/tuna-nfc-common.dtsi b/qcom/nfc/nxp/tuna-nfc-common.dtsi
new file mode 100644
index 00000000..4874d49b
--- /dev/null
+++ b/qcom/nfc/nxp/tuna-nfc-common.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#include "tuna-nfc-pinctrl.dtsi"
+
+&qupv3_se0_i2c {
+	status = "ok";
+	qcom,clk-freq-out = <1000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	nq@28 {
+		compatible = "qcom,sn-nci";
+		reg = <0x28>;
+		qcom,sn-irq = <&tlmm 55 0x00>;
+		qcom,sn-ven = <&tlmm 114 0x00>;
+		qcom,sn-clkreq = <&tlmm 115 0x00>;
+		qcom,sn-szone = "enable";
+		interrupt-parent = <&tlmm>;
+		interrupts = <55 0>;
+		interrupt-names = "nfc_irq";
+		pinctrl-names = "nfc_active", "nfc_suspend";
+		pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+		pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+	};
+};
diff --git a/qcom/nfc/nxp/tuna-nfc-pinctrl.dtsi b/qcom/nfc/nxp/tuna-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..fa234eff
--- /dev/null
+++ b/qcom/nfc/nxp/tuna-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, and Clock request gpios */
+				pins = "gpio114", "gpio115";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio114", "gpio115";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio114", "gpio115";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio114", "gpio115";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/nxp/tuna-nfc.dts b/qcom/nfc/nxp/tuna-nfc.dts
new file mode 100644
index 00000000..936049e9
--- /dev/null
+++ b/qcom/nfc/nxp/tuna-nfc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "tuna-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Tuna SoC";
+        compatible = "qcom,tuna";
+        qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
+        qcom,board-id = <8 4>;
+};
diff --git a/qcom/nfc/st/kera-nfc-common.dtsi b/qcom/nfc/st/kera-nfc-common.dtsi
new file mode 100644
index 00000000..abca9415
--- /dev/null
+++ b/qcom/nfc/st/kera-nfc-common.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "kera-nfc-pinctrl.dtsi"
+
+&qupv3_se9_i2c {
+        status = "ok";
+        qcom,clk-freq-out = <1000000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        st21nfc: st21nfc@08 {
+                compatible = "st,st21nfc";
+                reg = <0x08>;
+                irq-gpios = <&tlmm 7 0x00>;
+                reset-gpios = <&tlmm 57 0x00>;
+                clkreq-gpios = <&tlmm 6 0x00>;
+                interrupt-parent = <&tlmm>;
+                interrupts = <7 0>;
+                interrupt-names = "nfc_irq";
+                pinctrl-names = "nfc_active", "nfc_suspend";
+                pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+                pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+        };
+};
diff --git a/qcom/nfc/st/kera-nfc-pinctrl.dtsi b/qcom/nfc/st/kera-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..7e4a17ad
--- /dev/null
+++ b/qcom/nfc/st/kera-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio7";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio7";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, and Clock request gpios */
+				pins = "gpio57", "gpio6";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio57", "gpio6";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio57", "gpio6";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio57", "gpio6";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/st/kera-nfc.dts b/qcom/nfc/st/kera-nfc.dts
new file mode 100644
index 00000000..4a68a621
--- /dev/null
+++ b/qcom/nfc/st/kera-nfc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "kera-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Kera SoC";
+        compatible = "qcom,kera";
+        qcom,msm-id = <686 0x10000>, <659 0x10000>;
+        qcom,board-id = <0x30008 0>, <0x30008 1>;
+};
diff --git a/qcom/nfc/st/sun-mtp-kiwi-v8.dts b/qcom/nfc/st/sun-mtp-kiwi-v8.dts
new file mode 100644
index 00000000..ce72b368
--- /dev/null
+++ b/qcom/nfc/st/sun-mtp-kiwi-v8.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP Kiwi WLAN V8 Power Grid";
+	compatible = "qcom,sun-mtp", "qcom,sun", "qcom,sunp-mtp", "qcom,sunp",
+			   "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>;
+	qcom,board-id = <0x50008 0>;
+};
+
diff --git a/qcom/nfc/st/sun-nfc-atp.dts b/qcom/nfc/st/sun-nfc-atp.dts
new file mode 100644
index 00000000..1665e712
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-atp.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Sun ATP";
+	compatible = "qcom,sun-atp", "qcom,sun", "qcom,sunp-atp", "qcom,sunp",
+			   "qcom,atp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>;
+	qcom,board-id = <0x10021 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-cdp.dts b/qcom/nfc/st/sun-nfc-cdp.dts
new file mode 100644
index 00000000..16e36c9c
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-cdp.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Sun CDP";
+	compatible = "qcom, sun-cdp", "qcom,sun", "qcom,cdp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+	qcom,board-id = <0x1 0>, <0x20001 0>, <0x50001 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-common.dtsi b/qcom/nfc/st/sun-nfc-common.dtsi
new file mode 100644
index 00000000..02a066e5
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-common.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+
+&qupv3_se0_i2c {
+        status = "ok";
+        qcom,clk-freq-out = <1000000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        st21nfc: st21nfc@08 {
+                compatible = "st,st21nfc";
+                reg = <0x08>;
+                irq-gpios = <&tlmm 75 0x00>;
+                reset-gpios = <&tlmm 34 0x00>;
+                clkreq-gpios = <&tlmm 35 0x00>;
+                interrupt-parent = <&tlmm>;
+                interrupts = <75 0>;
+                interrupt-names = "nfc_irq";
+                pinctrl-names = "nfc_active", "nfc_suspend";
+                pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+                pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+        };
+};
diff --git a/qcom/nfc/st/sun-nfc-mtp.dts b/qcom/nfc/st/sun-nfc-mtp.dts
new file mode 100644
index 00000000..e2605d5d
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-mtp.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Sun MTP";
+	compatible = "qcom, sun-mtp", "qcom,sun", "qcom,mtp";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+	qcom,board-id = <0x8 0>, <0x20008 0>, <0x40008 0>, <0x50008 0>, <0x60008 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-pinctrl.dtsi b/qcom/nfc/st/sun-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..1c69223f
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio75";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio75";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio75";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio75";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable and Clock request gpios */
+				pins = "gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio34", "gpio35";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio34", "gpio35";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/st/sun-nfc-qrd-sku1-v8.dts b/qcom/nfc/st/sun-nfc-qrd-sku1-v8.dts
new file mode 100644
index 00000000..6408dc86
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-qrd-sku1-v8.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Sun QRD SKU1 V8 Power Grid";
+        compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp","qcom,qrd";
+        qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>;
+        qcom,board-id = <0x3000B 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-qrd-sku1.dts b/qcom/nfc/st/sun-nfc-qrd-sku1.dts
new file mode 100644
index 00000000..b1252f14
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-qrd-sku1.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Sun QRD SKU1";
+	compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp", "qcom,qrd";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>;
+	qcom,board-id = <0x1000B 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-qrd-sku2-v8.dts b/qcom/nfc/st/sun-nfc-qrd-sku2-v8.dts
new file mode 100644
index 00000000..eee84f27
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-qrd-sku2-v8.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Sun QRD SKU2 V8 Power Grid";
+        compatible = "qcom,sun-qrd", "qcom,sun", "qcom,sunp-qrd", "qcom,sunp","qcom,qrd";
+        qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+                      <0x100027f 0x10000>, <0x100027f 0x20000>;
+        qcom,board-id = <0x2000B 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc-rcm.dts b/qcom/nfc/st/sun-nfc-rcm.dts
new file mode 100644
index 00000000..72053c83
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc-rcm.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Sun RCM";
+	compatible = "qcom,sun-rcm", "qcom,sun", "qcom,sunp", "qcom,rcm";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>;
+	qcom,board-id = <0x15 0>;
+};
diff --git a/qcom/nfc/st/sun-nfc.dts b/qcom/nfc/st/sun-nfc.dts
new file mode 100644
index 00000000..9fd98552
--- /dev/null
+++ b/qcom/nfc/st/sun-nfc.dts
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "sun-nfc-pinctrl.dtsi"
+/ {
+	model = "Qualcomm Technologies, Inc. Sun";
+	compatible = "qcom,sun";
+	qcom,msm-id = <618 0x10000>, <618 0x20000>, <639 0x10000>, <639 0x20000>,
+		      <0x100026a 0x10000>, <0x100026a 0x20000>,
+		      <0x100027f 0x10000>, <0x100027f 0x20000>;
+	qcom,board-id = <0 0>;
+};
diff --git a/qcom/nfc/st/tuna-nfc-common.dtsi b/qcom/nfc/st/tuna-nfc-common.dtsi
new file mode 100644
index 00000000..58dcdf18
--- /dev/null
+++ b/qcom/nfc/st/tuna-nfc-common.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "tuna-nfc-pinctrl.dtsi"
+
+&qupv3_se0_i2c {
+        status = "ok";
+        qcom,clk-freq-out = <1000000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        st21nfc: st21nfc@08 {
+                compatible = "st,st21nfc";
+                reg = <0x08>;
+                irq-gpios = <&tlmm 55 0x00>;
+                reset-gpios = <&tlmm 114 0x00>;
+                clkreq-gpios = <&tlmm 115 0x00>;
+                interrupt-parent = <&tlmm>;
+                interrupts = <55 0>;
+                interrupt-names = "nfc_irq";
+                pinctrl-names = "nfc_active", "nfc_suspend";
+                pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
+                pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+        };
+};
diff --git a/qcom/nfc/st/tuna-nfc-pinctrl.dtsi b/qcom/nfc/st/tuna-nfc-pinctrl.dtsi
new file mode 100644
index 00000000..fa234eff
--- /dev/null
+++ b/qcom/nfc/st/tuna-nfc-pinctrl.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&tlmm {
+	nfc {
+		nfc_int_active: nfc_int_active {
+			/* active state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_int_suspend: nfc_int_suspend {
+			/* sleep state */
+			mux {
+				/* NFC Read Interrupt */
+				pins = "gpio55";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio55";
+				drive-strength = <2>; /* 2 MA */
+				bias-pull-down;
+			};
+		};
+
+		nfc_enable_active: nfc_enable_active {
+			mux {
+				/* Enable, and Clock request gpios */
+				pins = "gpio114", "gpio115";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio114", "gpio115";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+
+		nfc_enable_suspend: nfc_enable_suspend {
+			mux {
+				pins = "gpio114", "gpio115";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio114", "gpio115";
+				drive-strength = <2>; /* 2 MA */
+				bias-disable;
+			};
+		};
+	}; //nfc
+}; //tlmm
diff --git a/qcom/nfc/st/tuna-nfc.dts b/qcom/nfc/st/tuna-nfc.dts
new file mode 100644
index 00000000..45be6f56
--- /dev/null
+++ b/qcom/nfc/st/tuna-nfc.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include "tuna-nfc-common.dtsi"
+/ {
+        model = "Qualcomm Technologies, Inc. Tuna SoC";
+        compatible = "qcom,tuna";
+        qcom,msm-id = <681 0x10000>, <655 0x10000>, <694 0x10000>;
+        qcom,board-id = <33 0>, <1 0>, <8 0>, <8 3>, <11 0>, <21 0>;
+};