diff --git a/qcom/sdxkova-usb.dtsi b/qcom/sdxkova-usb.dtsi new file mode 100644 index 00000000..a48f3171 --- /dev/null +++ b/qcom/sdxkova-usb.dtsi @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +&soc { + usb: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0x0 0xa600000 0x0 0x100000>; + reg-names = "core_base"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 10 IRQ_TYPE_EDGE_RISING>, + <&pdc 9 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_gdsc>; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", + "bus_aggr_clk", "utmi_clk", + "sleep_clk"; + + resets = <&gcc GCC_USB30_BCR>; + reset-names = "core_reset"; + + qcom,sleep-clk-bcr; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,core-clk-rate-disconnected = <133333333>; + + dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xa600000 0x0 0xd93c>; + + iommus = <&apps_smmu 0x80 0x0>; + qcom,iommu-dma = "atomic"; + memory-region = <&dwc3_mem_region>; + dma-coherent; + + interrupts = ; + usb-phy = <&usb_nop_phy>, <&usb_qmp_phy>; + snps,has-lpm-erratum; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,hird-threshold = /bits/ 8 <0x10>; + tx-fifo-resize; + /* set host mode interrupt moderation to 1 us */ + imod-interval-ns = <1000>; + maximum-speed = "super-speed-plus"; + usb-role-switch; + dr_mode = "peripheral"; + }; + + }; + + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3 0x0 0x0 0x0 0x90000000>, + <&dwc3 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related QMP USB UNI PHY */ + usb_qmp_phy: ssphy@ff6000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0x0 0xff6000 0x0 0x2000>, + <0x0 0xff7400 0x0 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&L4B>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L1B>; + qcom,core-max-load-uA = <15000>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk", "ref_clk_src", + "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/sdxkova.dtsi b/qcom/sdxkova.dtsi index 7b0b9aac..0e1add5a 100644 --- a/qcom/sdxkova.dtsi +++ b/qcom/sdxkova.dtsi @@ -399,3 +399,5 @@ #clock-cells = <1>; #reset-cells = <1>; }; + +#include "sdxkova-usb.dtsi"