From 10d8b6507b62cc966c08cbb27844961bbf4ade43 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Fri, 29 Dec 2023 17:17:27 +0800 Subject: [PATCH] =?UTF-8?q?ARM:=20dts:=20qcom:=20use=20property=20?= =?UTF-8?q?=E2=80=9Ciommu-addresses=E2=80=9D=20for=20UFSHC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The upstream commit ("iommu: Implement of_iommu_get_resv_regions()") has added a devicetree property "iommu-addresses", which describes to the DMA api what IOVA addresses a device can/cannot use. So we replace “qcom,iommu-dma-addr-pool” by “iommu-addresses” since kernel 6.5 to follow upstream. Change-Id: I9c99fc931fa9a59a472f371bfb59f615f83539f4 Signed-off-by: Ziqi Chen --- qcom/sun.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index b394d74e..1071b45f 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -2254,6 +2254,14 @@ reg = <0x10c3000 0x1000>; }; + ufshc_dma_resv: ufshc_dma_resv_region { + /* + * Restrict IOVA mappings for UFSHC buffers to the 3 GB region + * from 0x1000 - 0xffffffff. + */ + iommu-addresses = <&ufshc_mem 0x0 0x1000>; + }; + ufshc_mem: ufshc@1d84000 { compatible = "qcom,ufshc"; reg = <0x1d84000 0x3000>, @@ -2374,8 +2382,8 @@ iommus = <&apps_smmu 0x60 0x0>; qcom,iommu-dma = "fastmap"; - qcom,iommu-dma-addr-pool = <0x1000 0xFFFFF000>; qcom,iommu-msi-size = <0x1000>; + memory-region = <&ufshc_dma_resv>; shared-ice-cfg = <&ice_cfg>; dma-coherent;