diff --git a/bindings/soc/qcom/qcom,gic-interrupt-router.yaml b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
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+++ b/bindings/soc/qcom/qcom,gic-interrupt-router.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,gic-interrupt-router.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. GIC Interrupt Router
+
+description: |
+  The ARM GIC peripheral supports "1 of N" selection of SPI interrupts. CPUs
+  may be classified as class0 and/or class1 and SPIs may be routed to any CPU
+  in a particular class.
+
+properties:
+  compatible:
+    const: "qcom,gic-intr-routing"
+    Usage: required
+
+  qcom,gic-class0-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 0.
+
+  qcom,gic-class1-cpus:
+    Usage: required
+    Value type: <prop-encoded-array>
+    Definition: List of CPUs in GIC class 1.
+
+examples:
+  - |
+    qcom,gic-interrupt-router {
+      compatible = "qcom,gic-intr-routing";
+      qcom,gic-class0-cpus = <0 1 2 3>;
+      qcom,gic-class1-cpus = <4 5 6 7>;
+    };
+...