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Merge "ARM: dts: msm: Add spi, i2c, gpi nodes for SVM kera"

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QCTECMDR Service
2024-11-06 23:01:15 -08:00
committed by Gerrit - the friendly Code Review server
parent 2ea738eb40 e6e2aa812d
commit 0bdf8836e1
2 changed files with 174 additions and 10 deletions
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22
qcom/kera-qupv3.dtsi
View File

@@ -47,7 +47,8 @@
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x1f>; qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>; qcom,ev-factor = <1>;
memory-region = <&qup1_gpi_iommu_region>; memory-region = <&qup1_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>; qcom,gpi-ee-offset = <0x10000>;
@@ -92,8 +93,8 @@
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>; pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
pinctrl-1 = <&qupv3_se0_i2c_sleep>; pinctrl-1 = <&qupv3_se0_i2c_sleep>;
dmas = <&gpi_dma1 0 0 3 64 0>, dmas = <&gpi_dma1 0 0 3 64 2>,
<&gpi_dma1 1 0 3 64 0>; <&gpi_dma1 1 0 3 64 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -116,8 +117,8 @@
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>, pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>; <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
pinctrl-1 = <&qupv3_se0_spi_sleep>; pinctrl-1 = <&qupv3_se0_spi_sleep>;
dmas = <&gpi_dma1 0 0 1 64 0>, dmas = <&gpi_dma1 0 0 1 64 2>,
<&gpi_dma1 1 0 1 64 0>; <&gpi_dma1 1 0 1 64 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
status = "disabled"; status = "disabled";
@@ -434,7 +435,8 @@
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,gpii-mask = <0x1f>; qcom,static-gpii-mask = <0x1>;
qcom,gpii-mask = <0x1e>;
qcom,ev-factor = <1>; qcom,ev-factor = <1>;
memory-region = <&qup2_gpi_iommu_region>; memory-region = <&qup2_gpi_iommu_region>;
qcom,gpi-ee-offset = <0x10000>; qcom,gpi-ee-offset = <0x10000>;
@@ -480,8 +482,8 @@
pinctrl-names = "default", "sleep"; pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>; pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
pinctrl-1 = <&qupv3_se8_i2c_sleep>; pinctrl-1 = <&qupv3_se8_i2c_sleep>;
dmas = <&gpi_dma2 0 0 3 64 0>, dmas = <&gpi_dma2 0 0 3 64 2>,
<&gpi_dma2 1 0 3 64 0>; <&gpi_dma2 1 0 3 64 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
status = "disabled"; status = "disabled";
}; };
@@ -504,8 +506,8 @@
pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>, pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
<&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>; <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
pinctrl-1 = <&qupv3_se8_spi_sleep>; pinctrl-1 = <&qupv3_se8_spi_sleep>;
dmas = <&gpi_dma2 0 0 1 64 0>, dmas = <&gpi_dma2 0 0 1 64 2>,
<&gpi_dma2 1 0 1 64 0>; <&gpi_dma2 1 0 1 64 2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
status = "disabled"; status = "disabled";

162
qcom/kera-vm.dtsi
View File

@@ -71,6 +71,9 @@
vm-attrs = "context-dump", "crash-restart"; vm-attrs = "context-dump", "crash-restart";
iomemory-ranges = <0x0 0xa24000 0x0 0xa24000 0x0 0x4000 0x0
0x0 0x824000 0x0 0x824000 0x0 0x4000 0x0>;
/* For LEVM por usecases is QUP1_SE4 and QUP2_SE7. /* For LEVM por usecases is QUP1_SE4 and QUP2_SE7.
* QUP1_SE4: GPII5 : IRQ_316 * QUP1_SE4: GPII5 : IRQ_316
* QUP2_SE7: GPII5 : IRQ_625 * QUP2_SE7: GPII5 : IRQ_625
@@ -250,6 +253,165 @@
qcom,custom-bridge-size = <64>; qcom,custom-bridge-size = <64>;
qcom,support-hypervisor; qcom,support-hypervisor;
}; };
/*
* QUP1 : SE0 - Secondary touch
* QUP2 : SE0 - Primary touch
*/
qup_iommu_group: qup_common_iommu_group {
iommu-addresses = <&gpi_dma1 0x00000000 0x00020000>,
<&qupv3_1 0x00000000 0x00020000>,
<&gpi_dma2 0x00000000 0x00020000>,
<&qupv3_2 0x00000000 0x00020000>;
};
/* GPI Instance */
gpi_dma1: qcom,gpi-dma@a00000 {
compatible = "qcom,gpi-dma";
reg = <0xa00000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_1 wrapper instance */
qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0xac0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0xb8 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Secondary Tounch */
qupv3_se0_i2c: i2c@a80000 {
compatible = "qcom,i2c-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma1 0 0 3 64 0xc>,
<&gpi_dma1 1 0 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Secondary Touch */
qupv3_se0_spi: spi@a80000 {
compatible = "qcom,spi-geni";
reg = <0xa80000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma1 0 0 1 64 0xc>,
<&gpi_dma1 1 0 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
/* GPI Instance */
gpi_dma2: qcom,gpi-dma@800000 {
compatible = "qcom,gpi-dma";
reg = <0x800000 0x60000>;
#dma-cells = <5>;
reg-names = "gpi-top";
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,static-gpii-mask = <0x20>;
qcom,gpii-mask = <0x0>;
qcom,ev-factor = <1>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* QUPv3_2 wrapper instance */
qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x8c0000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
iommus = <&apps_smmu 0x438 0x0>;
qcom,iommu-group = <&qup_iommu_group>;
dma-coherent;
ranges;
status = "ok";
/* Touchscreen I2C Instance */
qupv3_se8_i2c: i2c@880000 {
compatible = "qcom,i2c-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma2 0 0 3 64 0xc>,
<&gpi_dma2 1 0 3 64 0xc>;
dma-names = "tx", "rx";
qcom,le-vm;
status = "disabled";
};
/* Touchscreen SPI Instance */
qupv3_se8_spi: spi@880000 {
compatible = "qcom,spi-geni";
reg = <0x880000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "se_phys";
dmas = <&gpi_dma2 0 0 1 64 0xc>,
<&gpi_dma2 1 0 1 64 0xc>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,le-vm;
status = "disabled";
};
};
}; };
#include "msm-arm-smmu-kera-vm.dtsi" #include "msm-arm-smmu-kera-vm.dtsi"