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ARM: dts: msm: Update gpucc node as GenPD provider

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Mark gpucc clock node as GenPD provider and disable the
graphics GDSC regulator nodes.
While at it, keep the gdsc's as it is on rumi platform.

Change-Id: I91b4915723e26685e950de3ae575540ac3940036
Signed-off-by: Anaadi Mishra <quic_anaadim@quicinc.com>
This commit is contained in:
Anaadi Mishra
2024-08-28 14:16:14 +05:30
committed by Vishvanath Singh
parent 1e24f978b0
commit 0bc5f86b8c
2 changed files with 12 additions and 2 deletions
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8
qcom/kera-rumi.dtsi
View File

@@ -180,3 +180,11 @@
&disp_cc_mdss_core_int2_gdsc { &disp_cc_mdss_core_int2_gdsc {
status = "ok"; status = "ok";
}; };
&gpu_cc_cx_gdsc {
status = "ok";
};
&gpu_cc_gx_gdsc {
status = "ok";
};

6
qcom/kera.dtsi
View File

@@ -1849,14 +1849,18 @@
reg-name = "cc_base"; reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mx-supply = <&VDD_MX_LEVEL>;
vdd_gx-supply = <&VDD_GFX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
clock-names = "bi_tcxo", clock-names = "bi_tcxo",
"bi_tcxo_ao",
"gpll0_out_main", "gpll0_out_main",
"gpll0_out_main_div"; "gpll0_out_main_div";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
#power-domain-cells = <1>;
}; };
tcsrcc: clock-controller@1f40000 { tcsrcc: clock-controller@1f40000 {
@@ -3220,14 +3224,12 @@
parent-supply = <&VDD_CX_LEVEL>; parent-supply = <&VDD_CX_LEVEL>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk"; clock-names = "ahb_clk";
status = "ok";
}; };
&gpu_cc_gx_gdsc { &gpu_cc_gx_gdsc {
parent-supply = <&VDD_GFX_LEVEL>; parent-supply = <&VDD_GFX_LEVEL>;
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk"; clock-names = "ahb_clk";
status = "ok";
}; };
&video_cc_mvs0_gdsc { &video_cc_mvs0_gdsc {