From 0a6dffcb0d7a3bbbb7e59386427b0f99002714e6 Mon Sep 17 00:00:00 2001
From: Melody Olvera <quic_molvera@quicinc.com>
Date: Wed, 19 Apr 2023 14:29:14 -0700
Subject: [PATCH] ARM: dts: msm: Update cpu ids, spin-table region, timer
 interrupts

Update cpu ids, spin-table region, and timer interrupts on sun
to enable multicore boot.

Change-Id: Ibc25a86992dddc997c58e8e10a749b3c79731244
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
 qcom/sun-rumi.dtsi |  4 ++--
 qcom/sun.dtsi      | 10 +++++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/qcom/sun-rumi.dtsi b/qcom/sun-rumi.dtsi
index 043b4c0f..104b0371 100644
--- a/qcom/sun-rumi.dtsi
+++ b/qcom/sun-rumi.dtsi
@@ -4,9 +4,9 @@
  */
 
 &reserved_memory {
-	spintable: spintable_region@e3940000 {
+	spintable: spintable_region@90000000 {
 		no-map;
-		reg = <0x0 0xe3940000 0x0 0x100000>;
+		reg = <0x0 0x90000000 0x0 0x100000>;
 	};
 };
 
diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi
index 99126f11..0d59c70e 100644
--- a/qcom/sun.dtsi
+++ b/qcom/sun.dtsi
@@ -84,10 +84,10 @@
 			next-level-cache = <&L2_0>;
 		};
 
-		CPU6: cpu@600 {
+		CPU6: cpu@10000 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
-			reg = <0x0 0x600>;
+			reg = <0x0 0x10000>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_6>;
@@ -97,10 +97,10 @@
 			};
 		};
 
-		CPU7: cpu@700 {
+		CPU7: cpu@10100 {
 			device_type = "cpu";
 			compatible = "arm,armv8";
-			reg = <0x0 0x700>;
+			reg = <0x0 0x10100>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x90000000>;
 			next-level-cache = <&L2_6>;
@@ -231,7 +231,7 @@
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 		clock-frequency = <19200000>;
 	};
 };