diff --git a/qcom/sun-cdp.dtsi b/qcom/sun-cdp.dtsi index 290fbdac..72a073c1 100644 --- a/qcom/sun-cdp.dtsi +++ b/qcom/sun-cdp.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include "sun-pmic-overlay.dtsi" @@ -107,3 +108,52 @@ periph-d45-supply = <&L6N>; periph-d46-supply = <&L7N>; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-sun"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6j_l1>; + vdda-phy-max-microamp = <213000>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8g_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8i_l3>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v8d_l1>; + vccq-max-microamp = <1200000>; + + /* UFS Rst pin is always on. It is shared with VDD_PX14 */ + qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v8i_s7>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; diff --git a/qcom/sun-mtp.dtsi b/qcom/sun-mtp.dtsi index 6738e922..faefff83 100644 --- a/qcom/sun-mtp.dtsi +++ b/qcom/sun-mtp.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include "sun-pmic-overlay.dtsi" @@ -107,3 +108,52 @@ periph-d45-supply = <&L6N>; periph-d46-supply = <&L7N>; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-sun"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6j_l1>; + vdda-phy-max-microamp = <213000>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8g_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8i_l3>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v8d_l1>; + vccq-max-microamp = <1200000>; + + /* UFS Rst pin is always on. It is shared with VDD_PX14 */ + qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v8i_s7>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; diff --git a/qcom/sun-qrd.dtsi b/qcom/sun-qrd.dtsi index 6738e922..faefff83 100644 --- a/qcom/sun-qrd.dtsi +++ b/qcom/sun-qrd.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include "sun-pmic-overlay.dtsi" @@ -107,3 +108,52 @@ periph-d45-supply = <&L6N>; periph-d46-supply = <&L7N>; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-sun"; + + /* VDDA_UFS_CORE */ + vdda-phy-supply = <&pm_v6j_l1>; + vdda-phy-max-microamp = <213000>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; + + /* VDDA_UFS_0_1P2 */ + vdda-pll-supply = <&pm_v8g_l3>; + vdda-pll-max-microamp = <18300>; + + /* Phy GDSC for VDD_MX, always on */ + vdd-phy-gdsc-supply = <&gcc_ufs_mem_phy_gdsc>; + + /* Qref power supply, Refer Qref diagram */ + vdda-qref-supply = <&pm_v8i_l3>; + vdda-qref-max-microamp = <64500>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + + vcc-supply = <&pm_humu_l17>; + vcc-max-microamp = <1300000>; + + vccq-supply = <&pm_v8d_l1>; + vccq-max-microamp = <1200000>; + + /* UFS Rst pin is always on. It is shared with VDD_PX14 */ + qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,vccq-parent-supply = <&pm_v8i_s7>; + qcom,vccq-parent-max-microamp = <210000>; + + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + status = "ok"; +}; diff --git a/qcom/sun-rumi.dtsi b/qcom/sun-rumi.dtsi index e95a486c..130503bd 100644 --- a/qcom/sun-rumi.dtsi +++ b/qcom/sun-rumi.dtsi @@ -130,7 +130,12 @@ /* VDDA_UFS_CORE */ vdda-phy-supply = <&pm_v6j_l1>; - vdda-phy-max-microamp = <211000>; + vdda-phy-max-microamp = <213000>; + /* + * Platforms supporting Gear 5 && Rate B require a different + * voltage supply. Check the Power Grid document. + */ + vdda-phy-min-microvolt = <912000>; /* VDDA_UFS_0_1P2 */ vdda-pll-supply = <&pm_v8g_l3>; @@ -159,16 +164,18 @@ vcc-max-microamp = <1300000>; vccq-supply = <&pm_v8d_l1>; - vccq-max-microamp = <750000>; + vccq-max-microamp = <1200000>; + /* UFS Rst pin is always on. It is shared with VDD_PX14 */ qcom,vddp-ref-clk-supply = <&pm_v8i_l2>; qcom,vddp-ref-clk-max-microamp = <100>; qcom,vccq-parent-supply = <&pm_v8i_s7>; qcom,vccq-parent-max-microamp = <210000>; - vdda-qref-supply = <&pm_v8i_l3>; - vdda-qref-max-microamp = <30000>; + reset-gpios = <&tlmm 215 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; clock-names = "core_clk", diff --git a/qcom/sun.dtsi b/qcom/sun.dtsi index 57be73f9..c4fcba36 100644 --- a/qcom/sun.dtsi +++ b/qcom/sun.dtsi @@ -1512,6 +1512,7 @@ "MAX"; iommus = <&apps_smmu 0x60 0x0>; + qcom,iommu-dma = "fastmap"; shared-ice-cfg = <&ice_cfg>; qcom,bypass-pbl-rst-wa;