diff --git a/qcom/kera-rumi.dtsi b/qcom/kera-rumi.dtsi index 4a1f5de8..d4f43acc 100644 --- a/qcom/kera-rumi.dtsi +++ b/qcom/kera-rumi.dtsi @@ -19,10 +19,6 @@ }; &soc { - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - usb_emuphy: phy@a784000 { compatible = "qcom,usb-emu-phy"; reg = <0x0a784000 0x9500>; diff --git a/qcom/kera-usb.dtsi b/qcom/kera-usb.dtsi index d6d689be..60032b6f 100644 --- a/qcom/kera-usb.dtsi +++ b/qcom/kera-usb.dtsi @@ -3,14 +3,19 @@ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ +#include +#include + &soc { usb0: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; - reg = <0xa600000 0x100000>; - reg-names = "core_base"; + reg = <0xa600000 0x100000>, + <0x1fc6000 0x4>; + reg-names = "core_base", + "tcsr_dyn_en_dis"; - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; ranges; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; @@ -25,23 +30,50 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + qcom,dis-sending-cm-l1-quirk; qcom,core-clk-rate = <200000000>; qcom,core-clk-rate-hs = <66666667>; qcom,core-clk-rate-disconnected = <133333333>; - dwc3@a600000 { + qcom,use-pdc-interrupts; + qcom,use-eusb2-phy; + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>; + + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + + dummy-supply = <&apps_smmu>; + + + dwc3_0: dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xd93c>; + reg = <0x0 0xa600000 0x0 0xd93c>; iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "atomic"; - qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>; + memory-region = <&dwc3_mem_region>; dma-coherent; interrupts = ; + usb-phy = <&usb_nop_phy>, <&usb_qmp_dp_phy>; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; @@ -51,10 +83,261 @@ snps,dis_u2_susphy_quirk; snps,ssp-u3-u0-quirk; tx-fifo-resize; - dr_mode = "otg"; - maximum-speed = "high-speed"; + dr_mode = "peripheral"; + maximum-speed = "super-speed-plus"; usb-role-switch; }; }; -}; + dwc3_mem_region: dwc3_mem_region { + iommu-addresses = <&dwc3_0 0x0 0x0 0x0 0x90000000>, + <&dwc3_0 0x0 0xf0000000 0xffffffff 0x10000000>; + }; + + /* USB port related High Speed PHY */ + eusb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-snps-eusb2-phy"; + reg = <0x88e3000 0x154>, + <0x088e2000 0x4>, + <0x0c278000 0x4>; + reg-names = "eusb2_phy_base", + "eud_enable_reg", + "eud_detect_reg"; + + vdd-supply = <&L7K>; + qcom,vdd-voltage-level = <0 880000 880000>; + vdda12-supply = <&L4B>; + + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7K>; + qcom,vdd-voltage-level = <0 880000 880000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L4B>; + + usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>; + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_PAD_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "ref_clk", "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* based on tsmcn3e_USB3_Gen2_Seq v1.6 */ + + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x100b 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xb>; + qcom,usb-audio-intr-num = <2>; + }; + +};