From 0289936a74e1f6e70213ae3b8ebe09e79530f799 Mon Sep 17 00:00:00 2001
From: Lingutla Chandrasekhar <quic_lingutla@quicinc.com>
Date: Tue, 23 Jul 2024 16:03:11 -0700
Subject: [PATCH] dt-bindings: soc: add qcom,cpucp_fast documentation

Add documentation for the device qcom,cpucp_fast, which is used
for handling system hints from firmware.

Change-Id: I2336051df317d09d5224244e2d8248242980cc18
Signed-off-by: Lingutla Chandrasekhar <quic_lingutla@quicinc.com>
---
 bindings/soc/qcom/qcom,cpucp_fast.yaml | 43 ++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 bindings/soc/qcom/qcom,cpucp_fast.yaml

diff --git a/bindings/soc/qcom/qcom,cpucp_fast.yaml b/bindings/soc/qcom/qcom,cpucp_fast.yaml
new file mode 100644
index 00000000..7269c4cc
--- /dev/null
+++ b/bindings/soc/qcom/qcom,cpucp_fast.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,cpucp_fast.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. CPUCP FAST driver
+
+maintainers:
+  - Chandrasekhar Lingutla <quic_lingutla@quicinc.com>
+
+description: |
+  This device listens interrupts from CPUCP via mailbox and
+  sends notification to scheduler.
+
+properties:
+  compatible:
+    const: qcom,cpucp_fast
+
+  mboxes:
+    description: Mailboxes used for Interrupt from CPUCP
+
+  qcom,policy-cpus:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description: Base CPU index for cpufreq policy
+
+required:
+  - compatible
+  - mboxes
+  - qcom,policy-cpus
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      cpucp_fast: qcom,cpucp_fast {
+        compatible = "qcom,cpucp_fast";
+        mboxes = <&cpucp 5>;
+        qcom,policy-cpus = <6>;
+      };
+    };
+...