// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 */

#include <dt-bindings/clock/qcom,gcc-pineapple.h>
#include <dt-bindings/gpio/gpio.h>

&soc {
	pcie0: pcie@1c00000 {
		compatible = "qcom,pci-msm";
		device_type = "pci";

		reg = <0x01c00000 0x3000>,
			<0x01c06000 0x2000>,
			<0x60000000 0xf1d>,
			<0x60000f20 0xa8>,
			<0x60001000 0x1000>,
			<0x60100000 0x100000>,
			<0x01D07000 0x7000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
				"pcie_sm";

		cell-index = <0>;
		linux,pci-domain = <0>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
				"int_d";

		msi-map = <0x0 &gic_its 0x1400 0x1>,
			<0x100 &gic_its 0x1401 0x1>; /* 32 event IDs */

		qcom,pcie-clkreq-pin = <95>;
		perst-gpio = <&tlmm 94 GPIO_ACTIVE_HIGH>;
		wake-gpio = <&tlmm 96 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pcie0_perst_default
				&pcie0_clkreq_default
				&pcie0_wake_default>;
		pinctrl-1 = <&pcie0_perst_default
				&pcie0_clkreq_sleep
				&pcie0_wake_default>;

		qcom,bw-scale = /* Gen1 */
				<RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen2 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen3 */
				RPMH_REGULATOR_LEVEL_NOM
				RPMH_REGULATOR_LEVEL_NOM
				100000000>;

		interconnect-names = "icc_path";
		interconnects = <&pcie_noc MASTER_PCIE_0_PCIE_CRM_HW_0
				&mc_virt SLAVE_EBI1_PCIE_CRM_HW_0>;

		gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
		clocks = <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
		clock-names = "gcc_cnoc_pcie_sf_axi_clk";
		qcom,pcie-clock-frequency = <0>;
		clock-suppressible = <1>;

		resets = <&gcc GCC_PCIE_0_BCR>,
			<&gcc GCC_PCIE_0_PHY_BCR>;
		reset-names = "pcie_0_core_reset",
				"pcie_0_phy_reset";

		dma-coherent;
		qcom,smmu-sid-base = <0x1400>;
		iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
			<0x100 &apps_smmu 0x1401 0x1>;

		qcom,boot-option = <0x1>;
		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
		qcom,drv-supported;
		qcom,drv-l1ss-timeout-us = <5000>;
		qcom,l1-2-th-scale = <2>;
		qcom,l1-2-th-value = <150>;
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;

		qcom,pcie-phy-ver = <104>;
		qcom,phy-status-offset = <0x214>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x240>;

		qcom,phy-sequence = <0x0240 0x03 0x0
				0x00c0 0x01 0x0
				0x00cc 0x62 0x0
				0x00d0 0x02 0x0
				0x0060 0xf8 0x0
				0x0064 0x01 0x0
				0x0000 0x93 0x0
				0x0004 0x01 0x0
				0x00e0 0x90 0x0
				0x00e4 0x82 0x0
				0x00f4 0x07 0x0
				0x0070 0x02 0x0
				0x0010 0x02 0x0
				0x0074 0x16 0x0
				0x0014 0x16 0x0
				0x0078 0x36 0x0
				0x0018 0x36 0x0
				0x0110 0x08 0x0
				0x00bc 0x0a 0x0
				0x0120 0x42 0x0
				0x0080 0x04 0x0
				0x0084 0x0d 0x0
				0x0020 0x0a 0x0
				0x0024 0x1a 0x0
				0x0088 0x41 0x0
				0x0028 0x34 0x0
				0x0090 0xab 0x0
				0x0094 0xaa 0x0
				0x0098 0x01 0x0
				0x0030 0x55 0x0
				0x0034 0x55 0x0
				0x0038 0x01 0x0
				0x0140 0x14 0x0
				0x0164 0x34 0x0
				0x003c 0x01 0x0
				0x001c 0x04 0x0
				0x0174 0x16 0x0
				0x01bc 0x0f 0x0
				0x0170 0xa0 0x0
				0x11a4 0x38 0x0
				0x10dc 0x11 0x0
				0x1160 0xbf 0x0
				0x1164 0xbf 0x0
				0x1168 0xb7 0x0
				0x116c 0xea 0x0
				0x115c 0x3f 0x0
				0x1174 0x5c 0x0
				0x1178 0x9c 0x0
				0x117c 0x1a 0x0
				0x1180 0x89 0x0
				0x1170 0xdc 0x0
				0x1188 0x94 0x0
				0x118c 0x5b 0x0
				0x1190 0x1a 0x0
				0x1194 0x89 0x0
				0x10cc 0x00 0x0
				0x1008 0x09 0x0
				0x1014 0x05 0x0
				0x104c 0x08 0x0
				0x1050 0x08 0x0
				0x10d8 0x0f 0x0
				0x1118 0x1c 0x0
				0x10f8 0x07 0x0
				0x11f8 0x08 0x0
				0x1600 0x00 0x0
				0x0e84 0x15 0x0
				0x0e90 0x3f 0x0
				0x0ee4 0x02 0x0
				0x0e40 0x09 0x0
				0x0e3c 0x15 0x0
				0x19a4 0x38 0x0
				0x18dc 0x11 0x0
				0x1960 0xbf 0x0
				0x1964 0xbf 0x0
				0x1968 0xb7 0x0
				0x196c 0xea 0x0
				0x195c 0x3f 0x0
				0x1974 0x5c 0x0
				0x1978 0x9c 0x0
				0x197c 0x1a 0x0
				0x1980 0x89 0x0
				0x1970 0xdc 0x0
				0x1988 0x94 0x0
				0x198c 0x5b 0x0
				0x1990 0x1a 0x0
				0x1994 0x89 0x0
				0x18cc 0x00 0x0
				0x1808 0x09 0x0
				0x1814 0x05 0x0
				0x184c 0x08 0x0
				0x1850 0x08 0x0
				0x18d8 0x0f 0x0
				0x1918 0x1c 0x0
				0x18f8 0x07 0x0
				0x19f8 0x08 0x0
				0x1684 0x15 0x0
				0x1690 0x3f 0x0
				0x16e4 0x02 0x0
				0x1640 0x09 0x0
				0x163c 0x15 0x0
				0x02dc 0x05 0x0
				0x0388 0x77 0x0
				0x0398 0x0b 0x0
				0x06a4 0x1e 0x0
				0x06f4 0x27 0x0
				0x03e0 0x0f 0x0
				0x060c 0x1d 0x0
				0x0614 0x07 0x0
				0x0620 0xc1 0x0
				0x0694 0x00 0x0
				0x03d0 0x8c 0x0
				0x0368 0x17 0x0
				0x0200 0x00 0x0
				0x0244 0x03 0x0>;

		qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
					0x04d0 0x04d4 0x03c0 0x0630 0x0230
					0x0000>;
		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
					0x0734 0x0738 0x073c>;
		qcom,phy-debug-reg = <0x01cc 0x01d0 0x01d4 0x01d8 0x01dc
					0x01e0 0x01e4 0x01f8 0x0ed0 0x16d0
					0x0edc 0x16dc 0x11e0 0x19e0 0x0a00
					0x1200 0x0a04 0x1204 0x0a08 0x1208
					0x0a0c 0x120c 0x0a10 0x1210 0x0a14
					0x1214 0x0a18 0x1218 0x0c20 0x1420
					0x0214 0x0218 0x021c 0x0220 0x0224
					0x0228 0x022c 0x0230 0x0234 0x0238
					0x023c 0x0600 0x0604>;

		qcom,pcie-sm-branch-offset = <0x1000>;
		qcom,pcie-sm-start-offset = <0x1090>;

		qcom,pcie-sm-seq = <0x1c018081>, <0x70074002>, <0x50028000>,
				<0x28007003>, <0x80804002>, <0x70021c01>,
				<0x18001802>, <0x70005000>, <0x10004000>,
				<0x80814002>, <0x18001c01>, <0x1c018080>,
				<0x0000100>;

		qcom,pcie-sm-branch-seq = <0x4>, <0x1c>, <0x24>, <0x2c>, <0x0>,
					<0x0>, <0x0>;

		qcom,pcie-sm-debug = <0x1040>,	/* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_VAL */
				<0x1048>,	/* PCIE_SMs_SEQ_OVERRIDE_PWR_CTRL_MASK */
				<0x1050>,	/* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_VAL */
				<0x1058>,	/* PCIE_SMs_SEQ_OVERRIDE_WAIT_EVENT_MASK */
				<0x1060>,	/* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_VAL */
				<0x1068>,	/* PCIE_SMs_SEQ_OVERRIDE_BR_EVENT_MASK */
				<0x1070>,	/* PCIE_SMs_SEQ_PWR_CTRL_STATUS */
				<0x1078>,	/* PCIE_SMs_SEQ_WAIT_EVENT_STATUS */
				<0x1080>,	/* PCIE_SMs_SEQ_BR_EVENT_STATUS */
				<0x1088>,	/* PCIE_SMs_SEQ_PC_VAL */
				<0x1090>,	/* PCIE_SMs_SEQ_START */
				<0x1094>,	/* PCIE_SMs_CLKREQ_GATE */
				<0x1098>,	/* PCIE_SMs_CLKREQ_UNGATE */
				<0x109C>;	/* PCIE_SMs_CLKREQ_GATE_REQ_STATUS */

		pcie0_rp: pcie0_rp {
			reg = <0 0 0 0 0>;
		};
	};

	pcie0_msi: qcom,pcie0_msi@0x17110040 {
		compatible = "qcom,pci-msi";
		msi-controller;
		reg = <0x17110040 0x0>;
		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
		status = "disabled";
	};

	pcie1: pcie@1c08000 {
		compatible = "qcom,pci-msm";
		device_type = "pci";

		reg = <0x01c08000 0x3000>,
			<0x01c0e000 0x2000>,
			<0x40000000 0xf1d>,
			<0x40000f20 0xa8>,
			<0x40001000 0x1000>,
			<0x40100000 0x100000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

		cell-index = <1>;
		linux,pci-domain = <1>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
			<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;

		interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
				GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
				"int_d";

		msi-map = <0x0 &gic_its 0x1480 0x1>,
			<0x100 &gic_its 0x1481 0x1>; /* 32 event IDs */

		perst-gpio = <&tlmm 97 0>;
		wake-gpio = <&tlmm 99 0>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pcie1_perst_default
				&pcie1_clkreq_default
				&pcie1_wake_default>;
		pinctrl-1 = <&pcie1_perst_default
				&pcie1_clkreq_sleep
				&pcie1_wake_default>;

		gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
		gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
		vreg-1p2-supply = <&pm_v8_l3>;
		vreg-0p9-supply = <&pm_v6e_l3>;
		vreg-qref-supply = <&pm_v8_l1>;
		vreg-cx-supply = <&VDD_CX_LEVEL>;
		vreg-mx-supply = <&VDD_MXA_LEVEL>;

		qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>;
		qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,vreg-qref-voltage-level = <880000 880000 25700>;
		qcom,bw-scale = /* Gen1 */
				<RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen2 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen3 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				100000000
				/* Gen4 */
				RPMH_REGULATOR_LEVEL_NOM
				RPMH_REGULATOR_LEVEL_NOM
				100000000>;

		interconnect-names = "icc_path";
		interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;

		clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_PCIE_1_AUX_CLK>,
			<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
			<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
			<&tcsrcc TCSR_PCIE_1_CLKREF_EN>,
			<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
			<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
			<&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>,
			<&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
			<&gcc GCC_CNOC_PCIE_SF_AXI_CLK>,
			<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
			<&pcie_1_pipe_clk>,
			<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
		clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
				"pcie_aux_clk", "pcie_cfg_ahb_clk",
				"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
				"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
				"pcie_rate_change_clk",
				"gcc_ddrss_pcie_sf_qtb_clk",
				"pcie_aggre_noc_axi_clk",
				"gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
				"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
		qcom,pcie-clock-frequency = <0>, <0>, <19200000>, <0>, <0>,
				<0>, <0>, <0>, <100000000>, <0>, <0>, <0>,
				<0>, <0>, <0>;

		clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
				<0>, <0>, <0>, <1>, <0>, <0>, <0>;

		resets = <&gcc GCC_PCIE_1_BCR>,
			<&gcc GCC_PCIE_1_PHY_BCR>,
			<&gcc GCC_PCIE_1_LINK_DOWN_BCR>,
			<&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>;
		reset-names = "pcie_1_core_reset",
				"pcie_1_phy_reset",
				"pcie_1_link_down_reset",
				"pcie_1_phy_nocsr_com_phy_reset";

		dma-coherent;
		qcom,smmu-sid-base = <0x1480>;
		iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
			<0x100 &apps_smmu 0x1481 0x1>;

		qcom,boot-option = <0x1>;
		qcom,aux-clk-freq = <17>; /* 16.6 MHz */
		qcom,drv-name = "lpass";
		qcom,drv-l1ss-timeout-us = <5000>;
		qcom,eq-fmdc-t-min-phase23 = <1>;
		qcom,slv-addr-space-size = <0x20000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;
		qcom,l1-2-th-scale = <2>;
		qcom,l1-2-th-value = <150>;

		qcom,pcie-clkreq-offset = <0x2c48>;

		qcom,pcie-phy-ver = <106>;
		qcom,phy-status-offset = <0x1214>;
		qcom,phy-status-bit = <7>;
		qcom,phy-power-down-offset = <0x1240>;

		qcom,phy-sequence = <0x1240 0x03 0x0
				0x0030 0x1d 0x0
				0x0034 0x03 0x0
				0x0078 0x01 0x0
				0x007c 0x00 0x0
				0x0080 0x51 0x0
				0x00ac 0x34 0x0
				0x0208 0x0c 0x0
				0x020c 0x0a 0x0
				0x0218 0x04 0x0
				0x0220 0x16 0x0
				0x0234 0x00 0x0
				0x029c 0x80 0x0
				0x02a0 0x7c 0x0
				0x02b4 0x05 0x0
				0x02e8 0x0a 0x0
				0x030c 0x0d 0x0
				0x0320 0x0b 0x0
				0x0348 0x1c 0x0
				0x0388 0x20 0x0
				0x0394 0x30 0x0
				0x03dc 0x09 0x0
				0x03f4 0x14 0x0
				0x03f8 0xb3 0x0
				0x03fc 0x58 0x0
				0x0400 0x9a 0x0
				0x0404 0x26 0x0
				0x0408 0xb6 0x0
				0x040c 0xee 0x0
				0x0410 0xdb 0x0
				0x0414 0xdb 0x0
				0x0418 0xa0 0x0
				0x041c 0xdf 0x0
				0x0420 0x78 0x0
				0x0424 0x76 0x0
				0x0428 0xff 0x0
				0x0830 0x1d 0x0
				0x0834 0x03 0x0
				0x0878 0x01 0x0
				0x087c 0x00 0x0
				0x0880 0x51 0x0
				0x08ac 0x34 0x0
				0x0a08 0x0c 0x0
				0x0a0c 0x0a 0x0
				0x0a18 0x04 0x0
				0x0a20 0x16 0x0
				0x0a34 0x00 0x0
				0x0a9c 0x80 0x0
				0x0aa0 0x7c 0x0
				0x0ab4 0x05 0x0
				0x0ae8 0x0a 0x0
				0x0b0c 0x0d 0x0
				0x0b20 0x0b 0x0
				0x0b48 0x1c 0x0
				0x0b88 0x20 0x0
				0x0b94 0x30 0x0
				0x0bdc 0x09 0x0
				0x0bf4 0x14 0x0
				0x0bf8 0xb3 0x0
				0x0bfc 0x58 0x0
				0x0c00 0x9a 0x0
				0x0c04 0x26 0x0
				0x0c08 0xb6 0x0
				0x0c0c 0xee 0x0
				0x0c10 0xdb 0x0
				0x0c14 0xdb 0x0
				0x0c18 0xa0 0x0
				0x0c1c 0xdf 0x0
				0x0c20 0x78 0x0
				0x0c24 0x76 0x0
				0x0c28 0xff 0x0
				0x0ea0 0x01 0x0
				0x0eb4 0x00 0x0
				0x0ec4 0x00 0x0
				0x0ec8 0x1f 0x0
				0x0ed4 0x12 0x0
				0x0ed8 0x12 0x0
				0x0edc 0xdb 0x0
				0x0ee0 0x9a 0x0
				0x0ee4 0x38 0x0
				0x0ee8 0xb6 0x0
				0x0eec 0x64 0x0
				0x0ef0 0x1f 0x0
				0x0ef4 0x1f 0x0
				0x0ef8 0x1f 0x0
				0x0efc 0x1f 0x0
				0x0f00 0x1f 0x0
				0x0f04 0x1f 0x0
				0x0f0c 0x1f 0x0
				0x0f14 0x1f 0x0
				0x0f1c 0x1f 0x0
				0x0f28 0x5b 0x0
				0x1000 0x26 0x0
				0x1004 0x03 0x0
				0x1010 0x06 0x0
				0x1014 0x16 0x0
				0x1018 0x36 0x0
				0x101c 0x04 0x0
				0x1020 0x0a 0x0
				0x1024 0x1a 0x0
				0x1028 0x68 0x0
				0x1030 0xab 0x0
				0x1034 0xaa 0x0
				0x1038 0x02 0x0
				0x103c 0x12 0x0
				0x1060 0xf8 0x0
				0x1064 0x01 0x0
				0x1070 0x06 0x0
				0x1074 0x16 0x0
				0x1078 0x36 0x0
				0x107c 0x0a 0x0
				0x1080 0x04 0x0
				0x1084 0x0d 0x0
				0x1088 0x41 0x0
				0x1090 0xab 0x0
				0x1094 0xaa 0x0
				0x1098 0x01 0x0
				0x109c 0x00 0x0
				0x10bc 0x0a 0x0
				0x10c0 0x01 0x0
				0x10cc 0x62 0x0
				0x10d0 0x02 0x0
				0x10d8 0x40 0x0
				0x10dc 0x14 0x0
				0x10e0 0x90 0x0
				0x10e4 0x82 0x0
				0x10f4 0x0f 0x0
				0x1110 0x08 0x0
				0x1120 0x46 0x0
				0x1124 0x04 0x0
				0x1140 0x14 0x0
				0x1164 0x34 0x0
				0x1170 0xa0 0x0
				0x1174 0x06 0x0
				0x1184 0x88 0x0
				0x1188 0x14 0x0
				0x1198 0x0f 0x0
				0x129c 0x87 0x0
				0x12a0 0x05 0x0
				0x12a4 0xa1 0x0
				0x1378 0x2e 0x0
				0x1390 0xcc 0x0
				0x13f8 0x00 0x0
				0x13fc 0x22 0x0
				0x141c 0xc1 0x0
				0x1450 0x0f 0x0
				0x1490 0x00 0x0
				0x14a0 0x16 0x0
				0x14f0 0x27 0x0
				0x14f4 0x27 0x0
				0x1508 0x02 0x0
				0x155c 0x2e 0x0
				0x157c 0x03 0x0
				0x1584 0x28 0x0
				0x13dc 0x04 0x0
				0x13e0 0x02 0x0
				0x1418 0xc0 0x0
				0x140c 0x1d 0x0
				0x158c 0x0f 0x0
				0x15ac 0xf2 0x0
				0x15c0 0xf2 0x0
				0x1370 0x17 0x0
				0x1200 0x00 0x0
				0x1244 0x03 0x0>;

		qcom,parf-debug-reg = <0x01b0 0x0024 0x0028 0x0224 0x0500
					0x04d0 0x04d4 0x03c0 0x0630 0x0230
					0x0000>;
		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01f4 0x0730
					0x0734 0x0738 0x073c>;
		qcom,phy-debug-reg = <0x11cc 0x11d0 0x11d4 0x11d8 0x11dc
					0x11e0 0x11e4 0x11f8 0x00b8 0x08b8
					0x00c4 0x08c4 0x0464 0x0c64 0x1800
					0x1c00 0x1804 0x1c04 0x1808 0x1c08
					0x180c 0x1c0c 0x1810 0x1c10 0x1814
					0x1c14 0x1818 0x1c18 0x1a20 0x1e20
					0x1214 0x1218 0x121c 0x1220 0x1224
					0x1228 0x122c 0x1230 0x1234 0x1238
					0x123c 0x1400 0x1404>;

		pcie1_rp: pcie1_rp {
			reg = <0 0 0 0 0>;
		};
	};
};
