# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/lvds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: LVDS Display Common Properties

maintainers:
  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
  - Thierry Reding <thierry.reding@gmail.com>

description: |+
  LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
  incompatible data link layers have been used over time to transmit image data
  to LVDS devices. This bindings supports devices compatible with the following
  specifications.

  [JEIDA] "Digital Interface Standards for Monitor", JEIDA-59-1999, February
  1999 (Version 1.0), Japan Electronic Industry Development Association (JEIDA)
  [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
  Semiconductor
  [VESA] "VESA Notebook Panel Standard", October 2007 (Version 1.0), Video
  Electronics Standards Association (VESA)

  Device compatible with those specifications have been marketed under the
  FPD-Link and FlatLink brands.

properties:
  data-mapping:
    enum:
      - jeida-18
      - jeida-24
      - vesa-24
    description: |
      The color signals mapping order.

      LVDS data mappings are defined as follows.

      - "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
        [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><

      - "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
        specifications. Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
      DATA1     ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
      DATA3     ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><

      - "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
        Data are transferred as follows on 4 LVDS lanes.

      Slot          0       1       2       3       4       5       6
                ________________                         _________________
      Clock                     \_______________________/
                  ______  ______  ______  ______  ______  ______  ______
      DATA0     ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
      DATA1     ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
      DATA2     ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
      DATA3     ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><

      Control signals are mapped as follows.

      CTL0: HSync
      CTL1: VSync
      CTL2: Data Enable
      CTL3: 0

  data-mirror:
    type: boolean
    description:
      If set, reverse the bit order described in the data mappings below on all
      data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.

additionalProperties: true

...
