# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i3c/qcom,i3c-master-msm-geni.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies Inc.'s GENI based I3C controller

maintainers:
  - Mukesh Savaliya <quic_msavaliy@quicinc.com>

description:
  I3C busses can be described with a node for the primary I3C controller device
  and a set of child nodes for each I2C or I3C slave on the bus. Each of them
  may, during the life of the bus, request mastership.

allOf:
  - $ref: i3c.yaml#

properties:
  compatible:
    const: qcom,geni-i3c

  clocks:
    maxItems: 1

  clock-names:
    const: se-clk

  pinctrl-0: true
  pinctrl-1: true

  pinctrl-names:
    minItems: 1
    items:
      - const: default
      - const: sleep

  dmas:
    maxItems: 2

  dma-names:
    items:
      - const: tx
      - const: rx

  interconnects:
    minItems: 2
    maxItems: 3

  interconnect-names:
    minItems: 2
    items:
      - const: qup-core
      - const: qup-config
      - const: qup-memory

  interrupts:
    maxItems: 1

  reg:
    maxItems: 1

  reg-names:
    maxItems: 1

  qcom,ibi-ctrl-id:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - interrupts
  - pinctrl-names
  - qcom,ibi-ctrl-id

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-sun.h>
    #include <dt-bindings/interconnect/qcom,sun.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    i3c0: i3c-master@a80000 {
       compatible = "qcom,geni-i3c";
       reg = <0xa80000 0x4000>,
         <0xec90000 0x10000>;
       clock-names = "se-clk";
       clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
       interconnect-names = "qup-core", "qup-config", "qup-memory";
       interconnects =
       <&clk_virt MASTER_QUP_CORE_1 &clk_virt SLAVE_QUP_CORE_1>,
       <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
       <&aggre1_noc MASTER_QUP_1 &mc_virt  SLAVE_EBI1>;
       pinctrl-names = "default", "sleep", "disable";
       pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>;
       pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>;
       pinctrl-2 = <&qupv3_se0_i3c_disable>;
       interrupts-extended = <&intc GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
         <&pdc 31 IRQ_TYPE_LEVEL_HIGH>,
         <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
       #address-cells = <3>;
       #size-cells = <0>;
       qcom,ibi-ctrl-id = <0>;
   };

...
