# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sun.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Global Clock & Reset Controller

maintainers:
  - Xubin Bai <quic_xubibai@quicinc.com>

description: |
  Global clock control module which supports the clocks, resets and
  power domains on SUN

  See also:
  - dt-bindings/clock/qcom,gcc-sun.h
  - dt-bindings/clock/qcom,gcc-tuna.h

properties:
  compatible:
    enum:
      - qcom,gcc-sun
      - qcom,tuna-gcc
      - qcom,kera-gcc
      - qcom,tuna-gcc-v1

  clocks:
    items:
      - description: Board XO source
      - description: Sleep clock source
      - description: PCIE 0 Pipe clock source (Optional clock)
      - description: UFS Phy Rx symbol 0 clock source (Optional clock)
      - description: UFS Phy Rx symbol 1 clock source (Optional clock)
      - description: UFS Phy Tx symbol 0 clock source (Optional clock)
      - description: USB3 Phy wrapper pipe clock source (Optional clock)
    minItems: 2

  clock-names:
    items:
      - const: bi_tcxo
      - const: sleep_clk
      - const: pcie_0_pipe_clk # Optional clock
      - const: ufs_phy_rx_symbol_0_clk # Optional clock
      - const: ufs_phy_rx_symbol_1_clk # Optional clock
      - const: ufs_phy_tx_symbol_0_clk # Optional clock
      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
    minItems: 2

  vdd_cx-supply:
    description: Phandle pointer to the vdd_cx logic rail supply

  vdd_mx-supply:
    description: Phandle pointer to the vdd_mx logic rail supply

required:
  - compatible
  - clocks
  - clock-names

allOf:
  - $ref: "qcom,gcc.yaml#"

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    clock-controller@100000 {
      compatible = "qcom,sun-gcc", "syscon";
      reg = <0x100000 0x1f4200>;
      reg-name = "cc_base";
      vdd_cx-supply = <&VDD_CX_LEVEL>;
      vdd_mx-supply = <&VDD_MX_LEVEL>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
        <&pcie_0_pipe_clk>,
        <&sleep_clk>,
        <&ufs_phy_rx_symbol_0_clk>,
        <&ufs_phy_rx_symbol_1_clk>,
        <&ufs_phy_tx_symbol_0_clk>,
        <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
      clock-names = "bi_tcxo",
        "pcie_0_pipe_clk",
        "sleep_clk",
        "ufs_phy_rx_symbol_0_clk",
        "ufs_phy_rx_symbol_1_clk",
        "ufs_phy_tx_symbol_0_clk",
        "usb3_phy_wrapper_gcc_usb30_pipe_clk";
      #clock-cells = <1>;
      #reset-cells = <1>;
    };

...
