# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,dispcc-monaco.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. Display Clock & Reset Controller

maintainers:
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm Technologies, Inc. display clock control module which supports the clocks and
  power domains on Monaco.

  See also:
    dt-bindings/clock/qcom,dispcc-monaco.h

properties:
  compatible:
    enum:
      - qcom,monaco-dispcc

  clocks:
    items:
      - description: Brard XO source
      - description: Brard XO_AO source
      - description: Sleep clock source
      - description: GPLL0 OUT MAIN clock source

  clock-names:
    items:
      - const: bi_tcxo
      - const: bi_tcxo_ao
      - const: sleep_clk
      - const: gpll0_out_main

  vdd_cx-supply:
    description: Phandle pointer to the vdd_cx logic rail supply

  vdd_mxa-supply:
    description: Phandle pointer to the vdd_mxa logic rail supply

  '#clock-cells':
    const: 1

  reg:
    maxItems: 1

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/clock/qcom,gcc-monaco.h>
        dispcc: clock-controller@5f00000 {
                compatible = "qcom,monaco-dispcc", "syscon";
                reg = <0x05f00000 0x20000>;
                reg-names = "cc_base";
                clock-names = "bi_tcxo", "bi_tcxo_ao", "gpll0_out_main",
                              "sleep_clk";
                clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
                         <&gcc GPLL0>, <&sleep_clk>;
                vdd_cx-supply = <&VDD_CX_LEVEL>;
                #clock-cells = <1>;
                #reset-cells = <1>;
        };
...
