# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DPU dt properties for SDM845 target

maintainers:
  - Krishna Manikandan <quic_mkrishn@quicinc.com>

description: |
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
  bindings of MDSS and DPU are mentioned for SDM845 target.

properties:
  compatible:
    items:
      - const: qcom,sdm845-mdss

  reg:
    maxItems: 1

  reg-names:
    const: mdss

  power-domains:
    maxItems: 1

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display core clock

  clock-names:
    items:
      - const: iface
      - const: core

  interrupts:
    maxItems: 1

  interrupt-controller: true

  "#address-cells": true

  "#size-cells": true

  "#interrupt-cells":
    const: 1

  iommus:
    items:
      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
      - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1

  ranges: true

  resets:
    items:
      - description: MDSS_CORE reset

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    description: Node containing the properties of DPU.
    additionalProperties: false

    properties:
      compatible:
        items:
          - const: qcom,sdm845-dpu

      reg:
        items:
          - description: Address offset and size for mdp register set
          - description: Address offset and size for vbif register set

      reg-names:
        items:
          - const: mdp
          - const: vbif

      clocks:
        items:
          - description: Display ahb clock
          - description: Display axi clock
          - description: Display core clock
          - description: Display vsync clock

      clock-names:
        items:
          - const: iface
          - const: bus
          - const: core
          - const: vsync

      interrupts:
        maxItems: 1

      power-domains:
        maxItems: 1

      operating-points-v2: true
      opp-table:
        type: object

      ports:
        $ref: /schemas/graph.yaml#/properties/ports
        description: |
          Contains the list of output ports from DPU device. These ports
          connect to interfaces that are external to the DPU hardware,
          such as DSI, DP etc. Each output port contains an endpoint that
          describes how it is connected to an external interface.

        properties:
          port@0:
            $ref: /schemas/graph.yaml#/properties/port
            description: DPU_INTF1 (DSI1)

          port@1:
            $ref: /schemas/graph.yaml#/properties/port
            description: DPU_INTF2 (DSI2)

        required:
          - port@0
          - port@1

    required:
      - compatible
      - reg
      - reg-names
      - clocks
      - interrupts
      - power-domains
      - operating-points-v2
      - ports

required:
  - compatible
  - reg
  - reg-names
  - power-domains
  - clocks
  - interrupts
  - interrupt-controller
  - iommus
  - ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@ae00000 {
          #address-cells = <1>;
          #size-cells = <1>;
          compatible = "qcom,sdm845-mdss";
          reg = <0x0ae00000 0x1000>;
          reg-names = "mdss";
          power-domains = <&dispcc MDSS_GDSC>;

          clocks = <&gcc GCC_DISP_AHB_CLK>,
                   <&dispcc DISP_CC_MDSS_MDP_CLK>;
          clock-names = "iface", "core";

          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
          interrupt-controller;
          #interrupt-cells = <1>;

          iommus = <&apps_smmu 0x880 0x8>,
                   <&apps_smmu 0xc80 0x8>;
          ranges;

          display-controller@ae01000 {
                    compatible = "qcom,sdm845-dpu";
                    reg = <0x0ae01000 0x8f000>,
                          <0x0aeb0000 0x2008>;
                    reg-names = "mdp", "vbif";

                    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                             <&dispcc DISP_CC_MDSS_AXI_CLK>,
                             <&dispcc DISP_CC_MDSS_MDP_CLK>,
                             <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
                    clock-names = "iface", "bus", "core", "vsync";

                    interrupt-parent = <&mdss>;
                    interrupts = <0>;
                    power-domains = <&rpmhpd SDM845_CX>;
                    operating-points-v2 = <&mdp_opp_table>;

                    ports {
                           #address-cells = <1>;
                           #size-cells = <0>;

                           port@0 {
                                   reg = <0>;
                                   dpu_intf1_out: endpoint {
                                                  remote-endpoint = <&dsi0_in>;
                                   };
                           };

                           port@1 {
                                   reg = <1>;
                                   dpu_intf2_out: endpoint {
                                                  remote-endpoint = <&dsi1_in>;
                                   };
                           };
                    };
          };
    };
...
