# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,tuna-vm-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. SUN VM TLMM block

maintainers:
  - Murali Nalajala <quic_mnalajal@quicinc.com>
  - Satya Durga Srinivasu Prabhala <quic_satyap@quicinc.com>

description: |
  This binding describes the Top Level Mode Multiplexer block for VM.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,tuna-vm-tlmm

  reg:
    maxItems: 1

  interrupts-extended: true
  interrupt-controller: true
  '#interrupt-cells': true

  gpio-controller: true
  '#gpio-cells': true
  gpio-ranges: true
  gpios:
    description: array of gpio pin number required by VM TLMM clients

required:
  - compatible
  - reg

additionalProperties: false

patternProperties:
  '-state$':
    oneOf:
      - $ref: "#/$defs/qcom-tuna-vm-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-tuna-vm-tlmm-state"
        additionalProperties: false

$defs:
  qcom-tuna-vm-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ aoss_cti, atest_char0, atest_char1, atest_char2, atest_char3,
                atest_char_start, atest_usb0, atest_usb00, atest_usb01,
                atest_usb02, atest_usb03, audio_ext_mclk0, audio_ext_mclk1,
                audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, cam_mclk,
                cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c_scl0,
                cci_i2c_scl1, cci_i2c_scl2, cci_i2c_scl3, cci_i2c_scl4,
                cci_i2c_scl5, cci_i2c_sda0, cci_i2c_sda1, cci_i2c_sda2,
                cci_i2c_sda3, cci_i2c_sda4, cci_i2c_sda5, cci_timer0,
                cci_timer1, cci_timer2, cci_timer3, cci_timer4, cmu_rng0,
                cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1_rx, coex_uart1_tx,
                coex_uart2_rx, coex_uart2_tx, dbg_out_clk, ddr_bist_complete,
                ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
                ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2,
                gcc_gp3, gnss_adc0, gnss_adc1, gpio, i2chub0_se0_l0,
                i2chub0_se0_l1, i2chub0_se1_l0, i2chub0_se1_l1, i2chub0_se2_l0,
                i2chub0_se2_l1, i2chub0_se3_l0,i2chub0_se3_l1, i2chub0_se4_l0,
                i2chub0_se4_l1, i2chub0_se5_l0, i2chub0_se5_l1, i2chub0_se6_l0,
                i2chub0_se6_l1, i2chub0_se7_l0, i2chub0_se7_l1, i2chub0_se8_l0,
                i2chub0_se8_l1, i2chub0_se9_l0, i2chub0_se9_l1, i2s0_data0,
                i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck,
                i2s1_ws, ibi_i3c, jitter_bist, mdp_esync_0, mdp_esync_1,
                mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,
                mdp_vsync3_out, mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
                nav_gpio3, pcie0_clk_req_n, phase_flag0, phase_flag1,
                phase_flag10, phase_flag11, phase_flag12, phase_flag13,
                phase_flag14, phase_flag15, phase_flag16, phase_flag17,
                phase_flag18, phase_flag19, phase_flag2, phase_flag20,
                phase_flag21, phase_flag22, phase_flag23, phase_flag24,
                phase_flag25, phase_flag26, phase_flag27, phase_flag28,
                phase_flag29, phase_flag3, phase_flag30, phase_flag31,
                phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8,
                phase_flag9, pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
                prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
                qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
                qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
                qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
                qlink_big_enable, qlink_big_request, qlink_little_enable,
                qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3,
                qspi_clk, qspi_cs, qup1_se0_l0, qup1_se0_l1, qup1_se0_l2,
                qup1_se0_l3, qup1_se1_l0, qup1_se1_l1, qup1_se1_l2, qup1_se1_l3,
                qup1_se2_l0, qup1_se2_l1, qup1_se2_l2, qup1_se2_l3, qup1_se2_l4,
                qup1_se2_l5, qup1_se2_l6, qup1_se3_l0, qup1_se3_l1, qup1_se3_l2,
                qup1_se3_l3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, qup1_se4_l3,
                qup1_se5_l0, qup1_se5_l1, qup1_se5_l2, qup1_se5_l3, qup1_se6_l0,
                qup1_se6_l1, qup1_se6_l2, qup1_se6_l3, qup1_se7_l0, qup1_se7_l1,
                qup1_se7_l2, qup1_se7_l3, qup2_se0_l0, qup2_se0_l1, qup2_se0_l2,
                qup2_se0_l3, qup2_se1_l0, qup2_se1_l1, qup2_se1_l2, qup2_se1_l3,
                qup2_se2_l0, qup2_se2_l1, qup2_se2_l2, qup2_se2_l3, qup2_se2_l4,
                qup2_se2_l5, qup2_se2_l6, qup2_se3_l0, qup2_se3_l1, qup2_se3_l2,
                qup2_se3_l3, qup2_se4_l0, qup2_se4_l1, qup2_se4_l2, qup2_se4_l3,
                qup2_se5_l0, qup2_se5_l1, qup2_se5_l2, qup2_se5_l3, qup2_se5_l6,
                qup2_se6_l0, qup2_se6_l1, qup2_se6_l2, qup2_se6_l3, qup2_se7_l0,
                qup2_se7_l1, qup2_se7_l2, qup2_se7_l3, sd_write_protect, sdc40,
                sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2,
                tb_trig_sdc4, tmess_prng0, tmess_prng1, tmess_prng2,
                tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
                uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
                uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0,
                vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ]


      bias-disable: true
      bias-pull-down: true
      bias-pull-up: true
      drive-strength: true
      input-enable: true
      output-high: true
      output-low: true

    required:
      - pins

    allOf:
      - $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
      - if:
          properties:
            pins:
              pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
        then:
          required:
            - function

    additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    pinctrl@f100000 {
        compatible = "qcom,tuna-vm-tlmm";
        reg = <0x0f100000 0x300000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 211>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts-extended = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-state {
            rx-pins {
                pins = "gpio26";
                function = "qup1_se7_l0";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio27";
                function = "qup1_se7_l1";
                bias-disable;
            };
        };
    };
...
