# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. X1E80100 TLMM block

maintainers:
  - Rajendra Nayak <quic_rjendra@quicinc.com>

description:
  Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.

allOf:
  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#

properties:
  compatible:
    const: qcom,x1e80100-tlmm

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  interrupt-controller: true
  "#interrupt-cells": true
  gpio-controller: true

  gpio-reserved-ranges:
    minItems: 1
    maxItems: 119

  gpio-line-names:
    maxItems: 238

  "#gpio-cells": true
  gpio-ranges: true
  wakeup-parent: true

patternProperties:
  "-state$":
    oneOf:
      - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
      - patternProperties:
          "-pins$":
            $ref: "#/$defs/qcom-x1e80100-tlmm-state"
        additionalProperties: false

$defs:
  qcom-x1e80100-tlmm-state:
    type: object
    description:
      Pinctrl node's client devices use subnodes for desired pin configuration.
      Client device subnodes use below standard properties.
    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
    unevaluatedProperties: false

    properties:
      pins:
        description:
          List of gpio pins affected by the properties specified in this
          subnode.
        items:
          oneOf:
            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
        minItems: 1
        maxItems: 36

      function:
        description:
          Specify the alternative function to be configured for the specified
          pins.
        enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
                atest_char1, atest_char2, atest_char3, atest_usb,
                audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
                cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
                cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
                cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
                ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
                edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
                eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
                gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
                i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
                mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
                mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
                pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
                qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
                qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
                qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
                qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
                qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
                sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
                tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
                tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
                tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
                usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
                usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]

    required:
      - pins

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    tlmm: pinctrl@f100000 {
        compatible = "qcom,x1e80100-tlmm";
        reg = <0x0f100000 0xf00000>;
        gpio-controller;
        #gpio-cells = <2>;
        gpio-ranges = <&tlmm 0 0 239>;
        interrupt-controller;
        #interrupt-cells = <2>;
        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

        gpio-wo-state {
            pins = "gpio1";
            function = "gpio";
        };

        uart-w-state {
            rx-pins {
                pins = "gpio26";
                function = "qup2_se7";
                bias-pull-up;
            };

            tx-pins {
                pins = "gpio27";
                function = "qup2_se7";
                bias-disable;
            };
        };
    };
...
