LogicoreIP designed compatible with Xilinx ZYNQ family.
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General concept
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LogicoreIP design to provide the isolation between processing system
and programmable logic. Also provides the list of register set to configure
the frequency.

Required properties:
- compatible: shall be one of:
	"xlnx,vcu"
	"xlnx,vcu-logicoreip-1.0"
- reg : The base offset and size of the VCU_PL_SLCR register space.
- clocks: phandle for aclk and pll_ref clocksource
- clock-names: The identification string, "aclk", is always required for
   the axi clock. "pll_ref" is required for pll.
Example:

	xlnx_vcu: vcu@a0040000 {
		compatible = "xlnx,vcu-logicoreip-1.0";
		reg = <0x0 0xa0040000 0x0 0x1000>;
		clocks = <&si570_1>, <&clkc 71>;
		clock-names = "pll_ref", "aclk";
	};
