# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Last Level Cache Controller

maintainers:
  - Rishabh Bhatnagar <rishabhb@codeaurora.org>
  - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>

description: |
  LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
  that can be shared by multiple clients. Clients here are different cores in the
  SoC, the idea is to minimize the local caches at the clients and migrate to
  common pool of memory. Cache memory is divided into partitions called slices
  which are assigned to clients. Clients can query the slice details, activate
  and deactivate them.

properties:
  compatible:
    enum:
      - qcom,sc7180-llcc
      - qcom,sc7280-llcc
      - qcom,sc8180x-llcc
      - qcom,sc8280xp-llcc
      - qcom,sdm845-llcc
      - qcom,sm6350-llcc
      - qcom,sm8150-llcc
      - qcom,sm8250-llcc
      - qcom,sm8350-llcc
      - qcom,sm8450-llcc
      - qcom,sm8550-llcc
      - qcom,pineapple-llcc
      - qcom,sun-llcc

  reg:
    minItems: 2
    maxItems: 9

  reg-names:
    minItems: 2
    maxItems: 9

  interrupts:
    maxItems: 1

  child-node:
    description: Container of llcc_perfmon node
    type: object
    properties:
        compatible:
            const: qcom,llcc-perfmon
required:
  - compatible
  - reg
  - reg-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,pineapple-llcc
              - qcom,sun-llcc
    then:
      properties:
        reg:
          items:
            - description: LLCC0 base register region
            - description: LLCC1 base register region
            - description: LLCC2 base register region
            - description: LLCC3 base register region
            - description: LLCC broadcast base register region
        reg-names:
            items:
            - const: llcc0_base
            - const: llcc1_base
            - const: llcc2_base
            - const: llcc3_base
            - const: llcc_broadcast_base

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        system-cache-controller@1100000 {
            compatible = "qcom,sdm845-llcc";
            reg = <0x01100000 0x50000>, <0x01180000 0x50000>,
                <0x01200000 0x50000>, <0x01280000 0x50000>,
                <0x1300000 0x50000> ;
            reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
                "llcc3_base", "llcc_broadcast_base";
            interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

            llcc_perfmon {
                compatible = "qcom,llcc-perfmon";
            }
        };
    };
