# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2
---
$id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Mediatek Video Encode Accelerator

maintainers:
  - Yunfei Dong <yunfei.dong@mediatek.com>

description: |+
  Mediatek Video Encode is the video encode hardware present in Mediatek
  SoCs which supports high resolution encoding functionalities.

properties:
  compatible:
    enum:
      - mediatek,mt8173-vcodec-enc-vp8
      - mediatek,mt8173-vcodec-enc
      - mediatek,mt8183-vcodec-enc
      - mediatek,mt8188-vcodec-enc
      - mediatek,mt8192-vcodec-enc
      - mediatek,mt8195-vcodec-enc

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 1
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 5

  assigned-clocks: true

  assigned-clock-parents: true

  iommus:
    minItems: 1
    maxItems: 32
    description: |
      List of the hardware port in respective IOMMU block for current Socs.
      Refer to bindings/iommu/mediatek,iommu.yaml.

  dma-ranges:
    maxItems: 1
    description: |
      Describes the physical address space of IOMMU maps to memory.

  mediatek,vpu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to vpu.

  mediatek,scp:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Describes point to scp.

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - iommus
  - assigned-clocks
  - assigned-clock-parents

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8183-vcodec-enc
              - mediatek,mt8192-vcodec-enc

    then:
      required:
        - mediatek,scp

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8173-vcodec-enc-vp8
              - mediatek,mt8173-vcodec-enc

    then:
      required:
        - mediatek,vpu

  - if:
      properties:
        compatible:
          enum:
            - mediatek,mt8173-vcodec-enc
            - mediatek,mt8192-vcodec-enc

    then:
      properties:
        clock:
          items:
            minItems: 1
            maxItems: 1
        clock-names:
          items:
            - const: venc_sel
    else:  # for vp8 hw decoder
      properties:
        clock:
          items:
            minItems: 1
            maxItems: 1
        clock-names:
          items:
            - const: venc_lt_sel

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8173-clk.h>
    #include <dt-bindings/memory/mt8173-larb-port.h>
    #include <dt-bindings/interrupt-controller/irq.h>

    vcodec_enc_avc: vcodec@18002000 {
      compatible = "mediatek,mt8173-vcodec-enc";
      reg = <0x18002000 0x1000>;
      interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_VENC_RCPU>,
             <&iommu M4U_PORT_VENC_REC>,
             <&iommu M4U_PORT_VENC_BSDMA>,
             <&iommu M4U_PORT_VENC_SV_COMV>,
             <&iommu M4U_PORT_VENC_RD_COMV>,
             <&iommu M4U_PORT_VENC_CUR_LUMA>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
             <&iommu M4U_PORT_VENC_REF_LUMA>,
             <&iommu M4U_PORT_VENC_REF_CHROMA>,
             <&iommu M4U_PORT_VENC_NBM_RDMA>,
             <&iommu M4U_PORT_VENC_NBM_WDMA>;
      mediatek,vpu = <&vpu>;
      clocks = <&topckgen CLK_TOP_VENC_SEL>;
      clock-names = "venc_sel";
      assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
    };

    vcodec_enc_vp8: vcodec@19002000 {
      compatible = "mediatek,mt8173-vcodec-enc-vp8";
      reg =  <0x19002000 0x1000>;	/* VENC_LT_SYS */
      interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
      iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
      mediatek,vpu = <&vpu>;
      clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
      clock-names = "venc_lt_sel";
      assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
      assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
    };
